Motorola PowerQUICC II MPC8280 Series Reference Manual page 998

FCC Protocol-Specific Mode Registers (FPSMRx)
Table 30-3 describes GFEMRx fields.
Bit Name
0 TIREM Transmit internal rate expanded mode (ATM mode)
0 Internal rate mode: Internal rate for PHYs[0-3] is controlled only by FTIRR[0-3]. FIRPER,
1 Internal rate expanded mode: PHYs[0-31] are controlled by FTIRR[0-3], FIRPER,
1 LPB RMII Loopback diagnostic mode (Ethernet mode):
0 Normal mode
1 Loopback mode
2 CLK RMII reference clock rate for 50 Mhz input clock from external oscillator (Ethernet mode):
0 50 Mhz (for Fast Ethernet)
1 5 Mhz (for 10BaseT)
3–7 — Reserved, should be cleared.
30.3 FCC Protocol-Specific Mode Registers (FPSMRx)
The functionality of the FCC varies according to the protocol selected by GFMR[MODE].
Each FCC has an additional 32-bit, memory-mapped, read/write protocol-specific mode
register (FPSMR) that configures them specifically for a chosen mode. The section for each
specific protocol describes the FPSMR bits.
30.4 FCC Data Synchronization Registers (FDSRx)
Each FCC has a 16-bit, memory-mapped, read/write data synchronization register (FDSR)
that specifies the pattern used in the frame synchronization procedure of the synchronous
protocols. In the totally transparent protocol, the FDSR should be programmed with the
preferred SYNC pattern. For Ethernet protocol, it should be programmed with 0xD555. For
the ATM protocol, FSDRx is used to generate a constant byte for the HEC. It does not
generate the HEC; instead it only outputs this constant byte as a 'placeholder' for the HEC.
This byte is then replaced by the ATM PHY with the actual value.
At reset, FDSRx defaults to 0x7E7E (two HDLC flags), so it does not need to be written
for HDLC mode. The FDSR contents are always sent lsb first.
30-8
Freescale Semiconductor, Inc.
Table 30-3. GFEMRx Field Descriptions
FIRSR_HI, FIRSR_LO, FITER are unused.
FIRSR_HI and FIRSR_LO. Underrun status for PHYs[0-31] is available by FIRER. This
bit should be set only in transmit master multi-PHY mode. In this mode mixing of internal
rate and external rate is not enabled.
MPC8280 PowerQUICC II Family Reference Manual
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