Motorola PowerQUICC II MPC8280 Series Reference Manual page 1447

end-to-end channel signalling, 34-75
transmit, 34-75
group start-up, 34-62
as initiator (TX), 34-63
as responder (RX), 34-64
IDCR operation, 34-73
IDCR mode group activation, 34-74
start-up, 34-73
link addition, 34-64
Rx steps, 34-64
TX parameters, 34-65
link receive deactivation procedure, 34-68
link receive reactivation, 34-68
link removal, 34-66
Rx steps, 34-66
TX parameters, 34-67
receive event response, 34-70
receive link start-up procedure, 34-61
test pattern, 34-72
as initiator (NE), 34-72
as responder (FE), 34-72
transmit event response, 34-69
transmit ICP cell signalling, 34-61
TRL on-the-fly change, 34-69
software responsibilities, 34-57
failure alarms, 34-60
general operation, 34-58
group symmetry control, 34-59
ICP end-to-end channel transmission, 34-59
link addition and slow recovery (LASR), 34-59
performance parameter measurement and
reporting, 34-60
receive group state machine control, 34-58
receive link state machine control, 34-58
SNMP MIBs, 34-60
system definition, 34-58
test pattern control, 34-60
transmit group state machine control, 34-59
transmit link state machine control, 34-59
IMMR (internal memory map register), 4-37
Input/output port memory map, 3-8
Instruction field conventions, xc
Instruction queue (IQ), 2-6
Instruction timing overview, 2-28
Instruction unit, 2-5
Integer unit (IU), 2-7
Interrupts
ATM interrupt queues, 31-85
RISC timer tables
interrupt handling, 14-29
SCC interrupt handling, 20-16
Inverse Multiplexing for ATM (IMA)
see IMA, 34-1
MOTOROLA
Freescale Semiconductor, Inc.
Index
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J
JTAG implementation, 13-5
L
L_TESCR1 (local bus transfer error status and control
register 1), 4-43
L_TESCR2 (local bus transfer error status and control
register 2), 4-44
L_TESCRx (local bus error status and control
registers), 11-34
LCL_ACR (local bus arbiter configuration register),
4-32
LCL_ALRH (local bus arbitration high-level register),
4-33
LCL_ALRL (local bus arbitration low-level register),
4-34
LDTEA (SDMA local bus transfer error address
register), 19-4
LDTEM (SDMA local bus transfer error MSNUM
register), 19-4
Load/store unit (LSU), 2-7
Loopback mode, 15-7
LSDMR (local bus SDRAM mode register), 11-25
LSRT (local bus-assigned SDRAM refresh timer)
register, 11-33
LURT (local bus-assigned UPM refresh timer)
register, 11-31
M
MCCE (MCC event) register, 29-38
MCCFx (MCC configuration registers), 29-34
MCCM (MCC mask) register, 29-38
MDR (memory data register), 11-29
Memory controller
address checking, 11-8
address latch enable (ALE), 11-12
address space checking, 11-8
architecture overview, 11-5
atomic bus operation, 11-10
basic architecture, 11-5
basic operation, 11-8
boot chip-select operation, 11-65
controlling the timing of GPL1, GPL2, and CSx,
11-73
CSx timing example, 11-73
delayed read, 11-11
EDO interface connection, MPC8280 to 60x bus,
11-97
error checking and correction (ECC), 11-9
external master support, 11-107
external support, 11-11
features common to all machines, 11-6
Index-13