Motorola PowerQUICC II MPC8280 Series Reference Manual page 492

SDRAM Machine
For bank-based interleaving, this means that the address bus should be partitioned as shown
in Table 11-26.
A[0–5]
msb of start address Internal bank select
The following parameters can be extracted:
• PSDMR[PBI] = 0
• ORx[BPD] = 01—4 internal banks
• ORx[ROWST] = 0100—row starts at A[8]
• ORx[NUMR] = 011—there are 12 row lines
Now, from the SDRAM device point of view, during an
port should look like Table 11-27
Table 11-27. SDRAM Device Address Port During
A[0–14]
—
Table 11-20. indicates that in order to multiplex A[6–19] over A[15–28] PSDMR[SDAM]
must be 001 and, because the internal bank selects are multiplexed over A[15–16]
PSDMR[BSMA] must be 010 (only the lower two bank select lines are used).
During a /
READ WRITE
Table 11-28. SDRAM Device Address Port During
A[0–14] A[15–16]
— Internal bank select
Because AP alternates with A[9] of the row lines, set PSDMR[SDA10] = 011. This outputs
A[9] on the SDA10 line during the ACTIVATE command and AP during READ/WRITE
and CBR commands.
Table 11-29. shows the register configuration. Not shown are PSRT and MPTPR, which
should be programmed according to the device refresh requirements.
Table 11-29. Register Settings (Bank-Based Interleaving)
Register
BRx BA Base address
PS00 = 64-bit port size
DECC00
WP0
MS010 = SDRAM-60x bus
11-54
Freescale Semiconductor, Inc.
Table 11-26. 60x Address Bus Partition
A[6–7] A[8–19]
.
A[15–16]
Internal bank select (A[6–7])
command, the address port should look like Table 11-28.
A[17]
Don't care
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A[20–28]
Row Column
ACTIVATE
ACTIVATE
A[17–28]
Row (A[8–19])
READ
A[18] A[19]
AP Don't care
Settings
EMEMC0
ATOM00
DR0
V 1
A[29–31]
lsb
command, its address
Command
A[29–31]
n.c.
/ Command
WRITE
A[20–28] A[29–31]
Column n.c.
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