Motorola PowerQUICC II MPC8280 Series Reference Manual page 1299

Freescale Semiconductor, Inc.
TC Layer Programming Mode
35.4.3 TC Layer Cell Counters
Each TC block maintains six memory-mapped 16-bit performance cell counters that are
updated during operation and can be read by the host. If a counter overflows, it wraps back
to zero and generates a maskable interrupt. These counters are automatically cleared when
read if TCMODE[CM] = 0; see Section 35.4.1.1, "TC Layer Mode Registers 1–8
(TCMODEx)."
35.4.3.1 Received Cell Counters 1–8 (TC_RCCx)
This cell counter is updated whenever a received cell without HEC errors is passed to the
Rx UTOPIA FIFO.
35.4.3.2 Transmitted Cell Counters 1–8 (TC_TCCx)
This cell counter is updated whenever the transmission of a cell is completed.
35.4.3.3 Errored Cell Counters 1–8 (TC_ECCx)
This cell counter is updated whenever a received errored cell (cell with header error) is
discarded.
35.4.3.4 Corrected Cell Counters 1–8 (TC_CCCx)
This cell counter is updated whenever a received cell with a HEC single bit error is
corrected. If header single bit error correction is not enabled (TCMODE[SBC] is set), this
counter is not updated. (All errored cells are counted by the errored cell counter (ECC).)
35.4.3.5 Transmitted IDLE Cell Counters 1–8 (TC_ICCx)
This cell counter is updated whenever an idle cell is transmitted.
35.4.3.6 Filtered Cell Counters 1–8 (TC_FCCx)
This cell counter is updated whenever an idle/unassigned cell is filtered (discarded). If cell
filters are not enabled (TCMODE[CF] is cleared), this counter is not updated.
35.4.4 Programming FCC2
FCC2 is designed to work with the TC blocks. The TC blocks are located on fixed addresses
on the UTOPIA bus internally. FCC2 should be programmed to work with the TC blocks
as if the TC blocks are external PHYs located on the lowest eight (or fewer) addresses.
MOTOROLA Chapter 35. ATM Transmission Convergence Layer 35-13
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