Motorola PowerQUICC II MPC8280 Series Reference Manual page 596

Dual-Port RAM
Figure 14-9 shows a memory map of the internal instruction RAM. Note that the addresses
refer to CPU address space.
0X20000
Bank #1
CPM Instruction
2K
0X20800
Bank #2
CPM Instruction
2K
0X21000
Bank #3
CPM Instruction
2K
0X21800
Bank #4
CPM Instruction
2K
0X22000
Bank #5
CPM Instruction
2K
0X22800
Bank #6
CPM Instruction
2K
0X23000
Bank #7
CPM Instruction
2K
0X23800
Bank #8
CPM Instruction
2K
14.5.1 Buffer Descriptors (BDs)
The peripheral controllers (FCCs, SCCs, SMCs, MCCs, SPI, and I
controlling buffers and their BD formats are all the same, as shown in Table 14-9.
14-22
Freescale Semiconductor, Inc.
0X24000
Bank #9
CPM Instruction
2K
0X24800
Bank #10
CPM Instruction
2K
0X25000
Bank #11
CPM Instruction
2K
0X25800
Bank #12
CPM Instruction
2K
0X26000
Bank #13
CPM Instruction/
Trace Buffer
2K
0X26800
Bank #14
CPM Instruction/
Trace Buffer
2K
0X27000
Bank #15
CPM Instruction/
Trace Buffer
2K
0X27800
Bank #16
CPM Instruction /
Trace Buffer
2K
Figure 14-9. Instruction RAM Partitioning
MPC8280 PowerQUICC II Family Reference Manual
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0X28000
0X2C000
Reserved
2 C) always use BDs for
Reserved
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