Motorola PowerQUICC II MPC8280 Series Reference Manual page 1052

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ATM-to-TDM Interworking
(RCT)." For the MCC receiver, set CHAMR[EP]; see Section 29.3.2.3, "Channel Mode
Register (CHAMR)—Transparent Mode."
31.9.2 Using Interrupts in Automatic Data Forwarding
The core can program the MCC and ATM interrupt mechanism to trigger interrupts for
events such as a buffer closing or transfer errors. The interrupt mechanism can be used to
synchronize the start of the automatic bridging process. For example, to start the MCC
transmitter after a specific buffer reaches the ATM receiver (the buffering is required to
cope with the ATM network's CDV), set ATM RxBD[I]. When the receive buffer is full,
the RxBD is closed, RxBD[E] is set (because it is operating in opposite E-bit polarity), and
the core is interrupted. The core then starts the MCC transmitter.
31.9.3 Timing Issues
Use of the TDM interface assumes that all communicating entities are synchronized (that
is, that they are using a synchronized serial clock). If the TDM interfaces are not
synchronized, a slip can occur in the reassembly buffer. If a buffer-not-ready event occurs
at the MCC transmitter, the user must restart the MCC transmit channel. If a
buffer-not-ready event occurs at the ATM transmitter, the user must restart the ATM
transmit channel.
31.9.4 Clock Synchronization (SRTS and Adaptive FIFOs)
Clock synchronization methods, such as using a time stamp (SRTS) or adaptive FIFOs,
prevent buffer slipping during reassembly. The SRTS method may be implemented using
external logic. The MPC8280 can read the SRTS from external logic and insert it into
AAL1 CES cells, and can track the SRTS from AAL1 CES cells and deliver it to external
logic. See Section 31.16, "SRTS Generation and Clock Recovery Using External Logic."
Alternatively, an adaptive FIFOs method can be implemented using the core to maintain the
bridging buffer at a mid-level point. The difference between the MCC and ATM data
pointers is a measure of buffer synchronization. The core calculates the difference between
pointers at regular intervals and adapts the TDM clock accordingly to hold the difference
constant.
31.9.5 Mapping TDM Time Slots to VCs
Using the MCC and the SI, any TDM time-slot combination can be routed to a specific data
buffer. (See Chapter 29, "Multi-Channel Controllers (MCCs)," and Chapter 15, "Serial
Interface with Time-Slot Assigner.") The same data buffers should be used by the ATM
controller to route receive and transmit data. For information about ATM buffers see
Section 31.10.5, "ATM Controller Buffer Descriptors (BDs)."
31-38 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA
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