Motorola PowerQUICC II MPC8280 Series Reference Manual page 656

CMX Registers
Table 16-5. CMXFCR Field Descriptions (continued)
Bits Name
21–23 TF3CS Transmit FCC3 clock source (NMSI mode). Ignored if FCC3 is connected to the TSA (FC3 = 1).
000 FCC3 transmit clock is BRG5.
001 FCC3 transmit clock is BRG6.
010 FCC3 transmit clock is BRG7.
011 FCC3 transmit clock is BRG8.
100 FCC3 transmit clock is CLK13.
101 FCC3 transmit clock is CLK14.
110 FCC3 transmit clock is CLK15.
111 FCC3 transmit clock is CLK16.
24–31 — Reserved, should be cleared
16.4.5 CMX SCC Clock Route Register (CMXSCR)
The CMX SCC clock route register (CMXSCR), seen in Figure 16-11, defines the
connection of the SCCs to the TSA and to the clock sources from the bank of clocks. This
register also enables the use of the external grant pin.
0 1 2
Field GR1 SC1
Reset
R/W
Addr
16 17 18
Field GR3 SC3
Reset
R/W
Addr
Figure 16-11. CMX SCC Clock Route Register (CMXSCR)
Table 16-6 describes CMXSCR fields.
Bits Name
0 GR1 Grant support of SCC1
0 SCC1 transmitter does not support the grant mechanism. The grant is always asserted internally.
1 SCC1 transmitter supports the grant mechanism as determined by the GMx bit of a serial device
channel.
1 SC1 SCC1 connection
0 SCC1 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O
control register.
1 SCC1 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.
16-16
Freescale Semiconductor, Inc.
4 5
RS1CS TS1CS
0000_0000_0000_0000
20 21
RS3CS TS3CS
0000_0000_0000_0000
Table 16-6. CMXSCR Field Descriptions
MPC8280 PowerQUICC II Family Reference Manual
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Description
7 8 9 10
GR2 SC2 RS2CS
R/W
0x11B08
23 24 25 26
GR4 SC4 RS4CS
R/W
0x11B0A
Description
12 13 15
TS2CS
28 29 31
TS4CS
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