Motorola PowerQUICC II MPC8280 Series Reference Manual page 493

Table 11-29. Register Settings (Bank-Based Interleaving) (continued)
Register
ORx SDAM 1111_1100_0000
LSDAM 00000
BPD 01
ROWST 010
PSDMR PBI 0
RFEN 1
OP 000
SDAM 001
BSMA 010
SDA10 011
RFRC from device data sheet
PRETOACT from device data sheet
11.5 General-Purpose Chip-Select Machine (GPCM)
Users familiar with the MPC8xx memory controller should read Section 11.5.4,
"Differences Between the MPC8xx GPCM and MPC82xx GPCM," first.
The GPCM allows a glueless and flexible interface between the MPC8280, SRAM,
EPROM, FEPROM, ROM devices, and external peripherals. The GPCM contains two
basic configuration register groups—BRx and ORx.
Although GPCM does not support bursting, the internal logic will split a burst into
individual beats that the GPCM can support. Therefore, the flash can be cached. Note that
if the MPC8280 is in 60x-bus compatible mode, BADDR[27–31] should be used instead of
A[27–31].
Table 11-30 lists the GPCM interface signals on the 60x and local bus.
60x Bus
PWE[0–7]
POE
GPCM-controlled devices can use BCTLx as read/write indicators. The BCTLx signals
appears as R/W in the timing diagrams. See Section 11.2.7, "Data Buffer Controls (BCTLx
and LWR)."
Additional control is available in 60x-compatible mode (60x bus only)—ALE–external
address latch enable
MOTOROLA
Freescale Semiconductor, Inc.
Table 11-30. GPCM Interfaces Signals
Local Bus
CS[0–11]
LWE[0–3]
LOE
Chapter 11. Memory Controller
For More Information On This Product,
Go to: www.freescale.com
General-Purpose Chip-Select Machine (GPCM)
Settings
NUMR 011
PMSEL 0
IBID 0
ACTTOROW from device data sheet
BL 0
LDOTOPRE from device data sheet
WRC from device data sheet
EAMUX 0
BUFCMD 0
CL from device data sheet
Comments
Device select
Write enables for write cycles
Output enable for read cycles
11-55