Motorola PowerQUICC II MPC8280 Series Reference Manual page 1138

ATM-to-TDM Adaptive Slip Control
MCC
channel
When the MCC
closes the BD, the
adaptive counter
CES adaptive threshold table address: CATB + MCC_Super_Channel*8
1. The MCC start threshold, in effect, implements a CDV jitter buffer.
2. MCC stop threshold should be programmed to (BD Table size -b) to prevent buffer underrun.
3. ATM stop threshold should be programmed to (BD Table size - a) to prevent buffer overrun.
4. The MCC and ATM stop thresholds determine the CDVT.
5. The ATM start threshold determines the time the ATM receiver waits before restarting synchronization process.
6. (MCC start - MCC stop) >= frame size.
7. b and a are integers less the BD table size.
Figure 32-14. Data Structure for ATM-to-TDM Adaptive Slip Control
32.5.1 CES Adaptive Threshold Tables
The CES adaptive threshold tables (see Table 32-15) reside in the dual-port RAM and hold
the CES thresholds on a per-VC basis. The CES adaptive threshold base (CATB), located
in the AAL1 CES parameter RAM, points to the base address of these tables. Each
AAL1-MCC channel has its own table with a starting address given by CATB +
RCT[Super_Channel_Number]# × 8.
0
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
Figure 32-15. CES Adaptive Threshold Table
32-18
Freescale Semiconductor, Inc.
Core
Count down
Adaptive counter (1)
ATM start threshold
ATM stop threshold
MCC start threshold
(CESAC) is
decremented
MCC stop threshold
NOTES
—
ATM Stop Threshold
MCC Stop Threshold
MPC8280 PowerQUICC II Family Reference Manual
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ATM
channel
Polling
Count up
When the ATM controller
closes the BD, the
adaptive counter
(CESAC) is
incremented
7 8
CES Adaptive Counter
ATM Start Threshold
MCC Start Threshold
—
15
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