Motorola PowerQUICC II MPC8280 Series Reference Manual page 1374

The SPI Buffer Descriptor (BD) Table
39.7.1.1 SPI Receive BD (RxBD)
The CP uses RxBDs to report on each received buffer. It closes the current buffer, generates
a maskable interrupt, and starts receiving data in the next buffer once the current buffer is
full. The CP also closes the buffer when the SPI is configured as a slave and SPISEL is
negated, indicating that reception stopped. The core should write RxBD bits before the SPI
is enabled. The format of an RxBD is shown in Figure 39-11.
0 1 2
Offset + 0 E — W
Offset + 2
Offset + 4
Offset + 6
Table 39-8 describes the RxBD status and control fields.
Table 39-8. SPI RxBD Status and Control Field Descriptions
Bits Name
0 E Empty.
0 The buffer is full or stopped receiving because of an error. The core can examine or write to any
fields of this RxBD, but the CP does not use this BD while E = 0.
1 The buffer is empty or reception is in progress. The CP owns this RxBD and its buffer. Once E is
set, the core should not write any fields of this RxBD.
1 — Reserved, should be cleared.
2 W Wrap (last BD in table).
0 Not the last BD in the RxBD table.
1 Last BD in the RxBD table. After this buffer is used, the CP receives incoming data using the BD
pointed to by RBASE (top of the table). The number of BDs in this table is determined only by the
W bit and overall space constraints of the dual-port RAM.
3 I Interrupt.
0 No interrupt is generated after this buffer is filled.
1 SPIE[RXB] is set when this buffer is full, indicating the need for the core to process the buffer.
SPIE[RXB] causes an interrupt if not masked.
4 L Last. Updated by the SPI when the buffer is closed because SPISEL was negated (slave mode only).
Otherwise, RxBD[ME] is set. The SPI updates L after received data is placed in the buffer.
0 This buffer does not contain the last character of the message.
1 This buffer contains the last character of the message.
5 — Reserved, should be cleared.
6 CM Continuous mode. Master mode only; in slave mode, CM should be cleared.
0 Normal operation.
1 The CP does not clear RxBD[E] after this BD is closed; the buffer is overwritten when the CP next
accesses this BD. This allows continuous reception from an SPI slave into one buffer for
autoscanning of a serial A/D peripheral with no core overhead.
7–13 — Reserved, should be cleared.
39-16
Freescale Semiconductor, Inc.
3 4 5 6
I L — CM
Rx Buffer Pointer
Figure 39-11. SPI RxBD
MPC8280 PowerQUICC II Family Reference Manual
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7 8 9 10
—
Data Length
Description
11 12 13 14 15
OV ME
MOTOROLA