Motorola PowerQUICC II MPC8280 Series Reference Manual page 583

to the MPC8280 in the form of RAM microcode packages. If preferred, the user can obtain
binary microcode from Motorola and load it into the dual-port RAM.
14.3.7 RISC Controller Configuration Register (RCCR)
The RISC controller configuration register (RCCR), as shown in Figure 14-3, configures
the CP to run microcode from ROM or RAM and controls the CP's internal timer.
0 1 2
Field TIME MCCPR
Reset
R/W
Addr
16
Field ERAM
Reset
R/W
Addr
Figure 14-3. RISC Controller Configuration Register (RCCR
RCCR bit fields are described in Table 14-3.
.
Table 14-3. RISC Controller Configuration Register Field Descriptions
Bits Name
0 TIME Timer enable. Enables the CP internal timer that generates a tick to the CP based on the value
programmed into the TIMEP field. TIME can be modified at any time to start or stop the scanning
of the RISC timer tables.
1 MCCPR MCC request priority. Controls the priority of the MCCs in relation to the other communication
peripherals. See Table13-2. "Peripheral Prioritization," for more information.
0 Original CPM priority scheme. MCCx priority behaves according to Table 13-2.
1 MCC priority remains at emergency level, priority level 4.
2–7 TIMEP Timer period controls the CP timer tick. The RISC timer tables are scanned on each timer tick and
the input to the timer tick generator is the general system clock (133/166MHZ) divided by 1,024.
The formula is (TIMEP + 1) × 1,024 = (general system clock period). Thus, a value of 0 stored in
these bits gives a timer tick of 1 × (1,024) = 1,024 general system clocks and a value of 63
(decimal) gives a timer tick of 64 × (1,024) = 65,536 general system clocks.
8, 9, 24, DRxM IDMAx request mode. Controls the IDMA request x (DREQx) sensitivity mode. DREQx is used to
25 activate IDMA channel x. See Section 19.7, "IDMA Interface Signals."
0 DREQx is edge sensitive (according to EDMx).
1 DREQx is level sensitive.
Note: When DRxM is set to level mode, EDMx determines if IDMA request is active high or active
low. Refer to description of RCCR[20–24].
Note: If RCCR[EIE] = 1, RCCR[DR1M] must be reset. No external interrupt occurs otherwise.
MOTOROLA Chapter 14. Communications Processor Module Overview
Freescale Semiconductor, Inc.
TIMEP
0000_0000_0000_0000
0x119C4
19 20 21 22
EDM1 EDM2 EDM3 EDM4 DR3M DR4M DR3QP DEM12 DEM34 DR4QP
0000_0000_0000_0000
0X119C6
For More Information On This Product,
Go to: www.freescale.com
Communications Processor (CP)
7 8 9 10 11
DR1M DR2M DR1QP
R/W
23 24 25 26 27
R/W
Description
12 13 14 15
EIE SCD DR2QP
28 29 30 31
14-9