Motorola PowerQUICC II MPC8280 Series Reference Manual page 1415

4. Write the corresponding SIMR (mask register) bit with a 1 to allow interrupts to be
generated to the core.
5. The pin value can be read at any time using PDATC.
After connecting CTS or CD to the SCC/FCC, the user must
also choose the normal operation mode in GSMR[DIAG] to
enable and disable SCC/FCC transmission and reception with
these pins.
The IDMA-DREQ signals on port C can assert an external request to the CP instead of
asserting an interrupt to the core. Each line can be programmed to assert an interrupt request
upon a high-to-low change or any change as configured in SIEXR.
Do not program the IDMAx-DREQ pins to assert external
requests to the IDMA, unless the IDMA is used. Otherwise,
erratic operation occurs.
MOTOROLA
Freescale Semiconductor, Inc.
NOTE
NOTE
Chapter 41. Parallel I/O Ports
For More Information On This Product,
Go to: www.freescale.com
Interrupts from Port C
41-21