Motorola PowerQUICC II MPC8280 Series Reference Manual page 1365

and SYSTEMCLK/2 in slave mode. Gaps should be inserted between multiple characters
to keep from exceeding the maximum sustained data rate.
39.4 Programming the SPI Registers
The following sections describe the registers used in configuring and operating the SPI.
39.4.1 SPI Mode Register (SPMODE)
The SPI mode register (SPMODE), shown in Figure 39-4, controls both the SPI operation
mode and clock source.
0 1 2
Field — LOOP CI
Reset 0000_00
R/W
Addr
Table 39-1 describes the SPMODE fields.
Bits Name
0 — Reserved, should be cleared.
1 LOOP Loop mode. Enables local loopback operation.
0 Normal operation.
1 Loopback mode. The transmitter output is internally connected to the receiver input. The receiver and
transmitter operate normally, except that received data is ignored.
2 CI Clock invert. Inverts SPI clock polarity. See Figure 39-5 and Figure 39-6.
0 The inactive state of SPICLK is low.
1 The inactive state of SPICLK is high.
3 CP Clock phase. Selects the transfer format. See Figure 39-5 and Figure 39-6.
0 SPICLK starts toggling at the middle of the data transfer.
1 SPICLK starts toggling at the beginning of the data transfer.
4 DIV16 Divide by 16. Selects the clock source for the SPI baud rate generator when configured as an SPI
master. In slave mode, SPICLK is the clock source.
0 BRGCLK is the input to the SPI BRG.
1 BRGCLK/16 is the input to the SPI BRG.
5 REV Reverse data. Determines the receive and transmit character bit order.
0 Reverse data—lsb of the character sent and received first.
1 Normal operation—msb of the character sent and received first.
6 M/S Master/slave. Selects master or slave mode.
0 The SPI is a slave.
1 The SPI is a master.
MOTOROLA
Freescale Semiconductor, Inc.
3 4 5 6
CP DIV16 REV M/S
—
Figure 39-4. SPMODE—SPI Mode Register
Table 39-1. SPMODE Field Descriptions
Chapter 39. Serial Peripheral Interface (SPI)
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Programming the SPI Registers
7 8 9 10
EN LEN
0_0000_0000
R/W
0x11AA0
Description
11 12 13 14 15
PM
39-7