Motorola PowerQUICC II MPC8280 Series Reference Manual page 1380

Features
The I 2 C receiver and transmitter are double-buffered, which corresponds to an effective
two-character FIFO latency. In normal operation, the transmitter shifts the msb (bit 0) out
first. When the I 2 C is not enabled in the I
little power.
40.1 Features
The following is a list of the I
• Two-signal interface (SDA and SCL)
• Support for master and slave I
• Multiple-master environment support
• Continuous transfer mode for automatic scanning of a peripheral
• Supports a maximum clock rate of 2,080 KHz (with a CPM utilization of 25%),
assuming a 100-MHz system clock.
• Independent, programmable baud-rate generator
• Supports 7-bit I
• Open-drain output signals allow multiple master configuration
• Local loopback capability for testing
40.2 I C Controller Clocking and Signal Functions
2
The I 2 C controller can be configured as a master or slave for the serial channel. As a master,
the controller's BRG provides the transfer clock. The I
clock (BRGCLK), which is generated from the CPM clock; see Section 10.4, "System
Clock Control Register (SCCR)."
SDA and SCL are bidirectional signals connected to a positive supply voltage through an
external pull-up resistor. When the bus is free, both signals are pulled high. The general I
master/slave configuration is shown in Figure 40-2.
Figure 40-2. I
40-2
Freescale Semiconductor, Inc.
2 C mode register (I2MOD[EN] = 0), it consumes
2 C controller's main features:
2 C operation
2 C addressing
Master
SCL
SDA
2
C Master/Slave General Configuration
MPC8280 PowerQUICC II Family Reference Manual
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2 C BRG takes its input from the BRG
V DD
Slave
SCL
(EEPROM, for example)
SDA
V DD
2 C
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