Motorola PowerQUICC II MPC8280 Series Reference Manual page 1019

– Block error detection code (BEDC
– Total receive cell
– Total receive cell
— Specifying channel code for F5 OAM cells
• ATM layer statistic gathering on a per PHY basis.
— UTOPIA receiver error cells count (Rx parity error or short/long cells error)
— Misinserted cell count
— CRC-10 error cells count (ABR flow only)
• Memory management
— RxBD table per VC with option of global free buffer pool for AAL5
— TxBD table per VC
31.2 ATM Controller Overview
The following sections provide an overview of the transmitter and receiver portions of the
ATM controller.
31.2.1 Transmitter Overview
Before the transmitter is enabled, the host must initialize the MPC8280 and create the
transmit data structure, described in Section 31.10, "ATM Memory Structure." When data
is ready for transmission, the host arranges the BD table and writes the pointer of the first
BD in the transmit connection table (TCT). The host issues an
which inserts the current channel to the ATM pace control (APC) unit. The APC unit
controls the ATM traffic of the transmitter. It reads the traffic parameters of each channel
and divides the total bandwidth among them. The APC unit can pace the peak cell rate,
peak-and-sustain cell rate (GCRA traffic) or peak-and-minimum cell rate traffic. The APC
implements up to eight priority levels for servicing real-time channels before non-real-time
channels.
The transmitter ATM cell is 53–65 bytes and includes 4 bytes of ATM cell header, a 1-byte
HEC, and 48 bytes of payload. The HEC is a constant taken from FDSRx[0–15] when using
UTOPIA 16 and from FDSRx[8–15] when using UTOPIA 8; see Section 30.4, "FCC Data
Synchronization Registers (FDSRx)." User-defined cells (UDC mode) include an extra
header of 1–12 bytes with an optional HEC octet. Cell transfers use the UTOPIA level II,
cell-level handshake.
Transmission starts when the APC schedules a channel. According to the channel code, the
ATM controller reads the channel's entry in the TCT and opens the first BD for
transmission. In auto-VC-off mode, the APC automatically deactivates the current channel
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
Freescale Semiconductor, Inc.
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ATM Controller Overview
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ATM TRANSMIT
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