Motorola PowerQUICC II MPC8280 Series Reference Manual page 628

Serial Interface Registers
Figure 15-17 shows the effects of changing FE when CE = 0 with no frame sync delay.
CE=0
L1CLK
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
Figure 15-17. Falling Edge (FE) Effect When CE = 0 and xFSD = 00
15.5.3 SIx RAM Shadow Address Registers (SIxRSR)
The SIx RAM shadow address registers (SIxRSR), shown in Figure 15-18, define the
starting addresses of the shadow section in the SIx RAM for each of the TDM channels.
15-24
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MPC8280 PowerQUICC II Family Reference Manual
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The L1ST is Driven from Sync.
Data is Driven From Clock High.
Rx Sampled Here
L1ST is Driven from Clock Low.
Both the Data and L1ST from Sync
when Asserted during Clock High.
Both the Data and L1ST from the Clock
when Asserted during Clock Low.
xFSD=00
(FE=1)
(FE=1)
(FE=0)
(FE=0)
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