Motorola PowerQUICC II MPC8280 Series Reference Manual page 560

TAP Controller
TDI
TRST
TMS
TCK
The TAP consists of the signals in Table 13-1.
.
Signal
TCK Test clock input to synchronize the test logic
TMS Test mode select input (with an internal pull-up resistor) that is sampled on the rising edge of TCK to sequence
the TAP controller's state machine
TDI Test data input (with an internal pull-up resistor) that is sampled on the rising edge of TCK
TDO Data output that can be three-stated and actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCK.
TRST Asynchronous reset with an internal pull-up resistor that provides initialization of the TAP controller and other
logic required by the standard
13.2 TAP Controller
The TAP controller is responsible for interpreting the sequence of logical values on the
TMS signal. It is a synchronous state machine that controls the operation of the JTAG logic.
13-2
Freescale Semiconductor, Inc.
Boundary Scan Register
Bypass
Instruction Apply & Decode Register
8
8–Bit Instruction Register
TAP Controller
Figure 13-1. Test Logic Block Diagram
Table 13-1. TAP Signals
MPC8280 PowerQUICC II Family Reference Manual
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M
U
X
0
Description
M
U
TDO
X
MOTOROLA