Motorola PowerQUICC II MPC8280 Series Reference Manual page 730

SCC Parameter RAM
20.3.5 Controlling SCC Timing with RTS, CTS, and CD
When GSMR_L[DIAG] is programmed to normal operation, CD and CTS are controlled
by the SCC. In the following subsections, it is assumed that GSMR_L[TCI] is zero,
implying normal transmit clock operation.
20.3.5.1 Synchronous Protocols
RTS is asserted when the SCC data is loaded into the Tx FIFO and a falling Tx clock occurs.
At this point, the SCC starts sending data once appropriate conditions occur on CTS. In all
cases, the first data bit is the start of the opening flag, sync pattern, or preamble.
Figure 20-9 shows that the delay between RTS and data is 0 bit times, regardless of
GSMR_H[CTSS]. This operation assumes that CTS is already asserted to the SCC or that
CTS is reprogrammed to be a parallel I/O line, in which case CTS to the SCC is always
asserted. RTS is negated one clock after the last bit in the frame.
TCLK
TXD
(Output)
RTS
(Output)
CTS
(Input)
NOTE:
1. A frame includes opening and closing flags and syncs, if present in the protocol.
Figure 20-9. Output Delay from RTS Asserted for Synchronous Protocols
When RTS is asserted, if CTS is not already asserted, delays to the first data bit depend on
when CTS is asserted. Figure 20-10 shows that the delay between CTS and the data can be
approximately 0.5 to 1 bit times or no delay, depending on GSMR_H[CTSS].
20-18
Freescale Semiconductor, Inc.
First Bit of Frame Data
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Last Bit of Frame Data
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