Motorola PowerQUICC II MPC8280 Series Reference Manual page 1305

Table 35-10. Programming the TC Layer Block
Init Values
TCMODE1 = 0xC202 Enable TC Layer Rx and Tx, no error correction on header, the TC is the only PHY on
UTOPIA
CDSMR1 = 0x3980 ALPHA = 7, DELTA = 6 (default values)
Step 6
Program the SI to retrieve the data bits (192 bits) out of the T1 frame (193 bits). The SI
frame pattern is programmed in the SI RAM (Rx or Tx), as shown in Table 18.
Table 35-11. Programming the SI RAM (Rx or Tx) for a T1 Application
Init Values
SI_RAM[00]=0x0000 1 bit is ignored.
SI_RAM[02]=0x015E Route 8 bytes to FCC2.
SI_RAM[04]=0x015E Route 8 bytes to FCC2.
SI_RAM[06]=0x015F Route 8 bytes to FCC2 and go back to the first entry in table.
Step 7
The last step in this example is to initialize the serial interface registers and enable
TDM—in this case TDMa on SI1 as shown in Table 19.
Table 35-12. Programming SI Registers to Enable TDM
Init Values
SI1AMR = 0x0040 Common Receive and Transmit Pins for TDMa
SI1GMR = 01 Enable TDMa
MOTOROLA
Freescale Semiconductor, Inc.
Chapter 35. ATM Transmission Convergence Layer
For More Information On This Product,
Go to: www.freescale.com
Implementation Example
Description
Description
Description
35-19