Motorola PowerQUICC II MPC8280 Series Reference Manual page 885

Table of Contents

Advertisement

Offset
Bit
Name
2
W
3
I
4
L
5
F
6–7
8–9
PID
10
11
NO
12
AB
13
CR
14
OV
15
MOTOROLA
Freescale Semiconductor, Inc.
Table 27-16. USB Rx BD Fields (continued)
Wrap (Final BD in table)
0 This is not the last BD in the Rx BD table.
1 This is the last BD in the Rx BD table. After this buffer has been used, the CP will
receive incoming data into the first BD in the table (the BD pointed to by RBASE).
The number of Rx BDs in this table is programmable and is determined only by the
W-bit and the overall space constraints of the dual-port RAM.
Interrupt
0 No interrupt is generated after this buffer has been filled.
1 The RXB bit in the USB event register will be set when this buffer has been
completely filled by the CP, indicating the need for the CPU core to process the
buffer. The RXB bit can cause an interrupt if it is enabled.
Last. This bit is set by the USB controller when the buffer is closed due to detection
of end-of-packet condition on the bus, or as a result of error. Written by the USB
controller after the received data has been placed into the associated data buffer.
0 Buffer does not contain the last byte of the message.
1 Buffer contains the last byte of the message.
First. This bit is set by the USB controller when the buffer contains the first byte of a
packet. Written by the USB controller after the received data has been placed into the
associated data buffer.
0 Buffer does not contain the first byte of the message
1 Buffer contains the first byte of the message
Reserved, should be cleared
Packet ID. This bit field is set by the USB controller to indicate the type of the packet.
This bit is valid only if the USB RXBD[F] is set. Written by the USB controller after the
received data has been placed into the associated data buffer.
00 Buffer contains DATA0 packet
01 Buffer contains DATA1 packet
10 Buffer contains SETUP packet. This option can never be set on host RxBD
Reserved, should be cleared
Rx non-octet aligned packet. A packet that contained a number of bits not exactly
divisible by eight was received. Written by the USB controller after the received data
has been placed into the associated data buffer.
Frame aborted. Bit stuff error occurred during reception. Written by the USB controller
after the received data has been placed into the associated data buffer.
CRC error. This frame contains a CRC error. The received CRC bytes are always
written to the receive buffer. Written by the USB controller after the received data has
been placed into the associated data buffer.
Overrun. A receiver overrun occurred during reception. Written by the USB controller
after the received data has been placed into the associated data buffer.
Reserved, should be cleared
Chapter 27. Universal Serial Bus Controller
For More Information On This Product,
Go to: www.freescale.com
USB Buffer Descriptor Ring
Description
27-27

Advertisement

Table of Contents
loading

This manual is also suitable for:

Powerquicc ii mpc8270Powerquicc ii mpc8275Powerquicc ii mpc8280

Table of Contents