Motorola PowerQUICC II MPC8280 Series Reference Manual page 1417

Appendix A
Register Quick Reference Guide
A0
This section provides a brief guide to the core registers.
A.1 PowerPC Registers—User Registers
The implements the user-level registers defined by the PowerPC architecture except those
required for supporting floating-point operations (the floating-point register file (FPRs) and
the floating-point status and control register (FPSCR)). User-level, PowerPC registers are
listed in Table A-1 and Table A-2. Table A-2 lists user-level special-purpose registers
(SPRs).
Table A-1. User-Level PowerPC Registers (non-SPRs)
Description Name
General-purpose GPRs The thirty-two 32-bit (GPRs) are used for source
registers
Condition register CR
Table A-2. lists SPRs defined by the PowerPC architecture implemented on the MPC8280.
SPR Number
Decimal SPR [5–9] SPR [0–4]
1 00000 00001
8 00000 01000
9 00000 01001
268 01000 01100
269 01000 01101
1
Extended opcode for mftb, 371 rather than 339.
2
Any write (mtspr) to this address causes an implementation-dependent software emulation exception.
MOTOROLA
Freescale Semiconductor, Inc.
Comments
and destination operands.
See the Programming Environments Manual
Table A-2. User-Level PowerPC SPRs
Name Comments
XER See the Programming
Environments Manual
LR See the Programming
Environments Manual
CTR See the Programming
Environments Manual
1
TBL read See the Programming
Environments Manual
2
TBU read
Appendix A. Register Quick Reference Guide
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Access Level Serialize Access
User —
User Only mtcrf
Serialize Access
Write: Full sync
Read: Sync relative to load/store operations
No
No
Write (as a store)
A-1