Motorola PowerQUICC II MPC8280 Series Reference Manual page 1134

Interworking Functions
Table 32-1 describes CAS routing table entry fields.
Table 32-1. CAS Routing Table Entry Field Descriptions
Bits Name
0 W Wrap bit. When set, this bit indicates the last circular table entry. During initialization, the host must clear
all W bits in the table except the last one, which must be set.
1 — Reserved, should be cleared during initialization.
2 F/S First/Second.
0 Indicates that the signaling information occupies the first nibble in the CAS block (LSB).
1 Indicates that the signaling information occupies the second nibble in the CAS block (MSB).
3-7 SOP Signaling Offset Pointer. Offset of the signaling nibble from the internal CAS base address.
Note that in ESF mode the maximum offset is 23 and in E1 framing format the maximum offset is 31.
32.4.7.2 TDM-to-ATM CAS Support
During the segmentation process, the AAL1 CES transmitter reads the CAS data from the
internal CAS block and packs the data and the signaling information at the end of an AAL1
super frame (depicted in Figure 32-3). All AAL1 functions operate normally (generating
AAL1 PDU-headers, structured pointers, etc.). Each common (MCC, ATM) BD table
should point to buffers that can contain a whole number of super frames. The last buffer of
the super frame is marked as the end of a super frame (BD[EOSF]=1). After closing a buffer
with the EOSF indication, the ATM transmitter processes the CAS data—reads it from the
internal CAS block and inserts it into the cell payload at the transmit side. The EOSF
indication in the BD is statically set by the CPU when initializing the BD table.
Data I/F
MCC
T1/E1 framer
UTOPIA
ATM
interface
Transmit
Shown in
CAS routing
Figure 1-10
table
CAS serial I/F
MCC
T1/E1 framer
The CAS block is automatically written to internal RAM by the MCC receiver using a
separate TDM. When a super frame is received the MCC should be triggered with a
32-14
Freescale Semiconductor, Inc.
MCC
Rx pointer
Rx
ATM
Tx pointer
Tx
Rx
Note: With CAS only 4 T1/E1 are supported.
Figure 32-12. CAS Flow TDM-to-ATM
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Description
BD table per VC
EOSF
EOSF
Incoming CAS block per trunk
(internal RAM)
Buffer 1
Super
frame
Buffer 2
Buffer 3
Super
frame
Buffer 4
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