Motorola PowerQUICC II MPC8280 Series Reference Manual page 1101

Table 31-43. Interrupt Queue Parameter Table
1
Offset Name Width
0x00 INTQ_BASE
0x04 INTQ_PTR
0x08 INT_CNT Half Word Interrupt counter. Initialize with INT_ICNT. The CP decrements INT_CNT for each
0x0A INT_ICNT Half Word Interrupt initial count. User-defined global interrupt threshold—the number of
0x0C INTQ_ENTRY
Offset from INTT_BASE+RCT/TCT[INTQ] × 16
1
31.12 The UTOPIA Interface
The ATM controller interfaces with a PHY device through the UTOPIA interface. The
MPC8280 supports UTOPIA level 2 for both master and slave modes.
31.12.1 UTOPIA Interface Master Mode
Cell transfer on an ATM device (with single or multiple PHYs) uses cell-level handshaking
as defined in the UTOPIA standards. The FCC does not pause cell transmission by the PHY
and does not stop receiving cells from the PHY.
UTOPIA master signals are shown in Figure 31-57.
MPC8280
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
Freescale Semiconductor, Inc.
Word Base address of the interrupt queue. User-defined.
Word Pointer to interrupt queue entry. Initialize to INTQ_BASE.
interrupt. When INT_CNT reaches zero, the queue's global interrupt flag
FCCE[GINTx] is set.
interrupts required before the CP issues a global interrupt (FCCE[GINTx]).
Word Interrupt queue entry. Must be initialized to the entry pointed to by INTQ_PTR,
which is initially the first empty entry of the queue. Note that after an overrun
occurs, this entry must be reset to the entry pointed to by INTQ_PTR to reenable
interrupt processing.
TXDATA[15–0]/[7–0]
TxSOC
TXENB
TXPRTY
TXCLK
TXCLAV[3–0]/TxClav
TXADD[4–0]
Figure 31-57. UTOPIA Master Mode Signals
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The UTOPIA Interface
Description
RXDATA[15–0]/[7–0]
RXSOC
RXENB
MPC8280 RXPRTY
RXCLK
RXCLAV[3–0]/RxClav
RXADD[4–0]
31-87