Motorola PowerQUICC II MPC8280 Series Reference Manual page 1137

Freescale Semiconductor, Inc.
ATM-to-TDM Adaptive Slip Control
Overrun occurs when the MCC transmitter fetches data from the common BD table at a
slower rate than it is being filled by the ATM receiver. In this case, the ATM write pointer
meets the MCC read pointer and a BSY state is declared (an entry is added to the ATM
interrupt table) on the ATM side.
Underrun occurs when the MCC transmitter fetches data from the common BD table at a
higher rate than it is being filled by the ATM receiver. In this case, the MCC read pointer
reaches a BD that is not ready and a buffer-not-ready state is declared on the MCC side.
In both slip cases, the MCC and ATM controller automatically recover and restart the
ATM-to-TDM interworking function.
In order to prevent overrun and underrun conditions, the MPC8280 maintains an adaptive
slip control using a set of 4 threshold pointers for each ATM-TDM (VC - super channel)
connection.
The pre-underrun state (shown in Figure 32-14) occurs when the MCC read pointer goes
faster than the ATM write pointer. When the adaptive counter reaches the MCC_Stop
threshold, the MCC read pointer does not advance. At this point, the current BD (or the
underrun template) is retransmitted a multiple of the frame size. In the meantime, the ATM
receiver continues to receive valid data and advance the ATM write pointer. When the
adaptive counter reaches the MCC_start threshold and the MCC has finished sending a
multiple of the frame size, the MCC starts to transmit the valid received data and advance
the MCC read pointer.
Note that when the pre-underrun state occurs, the MCC transmitter can transmit the last
buffer continuously or the underrun template. This is determined by the MCC channel
configuration; see the CHAMR[UTM] bit description in Section 29.3.2.3, "Channel Mode
Register (CHAMR)—Transparent Mode." In the example shown in Figure 32-14, the MCC
is programmed to send the current BD during the pre-underrun condition.
The pre-overrun state occurs when the ATM write pointer goes faster than the MCC read
pointer. When the adaptive counter reaches the ATM_Stop threshold, the ATM write pointer
does not advance. The ATM receiver waits until the adaptive counter reaches the ATM_start
threshold. In the meantime, the MCC read pointer continues to process valid data from the
common BD table. When CESAC reaches the ATM start threshold, the ATM write pointer
advances to the first BD after the one that marked with EOSF (in CAS mode). When this
BD is ready, the ATM receiver begins the resynchronization process: for unstructured
AAL1 type the ATM receiver waits for the first valid cell, and for structured AAL1 type the
receiver waits for the first valid cell that contains a valid pointer. The first received octet
becomes the first byte of the new BD (new super frame).
Note that this implementation for slip control provides a good interface for an adaptive
FIFO implemented in software. CESAC represents the difference between the ATM and
MCC pointers; the software application need only convert this value into an SRTS format.
Figure 32-14 shows the 8-byte data structure used to implement ATM-to-TDM slip control.
(Three of the bytes are unused.)
MOTOROLA Chapter 32. ATM AAL1 Circuit Emulation Service 32-17
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