Motorola PowerQUICC II MPC8280 Series Reference Manual page 1165

0
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
Offset + 0x0C
Offset + 0x0E
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
Offset + 0x1A
Offset + 0x1C
Offset + 0x1E
Figure 32-31. AAL1 Sequence Number (SN) Protection Table
32.15 Internal AAL1 CES Statistics Tables
An AAL1 CES statistics table, shown in Table 32-14, resides in the dual-port RAM and
holds AAL1 CES statistics on a per-VC basis. AAL1_Int_STATT_BASE points to the base
address of these tables. Each AAL1 channel has its own table with a starting address given
by AAL1_Int_STATT_BASE + ATM_CHANNEL# × 8.
Table 32-14. AAL1 CES DPR Statistics Table
Offset Name
0x00 Rx_AAL1_VALID
0x02 Rx_AAL1_BOV
0x04 Tx_AAL1_VALID
0x06 Tx_AAL1_BUN
MOTOROLA
Freescale Semiconductor, Inc.
Width
Hword 16-bit cyclic counter. Counts the total received AAL1 cells delivered to the
receive buffers. This counter includes the tag cells (with SCE, SNE).
Hword 16-bit cyclic counter. Counts the number of ATM buffer-pre overrun events i.e
the ATM write pointer reaches the ATM_STOP threshold.See Section 32.5,
"ATM-to-TDM Adaptive Slip Control."
Hword 16-bit cyclic counter. Counts the transmitted AAL1 cells.
Hword 16-bit cyclic counter. Counts the number of ATM buffer underrun events. See
Section 32.4.1.2, "TDM-to-ATM."
Chapter 32. ATM AAL1 Circuit Emulation Service
For More Information On This Product,
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Internal AAL1 CES Statistics Tables
0x0000
0x0007
0x000D
0x000A
0x000E
0x0009
0x0003
0x0004
0x000B
0x000C
0x0006
0x0001
0x0005
0x0002
0x0008
0x000F
Description
15
32-45