Motorola PowerQUICC II MPC8280 Series Reference Manual page 1099

31.11 ATM Exceptions
The ATM controller interrupt handling involves two principal data structures: FCCEs (FCC
event registers) and circular interrupt queues.
Four priority interrupt queues are available. By programming RCT[INTQ] and
TCT[INTQ], the user determines which queue receives the interrupt. Channel Rx buffer,
Rx frame, or Tx buffer events can be masked by clearing interrupt mask bits in RCT and
TCT.
After an interrupt request, the host reads FCCE. If FCCE[GINTx] = 1, at least one entry
was added to one of the interrupt queues. After clearing FCCE[GINTx], the host processes
the valid interrupt queue entries and clears each entry's valid bit. The host follows this
procedure until it reaches an entry with V = 0. See Section 31.11.2, "Interrupt Queue
Entry."
The host controls the number of interrupts sent to the core using a down counter in the
interrupt queue's parameter table; see Section 31.11.3. For each event sent to an interrupt
queue, a counter (that has been initialized to a threshold number of interrupts) is
decremented. When the counter reaches zero, the global interrupt, FCCE[GINTx], is set.
31.11.1 Interrupt Queues
Interrupt queues are located in external memory. The parameters of each queue are stored
in a table. See Section 31.11.3, "Interrupt Queue Parameter Tables."
When an interrupt occurs, the CP writes a new entry to the interrupt queue, the V bit is set,
and the queue pointer (INTQ_PTR) is incremented. Once the CP uses an entry with W = 1,
it returns to the first entry in the queue. If the CP tries to overwrite a valid entry (V = 1), an
overflow condition occurs and the queue's overflow flag, FCCE[INTOx], is set.
The interrupt queue structure is displayed in Figure 31-55.
INTQ_BASE
Software (Core) Pointer
INTQ_PTR
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
Freescale Semiconductor, Inc.
V = 0 W = 0
V = 0 W = 0
V = 0 W = 0
V = 1 W = 0
V = 1 W = 0
V = 1 W = 0
V = 0 W = 0
V = 0 W = 0
V = 0 W = 1
Figure 31-55. Interrupt Queue Structure
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ATM Exceptions
Word
Invalid
Invalid
Invalid
Interrupt Entry
Interrupt Entry
Interrupt Entry
Invalid
Invalid
Invalid
31-85