Motorola PowerQUICC II MPC8280 Series Reference Manual page 936

The SMC in GCI Mode
28.5.6 SMC GCI Monitor Channel TxBD
The CP uses this BD, shown in Figure 28-16, to report about the monitor channel transmit
byte.
0 1 2
Offset + 0 R L AR
Table 28-20 describes SMC monitor channel TxBD fields.
Table 28-20. SMC Monitor Channel TxBD Field Descriptions
Bits Name
0 R Ready.
0 Cleared by the CP after transmission. The TxBD is now available to the core.
1 Set by the core when the data byte associated with this BD is ready for transmission.
1 L Last (EOM). Valid only for monitor channel protocol. When L = 1, the SMC first transmits the buffer
data and then transmits the EOM indication on the E bit.
2 AR Abort request. Valid only for monitor channel protocol. Set by the SMC when an abort request is
received on the A bit. The transmitter sends the EOM on the E bit after receiving an abort request.
3–7 — Reserved, should be cleared.
8–15 DATA Data field. Contains the data to be sent by the SMC on the monitor channel.
28.5.7 SMC GCI C/I Channel RxBD
The CP uses this BD, seen in Figure 28-17, to report information about the C/I channel
receive byte.
0 1
Offset + 0 E
Table 28-21 describes SMC C/I channel RxBD fields.
Table 28-21. SMC C/I Channel RxBD Field Descriptions
Bits Name
0 E Empty.
0 Cleared by the CP to indicate that the byte associated with this BD is available to the core.
1 The core sets E to indicate that the byte associated with this BD has been read.
Note that additional data received is discarded until E bit is set.
1–7 — Reserved, should be cleared.
8–13 C/I Command/indication data bits. For C/I channel 0, bits 10–13 contain the 4-bit data field and bits 8–9
DATA are always written with zeros. For C/I channel 1, bits 8–13 contain the 6-bit data field.
14–15 — Reserved, should be cleared.
28-36
Freescale Semiconductor, Inc.
3
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Figure 28-16. SMC Monitor Channel TxBD
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Figure 28-17. SMC C/I Channel RxBD
MPC8280 PowerQUICC II Family Reference Manual
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7 8
DATA
Description
7 8
C/I DATA
Description
15
13 14 15
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