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Motorola MC68340 User Manual

Integrated processor with dma.
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Freescale Semiconductor, Inc.
µ MOTOROLA
MC68340
Integrated Processor with DMA
User's Manual
©MOTOROLA INC., 1992
For More Information On This Product,
Go to: www.freescale.com

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   Summary of Contents for Motorola MC68340

  • Page 1

    Freescale Semiconductor, Inc. µ MOTOROLA MC68340 Integrated Processor with DMA User’s Manual ©MOTOROLA INC., 1992 For More Information On This Product, Go to: www.freescale.com...

  • Page 2

    Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.

  • Page 3

    MC68340; the MC68000 Family Programmer’s Reference Manual provides instruction details for the MC68340; and the MC68340 Integrated Processor with DMA Product Brief provides a brief description of the MC68340 capabilities. This user’s manual is organized as follows:...

  • Page 4: Table Of Contents

    Function Codes (FC3–FC0)................2-5 Chip Selects ( CS3 – CS0 ) ................2-5 Interrupt Request Level ( IRQ7 , IRQ6 , IRQ5 , IRQ3 ) ........2-6 MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 5

    2.14 Timer Signals ....................2-12 Timer Gate ( TGATE2 , TGATE1 )..............2-12 2.14.1 2.14.2 Timer Input (TIN2, TIN1) ................2-12 2.14.3 Timer Output (TOUT2, TOUT1)..............2-12 MC68340 USER'S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 6

    Synchronous Operation with DSACK ............. 3-14 3.2.5 3.2.6 Fast Termination Cycles................3-15 Data Transfer Cycles..................3-16 3.3.1 Read Cycle..................... 3-16 3.3.2 Write Cycle..................... 3-18 3.3.3 Read-Modify-Write Cycle................3-19 MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 7

    Clock Synthesizer Operation..............4-9 4.2.3.1 Phase Comparator and Filter ..............4-11 4.2.3.2 Frequency Divider ..................4-12 4.2.3.3 Clock Control..................... 4-13 4.2.4 Chip Select Operation ................. 4-13 4.2.4.1 Programmable Features................4-14 MC68340 USER'S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 8

    Port B Pin Assignment Register (PPARB) ..........4-35 4.3.5.6 Port B Data Direction Register (DDRB)..........4-35 4.3.5.7 Port B Data Register (PORTB, PORTB1) ..........4-35 MC68340 Initialization Sequence..............4-36 4.4.1 Startup ......................4-36 4.4.2 SIM40 Module Configuration ..............4-36 4.4.3 SIM40 Example Configuration Code............

  • Page 9

    Pipeline Synchronization with the NOP Instruction........ 5-36 Processing States..................... 5-36 5.4.1 State Transitions................... 5-37 5.4.2 Privilege Levels..................... 5-37 5.4.2.1 Supervisor Privilege Level..............5-37 5.4.2.2 User Privilege Level................. 5-39 viii MC68340 USER'S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 10

    Bus Error Stack Frame................5-60 Development Support..................5-63 5.6.1 CPU32 Integrated Development Support..........5-63 5.6.1.1 Background Debug Mode (BDM) Overview ........5-64 5.6.1.2 Deterministic Opcode Tracking Overview..........5-64 MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 11

    Instruction Pipe ( IPIPE )................5-87 5.6.3.2 5.6.3.3 Opcode Tracking during Loop Mode ............ 5-88 Instruction Execution Timing................5-88 5.7.1 Resource Scheduling .................. 5-88 5.7.1.1 Microsequencer ..................5-89 5.7.1.2 Instruction Pipeline................... 5-89 MC68340 USER'S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 12

    Internal Request Generation............... 6-4 6.3.1.1 Internal Request, Maximum Rate............6-5 6.3.1.2 Internal Request, Limited Rate ............... 6-5 6.3.2 External Request Generation ..............6-5 6.3.2.1 External Burst Mode................. 6-5 MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 13

    7.1.1 Serial Communication Channels A and B..........7-3 7.1.2 Baud Rate Generator Logic ................ 7-3 7.1.3 Internal Channel Control Logic..............7-3 7.1.4 Interrupt Control Logic ................. 7-3 MC68340 USER'S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 14

    Read Cycles....................7-17 7.3.5.2 Write Cycles....................7-17 7.3.5.3 Interrupt Acknowledge Cycles..............7-17 Register Description and Programming ............7-17 7.4.1 Register Description..................7-17 7.4.1.1 Module Configuration Register (MCR)..........7-19 MOTOROLA MC68340 USER'S MANUAL xiii For More Information On This Product, Go to: www.freescale.com...

  • Page 15

    Timer Gate ( TGATE1 , TGATE2 )..............8-6 8.2.2 8.2.3 Timer Output (TOUT1, TOUT2)..............8-6 Operating Modes ....................8-6 8.3.1 Input Capture/Output Compare..............8-6 8.3.2 Square-Wave Generator................8-8 MC68340 USER'S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 16

    9.4.1 EXTEST (000) ....................9-10 9.4.2 SAMPLE/PRELOAD (001) ................9-10 9.4.3 BYPASS (X1X, 101)..................9-11 9.4.4 HI-Z (100) ....................... 9-11 MC68340 Restrictions..................9-11 Non-IEEE 1149.1 Operation................9-12 Section 10 Applications 10.1 Minimum System Configuration..............10-1 10.1.1 Processor Clock Circuitry................10-1...

  • Page 17

    10.2.4 Interfacing an 8-Bit Device to 16-Bit Memory Using Single-Address DMA Mode..............10-10 10.3 Power Consumption Considerations............10-10 10.3.1 MC68340 Power Reduction at 5V ............10-11 10.3.2 MC68340V (3.3 V) ..................10-13 Section 11 Electrical Characteristics 11.1 Maximum Rating ..................... 11-1 11.2...

  • Page 18

    Block Diagram......................1-1 Functional Signal Groups ..................2-1 Input Sample Window.................... 3-2 MC68340 Interface to Various Port Sizes............3-7 Long-Word Operand Read Timing from 8-Bit Port..........3-11 Long-Word Operand Write Timing to 8-Bit Port..........3-12 Long-Word and Word Read and Write Timing—16-Bit Port ......3-13 Fast Termination Timing..................

  • Page 19

    LIST OF ILLUSTRATIONS (Continued) Figure P a g e Number Title Number MC68340 Crystal Oscillator.................. 4-10 Clock Block Diagram for External Oscillator Operation........4-11 Full Interrupt Request Multiplexer................ 4-16 SIM40 Programming Model.................. 4-19 CPU32 Block Diagram................... 5-3 Loop Mode Instruction Sequence ............... 5-3 User Programming Model..................

  • Page 20

    Period Measurement Mode .................. 8-14 8-10 Event Count Mode....................8-15 8-11 Timer Module Programming Model..............8-18 Test Access Port Block Diagram................9-2 TAP Controller State Machine................9-3 MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 21

    Single-Address DMA Mode................10-10 10-15 MC68340 Current vs. Activity at 5 V..............10-11 10-16 MC68340 Current vs. Voltage/Temperature............ 10-12 10-17 MC68340 Current vs. Clock Frequency at 5 V..........10-12 11-1 Drive Levels and Test Points for AC Specifications........11-4 11-2 Read Cycle Timing Diagram................

  • Page 22

    11-18 Serial Module Synchronous Mode Timing Diagram ........11-23 11-19 Test Clock Input Timing Diagram............... 11-25 11-20 Boundary Scan Timing Diagram ............... 11-26 11-21 Test Access Port Timing Diagram..............11-26 MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 23

    5-10 Program Control Operations................. 5-26 5-11 System Control Operations................... 5-28 5-12 Condition Tests ....................... 5-29 5-13 Standard Usage Entries..................5-30 5-14 Compressed Table Entries ................... 5-32 xxii MC68340 USER'S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 24

    Boundary Scan Control Bits ................. 9-4 Boundary Scan Bit Definitions ................9-5 Instructions....................... 9-10 10-1 Memory Access Times at 16.78 MHz..............10-7 10-2 Typical Electrical Characteristics............... 10-13 MOTOROLA MC68340 USER'S MANUAL xxiii For More Information On This Product, Go to: www.freescale.com...

  • Page 25: Device Overview

    The MC68340 CPU32 delivers 32-bit CISC processor performance from a lower cost 16-bit memory system. The combination of peripherals offered in the MC68340 can be found in a diverse range of microprocessor-based systems, including embedded control and general computing.

  • Page 26: M68300 Family

    • 144-Pin Ceramic Quad Flat Pack (CQFP) or 145-Pin Plastic Pin Grid Array (PGA) As a low voltage part, the MC68340V can operate with a 3.3-V power supply. MC68340 is used throughout this manual to refer to both the low voltage and standard 5-V parts since both are functionally equivalent.

  • Page 27: Organization

    The CPU32 is a powerful central processor that supervises system functions, makes decisions, manipulates data, and directs I/O. A special debugging mode simplifies processor emulation during system debug. MOTOROLA MC68340 USER’S MANUAL 1- 3 For More Information On This Product, Go to: www.freescale.com...

  • Page 28: Cpu32

    Position-independent code is easily written. The CPU32 is specially optimized to run with the MC68340's 16-bit data bus. Most instructions execute in one-half the number of clocks compared to the original MC68000, yielding an overall 1.6 times the performance of the same-speed MC68000 and measuring 10,045 Dhrystones/sec 25.16 MHz (6,742 Dhrystones/sec...

  • Page 29: On-chip Peripherals

    To improve total system throughput and reduce part count, board size, and cost of system implementation, the M68300 family integrates on-chip, intelligent peripheral modules and typical glue logic. These functions on the MC68340 include the SIM40, a DMA controller, a serial module, and two timers.

  • Page 30: System Configuration And Protection

    1.3.1.2 SYSTEM CONFIGURATION AND PROTECTION. The M68000 family of processors is designed with the concept of providing maximum system safeguards. System configuration and various monitors and timers are provided in the MC68340. Power-on reset circuitry is a part of the SIM40. A bus monitor ensures that the system does not lock up when there is no response to a memory access.

  • Page 31: Ieee 1149.1 Test Access Port

    Freescale Semiconductor, Inc. 1.3.1.7 IEEE 1149.1 TEST ACCESS PORT. To aid in system diagnostics, the MC68340 includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1 standard for boundary scan testability, often referred to as JTAG (Joint Test Action Group).

  • Page 32: Timer Modules

    The MC68340 has two, identical, versatile, on-chip counter/timers as well as a simple timer in the SIM40. These general-purpose counter/timers can be used for precisely timed events without the errors to which software-based counters and timers are susceptible—...

  • Page 33: Physical

    SIM40's periodic interrupt timer. 1.5 PHYSICAL The MC68340 is available as 0–16.78 MHz and 0–25.16 MHz, 0 C to +70 C and -40 C to +85 C, and 5.0 V 5% and 3.3 V 0.3 supply voltages (reduced frequencies at 3.3 V) Thirty-two power and ground leads minimize ground bounce and ensure proper isolation of different sections of the chip, including the clock oscillator.

  • Page 34: More Information

    Freescale Semiconductor, Inc. 1.7 MORE INFORMATION The following table lists available documentation related to the MC68340: Document Number Document Name BR1114/D M68300 Integrated Processor Family MC68340 Technical Summary MC68340/D MC68340UM/AD MC68340 User's Manual M68000 Family Programmer's Reference Manual M68000PM/AD AN1063/D...

  • Page 35: Signal Descriptions

    Freescale Semiconductor, Inc. SECTION 2 SIGNAL DESCRIPTIONS This section contains brief descriptions of the MC68340 input and output signals in their functional groups as shown in Figure 2-1. A31/PORT A7/IACK7 A30/PORT A6/IACK6 A29/PORT A5/IACK5 A28/PORT A4/IACK4 PORT A A27/PORT A3/IACK3...

  • Page 36: Signal Index

    Freescale Semiconductor, Inc. 2.1 SIGNAL INDEX The input and output signals for the MC68340 are listed in Table 2-1. The name, mnemonic, and brief functional description are presented. For more detail on each signal, refer to the signal paragraph. Guaranteed timing specifications for the signals listed in Table 2-1 can be found in Section 11 Electrical Characteristics.

  • Page 37

    V CCSYN Quiet power supply to VCO; also used to control — synthesizer mode after reset. System Power Supply V CC , GND Power supply and ground to the MC68340 — and Ground MOTOROLA MC68340 USER’S MANUAL 2- 3 For More Information On This Product,...

  • Page 38: Address Bus

    This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or from the MC68340. A read or write operation may transfer 8 or 16 bits of data (one or two bytes) in one bus cycle. During a read cycle, the data is latched by the MC68340 on the MC68340 USER’S MANUAL...

  • Page 39: Function Codes (fc3-fc0)

    For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MC68340 places the data on the data bus approximately one-half clock cycle after AS is asserted in a write cycle.

  • Page 40: Interrupt Request Level (irq7, Irq6, Irq5, Irq3)

    DSACK1 and/or DSACK0 as part of the bus protocol. During a read cycle, this signals the MC68340 to terminate the bus cycle and to latch the data. During a write cycle, this indicates that the external device has successfully stored the data and that the cycle may terminate.

  • Page 41: Data Strobe ( Ds )

    2.7.3 Data Strobe ( DS ) DS is an output timing signal that applies to the data bus. For a read cycle, the MC68340 asserts DS and AS simultaneously to signal the external device to place data on the bus.

  • Page 42: Read-modify-write Cycle ( Rmc )

    This active-low, open-drain, bidirectional signal is used to initiate a system reset. An external reset signal (as well as a reset from the SIM40) resets the MC68340 and all external devices. A reset signal from the CPU32 (asserted as part of the RESET instruction) resets external devices;...

  • Page 43: Crystal Oscillator (extal, Xtal)

    This development serial input signal helps to provide serial communications for background debug mode. 2.11.2 Instruction Pipe (IPIPE) This pin functions as IPIPE in normal operation and as DSO in background debug mode. MOTOROLA MC68340 USER’S MANUAL 2- 9 For More Information On This Product, Go to: www.freescale.com...

  • Page 44: Breakpoint (bkpt)

    As an output, it is only active in external request mode. An external pullup resistor is required even during operation in the internal request mode. 2-10 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 45: Serial Module Signals

    2.13.7 Transmitter Ready (T RDYA) This active-low output can be programmed as the channel A transmitter ready status indicator or used as a discrete output. MOTOROLA MC68340 USER’S MANUAL 2- 11 For More Information On This Product, Go to: www.freescale.com...

  • Page 46: Receiver Ready ( R Rdya )

    These inputs can be programmed as clocks that cause events to occur in the counters and prescalers. 2.14.3 Timer Output (TOUT2, TOUT1) These outputs drive the various output waveforms generated by the timers. 2-12 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 47: Test Signals

    Integration Module for more information. 2.17 SYSTEM POWER AND GROUND (V CC AND GND) These pins provide system power and ground to the MC68340. Multiple pins are provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression.

  • Page 48

    IPIPE /DSO Out/Out Low/— No/— Development Serial Out Breakpoint/ BKPT /DSCLK In/In Low/— —/— Development Serial Clock Freeze FREEZE High Receive Data RxDA, RxDB — — 2-14 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 49

    — Test Data Out High — Synchronizer Power V CCSYN – — — System Power Supply and V CC , GND – — — Return MOTOROLA MC68340 USER’S MANUAL 2- 15 For More Information On This Product, Go to: www.freescale.com...

  • Page 50: Bus Operation

    The maximum number of bits accepted or provided during a bus transfer is defined as the port width. The MC68340 contains an address bus that specifies the address for the transfer and a data bus that transfers the data.

  • Page 51: Bus Control Signals

    3.1.1 Bus Control Signals The MC68340 initiates a bus cycle by driving the A31–A0, SIZx, FCx, and R/ W outputs. At the beginning of a bus cycle, SIZ1 and SIZ0 are driven with FC3–FC0. SIZ1 and SIZ0 indicate the number of bytes remaining to be transferred during an operand cycle (consisting of one or more bus cycles).

  • Page 52: Function Code Signals

    Address Spaces Reserved (Motorola) User Data Space User Program Space Reserved (User ) Reserved (Motorola) Supervisor Data Space Supervisor Program Space CPU Space DMA Space MOTOROLA MC68340 USER’S MANUAL 3- 3 For More Information On This Product, Go to: www.freescale.com...

  • Page 53: Address Bus (a31-a0)

    This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or from the MC68340. A read or write operation may transfer 8 or 16 bits of data (one or two bytes) in one bus cycle. During a read cycle, the data is latched by the MC68340 on the last falling edge of the clock for that bus cycle.

  • Page 54: Bus Error ( Berr )

    8- and 16-bit ports. During an operand transfer cycle, the slave device signals its port size (byte or word) and indicates completion of the bus cycle to the MC68340 through the use of the DSACK inputs. Refer to Table 3-3 for DSACK encoding.

  • Page 55

    For example, if the MC68340 is executing an instruction that reads a long-word operand from a 16-bit port, the MC68340 latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits. The operation from an 8-bit port is similar, but requires four read cycles.

  • Page 56: Misaligned Operands

    The following cases are examples of the allowable alignments of operands to ports. 3.2.3.1 BYTE OPERAND TO 8-BIT PORT, ODD OR EVEN (A0 = X). The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a single- byte operand.

  • Page 57: Byte Operand To 16-bit Port, Even (a0 = 0)

    15–8 and ignores bits 7–0. For a write operation, the MC68340 drives the single-byte operand on both bytes of the data bus because it does not know the port size until the DSACK signals are read. The slave device reads the byte operand from bits 15–8 and places the operand in the...

  • Page 58: Byte Operand To 16-bit Port, Odd (a0 = 1)

    15–8 of the data bus. For a write operation, the MC68340 drives the word operand on bits 15–0 of the data bus. The slave device then reads the most significant byte of the operand from bits 15–8 of the data bus and asserts DSACK0 to indicate that it received the data but is an 8-bit port.

  • Page 59: Word Operand To 16-bit Port, Aligned

    MC68340 reads the data on the data bus and terminates the cycle. For a write operation, the MC68340 drives the word operand on bits 15–0 of the data bus. The slave device then reads the entire operand from bits 15–0 of the data bus and asserts DSACK1 to terminate the bus cycle.

  • Page 60: Long-word Operand Read Timing From 8-bit Port

    D15–D8 D7–D0 BYTE BYTE BYTE BYTE READ READ READ READ LONG-WORD OPERAND READ FROM 8-BIT BUS Figure 3-3. Long-Word Operand Read Timing from 8-Bit Port MOTOROLA MC68340 USER’S MANUAL 3- 11 For More Information On This Product, Go to: www.freescale.com...

  • Page 61: Long-word Operand To 16-bit Port, Aligned

    3.2.3.7 LONG-WORD OPERAND TO 16-BIT PORT, ALIGNED. Figure 3-5 shows both long-word and word read and write timing to a 16-bit port. LONG-WORD OPERAND DATA BUS SIZ1 SIZ0 DSACK1 DSACK0 CYCLE 1 CYCLE 2 3-12 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 62: Long-word And Word Read And Write Timing—16-bit Port

    Figure 3-5. Long-Word and Word Read and Write Timing—16-Bit Port The MC68340 drives the address bus with the desired address and drives the SIZx pins to indicate a long-word operand. For a read operation, the slave responds by placing the two most significant bytes of the operand on bits 15–0 of the data bus and asserting DSACK1...

  • Page 63: Bus Operation

    If the setup and hold times are met for the assertion or negation of a signal such as DSACK , the MC68340 is guaranteed to recognize that signal level on that specific falling edge of the system clock.

  • Page 64: Fast Termination Cycles

    DSACK is recognized. This setup time is critical, and the MC68340 may exhibit erratic behavior if it is violated. When operating synchronously, the data-in setup and hold times for synchronous cycles may be used instead of the timing requirements for data relative to DS .

  • Page 65: Data Transfer Cycles

    MC68340 attempts to read two bytes at once. For a byte operation, the MC68340 reads one byte. The section of the data bus from which each byte is read depends on the operand size, address signal A0, and the port size.

  • Page 66

    DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACK on the falling edges of the clock until one is recognized.

  • Page 67: Write Cycle

    DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACK on the falling edges of the clock until one is recognized. The selected device uses R/ W , SIZ1/SIZ0, and A0 to latch data from the appropriate byte(s) of D15–D8...

  • Page 68: Read-modify-write Cycle

    State 4—The MC68340 issues no new control signals during S4. State 5—The MC68340 negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems. R/ W , SIZ1/SIZ0, and FC3–...

  • Page 69

    If DSACK is not recognized by the start of S3, the MC68340 inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2.

  • Page 70: Cpu Space Cycles

    State 4—The MC68340 issues no new control signals during S4. State 5—The MC68340 negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems. R/ W and FC3–FC0 also remain valid throughout S5.

  • Page 71: Breakpoint Acknowledge Cycle

    If the bus cycle is terminated by DSACK , the MC68340 uses the data on D15–D0 (for 16-bit ports) or two reads from D15–D8 (for 8-bit ports) to replace the BKPT instruction in the internal instruction pipeline and then begins execution of that instruction.

  • Page 72: Lpstop Broadcast Cycle

    MC68340 is going into LPSTOP mode. If an external device requires additional time to prepare for entry into LPSTOP mode, entry can be delayed by asserting HALT .

  • Page 73: Breakpoint Operation Flowchart

    1. CONTINUE PROCESSING IF BREAKPOINT INSTRUCTION EXECUTED: 1. INITIATE ILLEGAL INSTRUCTION PROCESSING IF BKPT PIN ASSERTED: 1. INITIATE HARDWARE BREAKPOINT PROCESSING Figure 3-11. Breakpoint Operation Flowchart 3-24 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 74: Breakpoint Acknowledge Cycle Timing (opcode Returned)

    DSACKx D7–D0 D15–D8 BERR HALT BKPT FETCHED INSTRUCTION EXECUTION BREAKPOINT BREAKPOINT READ ACKNOWLEDGE OCCURS INSTRUCTION WORD FETCH Figure 3-12. Breakpoint Acknowledge Cycle Timing (Opcode Returned) MOTOROLA MC68340 USER’S MANUAL 3- 25 For More Information On This Product, Go to: www.freescale.com...

  • Page 75: Breakpoint Acknowledge Cycle Timing (exception Signaled)

    SIZ0 SIZ1 DSACKx D7–D0 D15–D8 BERR HALT BKPT EXCEPTION STACKING BREAKPOINT READ BREAKPOINT ACKNOWLEDGE BUS ERROR ASSERTED OCCURS Figure 3-13. Breakpoint Acknowledge Cycle Timing (Exception Signaled) 3-26 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 76: Module Base Address Register Access

    Other interrupting conditions or devices that cannot supply a vector number will use the autovector cycle described in 3.4.4.2 Autovector Interrupt Acknowledge Cycle. MOTOROLA MC68340 USER’S MANUAL 3- 27 For More Information On This Product, Go to: www.freescale.com...

  • Page 77: Interrupt Acknowledge Cycle Flowchart

    NUMBER) ACQUIRE VECTOR NUMBER 1. LATCH VECTOR NUMBER 2. NEGATE DS AND AS RELEASE 1. NEGATE DSACKx START NEXT CYCLE Figure 3-14. Interrupt Acknowledge Cycle Flowchart 3-28 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 78: Autovector Interrupt Acknowledge Cycle

    AVEC to terminate the cycle. If the DSACK signals are asserted during an interrupt acknowledge cycle terminated by AVEC , the DSACK signals and MOTOROLA MC68340 USER’S MANUAL 3- 29 For More Information On This Product, Go to: www.freescale.com...

  • Page 79: Spurious Interrupt Cycle

    When AVEC is asserted instead of DSACK during an interrupt acknowledge cycle, the MC68340 ignores the state of the data bus and internally generates the vector number (the sum of the interrupt level plus 24 ($18)).

  • Page 80: Autovector Operation Timing

    D15–D0 AVEC IRQ7–IRQ1 IACK7–IACK1 WRITE CYCLE INTERNAL STACK READ ARBITRATION IACK CYCLE * Internal Arbitration may take between 0–2 clocks. Figure 3-16. Autovector Operation Timing MOTOROLA MC68340 USER’S MANUAL 3- 31 For More Information On This Product, Go to: www.freescale.com...

  • Page 81: Bus Exception Control Cycles

    MC68340 asserts AS . This mechanism allows the cycle to terminate and the MC68340 to enter exception processing for the error condition. HALT is also used for bus exception control. This signal can be asserted by an external device for debugging purposes to cause single bus cycle operation, or, in combination with BERR , a retry of a bus cycle in error.

  • Page 82

    1. Delay DSACK until data is verified and assert BERR and HALT simultaneously to indicate to the MC68340 to automatically retry the error cycle (case 5), or if data is valid, assert DSACK (case 1). 2. Delay DSACK until data is verified and assert BERR with or without DSACK if data is in error (case 3).

  • Page 83: Bus Errors

    DSACK is recognized. If BERR is not stable at this time, the MC68340 may exhibit erratic behavior. BERR has priority over DSACK . In this case, data may be present on the bus, but it may not be valid.

  • Page 84: Bus Error Without Dsack

    Freescale Semiconductor, Inc. CLKOUT A31–A0 FC3–FC0 DSACKx D15–D0 BERR READ CYCLE WITH BUS STACK INTERNAL ERROR PROCESSING WRITE Figure 3-17. Bus Error without DSACK MOTOROLA MC68340 USER’S MANUAL 3- 35 For More Information On This Product, Go to: www.freescale.com...

  • Page 85: Retry Operation

    When both BERR and HALT are asserted by an external device during a bus cycle, the MC68340 enters the retry sequence shown in Figure 3-19. A delayed retry, which is similar to the delayed BERR signal described previously, can also occur (see Figure 3-20).

  • Page 86: Retry Sequence

    RMC remains asserted during the entire retry sequence. Asserting BR along with BERR and HALT provides a relinquish and retry operation. The MC68340 does not relinquish the bus during a read-modify-write operation. Any device that requires the MC68340 to give up the bus and retry a bus cycle during a read-modify-write cycle must assert only BERR and BR ( HALT must not be included).

  • Page 87: Halt Operation

    The single-cycle mode allows the user to proceed through (and debug) external MC68340 operations, one bus cycle at a time. Since the occurrence of a bus error while HALT is asserted causes a retry operation, the user must anticipate retry cycles while debugging in the single-cycle mode.

  • Page 88: Double Bus Fault

    Freescale Semiconductor, Inc. asserted, the A31–A0, FCx, SIZx, and R/ W signals are again driven to their previous states. The MC68340 does not service interrupt requests while it is halted. CLKOUT A31–A0 FC3–FC0 DSACKx D15–D10 HALT BGACK READ HALT READ...

  • Page 89: Bus Arbitration

    Reset can also be generated internally by the halt monitor (see Section 5 CPU32). 3.6 BUS ARBITRATION The bus design of the MC68340 provides for a single bus master at any one time, either the MC68340 or an external device. One or more of the external devices on the bus can have the capability of becoming bus master for the external bus, but not the MC68340 internal bus.

  • Page 90: Bus Arbitration Flowchart For Single Request

    BG is negated a few clock cycles after the transition of BGACK . However, if bus requests are still pending after the negation of BG , the MC68340 asserts another BG within a few clock cycles after it was negated. This additional assertion of BG allows external arbitration circuitry to select the next bus master before the current bus master has finished using the bus.

  • Page 91: Bus Arbitration Timing Diagram—idle Bus Case

    CLKOUT A31–A0 D15–D0 BGACK Figure 3-23. Bus Arbitration Timing Diagram—Idle Bus Case CLKOUT A31–A0 D15–D0 DSACK0, DSACK1 BGACK Figure 3-24. Bus Arbitration Timing Diagram—Active Bus Case 3-42 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 92: Bus Request

    MC68340 that some external device requires control of the bus. The MC68340 is effectively at a lower bus priority level than the external device and relinquishes the bus after it has completed the current bus cycle (if one has started).

  • Page 93: Bus Arbitration Control

    MC68340. State 0, in which G and T are both negated, is the state of the bus arbiter while the MC68340 is bus master. R and A keep the arbiter in state 0 as long as they are both negated.

  • Page 94: Bus Arbitration State Diagram

    T - THREE-STATE SIGNAL TO BUS CONTROL A - BUS GRANT ACKNOWLEDGE V - BUS AVAILABLE TO BUS CONTROL B - BUS CYCLE IN PROGRESS Figure 3-25. Bus Arbitration State Diagram MOTOROLA MC68340 USER’S MANUAL 3- 45 For More Information On This Product, Go to: www.freescale.com...

  • Page 95: Reset Operation

    Figure 3-26. Show Cycle Timing Diagram 3.7 RESET OPERATION The MC68340 has reset control logic to determine the cause of reset, synchronize it if necessary, and assert the appropriate reset lines. The reset control logic can independently drive three different lines: 1.

  • Page 96: Timing For External Devices Driving Reset

    Asynchronous reset sources indicate a catastrophic failure, and the reset controller logic immediately resets the system. Resetting the MC68340 causes any bus cycle in progress to terminate as if DSACK or BERR had been asserted. In addition, the MC68340 appropriately initializes registers for a reset exception. Asynchronous reset sources include power-up, software watchdog, double bus fault resets, and execution of the RESET instruction.

  • Page 97: Power-up Reset Timing Diagram

    4. First instruction fetched here. Figure 3-28. Power-Up Reset Timing Diagram When a RESET instruction is executed, the MC68340 drives the RESET signal for 512 clock cycles. The SIM40 registers and the module control registers in each internal peripheral module (DMA, timers, and serial modules) are not affected. All other peripheral module registers are reset the same as for a hardware reset.

  • Page 98: System Integration Module

    SECTION 4 SYSTEM INTEGRATION MODULE The MC68340 system integration module (SIM40) consists of several functions that control the system start-up, initialization, configuration, and the external bus with a minimum of external devices. It also provides the IEEE 1149.1 boundary scan capabilities.

  • Page 99: Module Operation

    CPU32 and memory, peripherals, or other processing elements in the external address space. See Section 3 Bus Operation for further information. The MC68340 dynamically interprets the port size of an addressed device during each bus cycle, allowing operand transfers to or from 8-, 16-, and 32-bit ports. The device signals its port size and indicates completion of the bus cycle through the use of the DSACK inputs.

  • Page 100: System Configuration And Protection Operation

    All M68000 family members are designed to provide maximum system safeguards. As an extension of the family, the MC68340 promotes the same basic concepts of safeguarded design present in all M68000 members. In addition, many functions that normally must be provided by external circuits are incorporated in this device.

  • Page 101: Internal Bus Monitor

    122 s to 15.94 s (with a 32.768-kHz crystal used to generate the system clock). This function can be disabled. Figure 4-2 shows a block diagram of the system configuration and protection function. MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 102: System Configuration And Protection Function

    IARB = 0 are discarded as extraneous. The SIM40 arbitrates for both its own interrupts and externally generated interrupts. MOTOROLA MC68340 USER’S MANUAL 4- 5 For More Information On This Product, Go to: www.freescale.com...

  • Page 103

    The internal bus monitor cannot check the DSACK response on the external bus unless the MC68340 is the bus master. The BME bit in the system protection control register (SYPCR) enables the internal bus monitor for internal-to-external bus cycles.

  • Page 104: Software Watchdog Block Diagram

    If a new value is written to the PITR, this value is loaded into the modulus counter when the current count is completed. MOTOROLA MC68340 USER’S MANUAL 4- 7 For More Information On This Product, Go to: www.freescale.com...

  • Page 105: Periodic Timer Period Calculation

    For fast calculation of periodic timer period using a 32.768-kHz crystal, the following equations can be used: With prescaler disabled: programmable interrupt timer period PITR (122 s) With prescaler enabled: programmable interrupt timer period PITR (62.5 ms) MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 106: Using The Periodic Timer As A Real-time Clock

    Figure 4-5. A 32.768-kHz watch crystal provides an inexpensive reference, but the reference crystal or external oscillator frequency can be any frequency in the range specified in Section 11 Electrical Characteristics. When MOTOROLA MC68340 USER’S MANUAL 4- 9 For More Information On This Product, Go to: www.freescale.com...

  • Page 107: Clock Block Diagram For Crystal Operation

    60 k XTAL EXTAL 60 k Figure 4-5. MC68340 Crystal Oscillator A separate power pin (V ) is used to allow the clock circuits to run with the rest of CCSYN the device powered down and to provide increased noise immunity for the clock circuits.

  • Page 108: Phase Comparator And Filter

    4.2.3.1 PHASE COMPARATOR AND FILTER. The phase comparator takes the output of the frequency divider and compares it to an external input signal reference. The result of MOTOROLA MC68340 USER’S MANUAL 4- 11 For More Information On This Product, Go to: www.freescale.com...

  • Page 109

    VCO frequency limits are given in Section 11 Electrical Characteristics. Table 4-2 lists some frequencies available from various combinations of SYNCR bits with a reference frequency of 32.768-KHz. 4-12 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 110: Chip Select Operation

    4.2.4 Chip Select Operation Typical microprocessor systems require external hardware to provide select signals to external memory and peripherals. The MC68340 integrates these functions on chip to provide the cost, speed, and reliability benefits of a higher level of integration. The chip select function contains register pairs for each external chip select signal.

  • Page 111: Programmable Features

    When the CPU32 begins fetching after reset, CS0 is asserted for every address until the V-bit is set in the CS0 base address register. 4-14 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 112: External Bus Interface Operation

    PPARA2 = 1 IACK7 PORT A7 IACK6 PORT A6 PORT A5 IACK5 PORT A4 IACK4 IACK3 PORT A3 IACK2 PORT A2 PORT A1 IACK1 PORT A0 — MOTOROLA MC68340 USER’S MANUAL 4- 15 For More Information On This Product, Go to: www.freescale.com...

  • Page 113: Port B

    IRQ5 PORTB3 IRQ3 PORTB3 IRQ3 IRQ3 IRQ4 PORTB4 PORTB2 IRQ2 IRQ1 PORTB1 AVEC AVEC PORTB0 MODCK PORTB0 MODCK MODCK NOTE: MODCK has no function after reset. 4-16 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 114: Low-power Stop

    4.2.6 Low-Power Stop Executing the LPSTOP instruction provides reduced power consumption when the MC68340 is idle; only the SIM40 remains active. Operation of the SIM40 clock and CLKOUT during LPSTOP is controlled by the STSIM and STEXT bits in the SYNCR (see Table 4-3).

  • Page 115: Programming Model

    The access privilege is indicated in the lower right-hand corner. NOTE: A CPU32 RESET instruction will not affect any of the SIM40 registers. 4-18 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 116: Sim40 Programming Model

    CHIP SELECT ADDRESS MASK 2 CS3 CHIP SELECT BASE ADDRESS 1 CS3 CHIP SELECT BASE ADDRESS 2 CS3 CHIP SELECT Figure 4-8. SIM40 Programming Model MOTOROLA MC68340 USER’S MANUAL 4- 19 For More Information On This Product, Go to: www.freescale.com...

  • Page 117: Module Base Address Register (mbar)

    V-bit is set. 1 = Contents are valid. 0 = Contents are not valid. 4-20 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 118: System Configuration And Protection Registers

    0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters continue to run. See 4.2.7 Freeze for more information. MOTOROLA MC68340 USER’S MANUAL 4- 21 For More Information On This Product, Go to: www.freescale.com...

  • Page 119

    IACK cycle immediately after reset. The system software should initialize the IARB field to a value from $F (highest priority) to $1 (lowest priority). A 4-22 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 120: Autovector Register (avr)

    1 = The last reset was caused by the software watchdog circuit. DBF—Double Bus Fault Monitor Reset 1 = The last reset was caused by the double bus fault monitor. Bits 3, 0—Reserved MOTOROLA MC68340 USER’S MANUAL 4- 23 For More Information On This Product, Go to: www.freescale.com...

  • Page 121: Software Interrupt Vector Register (swiv)

    See 4.2.2.5 Software Watchdog for more information. SWRI—Software Watchdog Reset/Interrupt Select 1 = Software watchdog causes a system reset. 0 = Software watchdog causes a level 7 interrupt to the CPU32. 4-24 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 122

    BMT1, BMT0—Bus Monitor Timing These bits select the timeout period for the bus monitor (see Table 4-8). Upon reset, the bus monitor is set to 64 system clocks. MOTOROLA MC68340 USER’S MANUAL 4- 25 For More Information On This Product, Go to: www.freescale.com...

  • Page 123

    Use caution with a level 7 interrupt encoding due to the SIM40's interrupt servicing order. See 4.2.2.7 Simultaneous Interrupts by Sources in the SIM40 for the servicing order. 4-26 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 124: Periodic Interrupt Timer Register (pitr)

    PITR7–PITR0—Periodic Interrupt Timer Register Bits 7–0 The remaining bits of the PITR contain the count value for the periodic timer. A zero value turns off the periodic timer. MOTOROLA MC68340 USER’S MANUAL 4- 27 For More Information On This Product, Go to: www.freescale.com...

  • Page 125: Clock Synthesizer Control Register (syncr)

    Y+1 (see the equation for determining system frequency). Changing these bits requires a time delay for the VCO to relock. Bits 7–5—Reserved Bit 7 is reserved for factory testing. 4-28 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 126

    The following paragraphs provide descriptions of the registers in the chip select function, and an example of how to program the registers. The chip select registers cannot be used until the V-bit in the MBAR is set. MOTOROLA MC68340 USER’S MANUAL 4- 29 For More Information On This Product, Go to: www.freescale.com...

  • Page 127

    (see Section 3 Bus Operation). 1 = Fast termination cycle enabled (termination determined by PS bits). 0 = Fast termination cycle disabled (termination determined by DD and PS bits). 4-30 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 128

    This field can be read or written at any time. MOTOROLA MC68340 USER’S MANUAL 4- 31 For More Information On This Product,...

  • Page 129

    *Use only for 32-bit DMA transfers. To use the external DSACK response, PS1–PS0 = 11 should be selected to suppress internal DSACK generation . The DDx bits then have no significance. 4-32 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 130

    PPARA1 $015 PRTA7 PRTA6 PRTA5 PRTA4 PRTA3 PRTA2 PRTA1 PRTA0 (A31) (A30) (A29) (A28) (A27) (A26) (A25) (A24) RESET: Supervisor Only MOTOROLA MC68340 USER’S MANUAL 4- 33 For More Information On This Product, Go to: www.freescale.com...

  • Page 131

    Otherwise, the value read is the value stored in the internal data latch. This register can be read or written at any time. PORTA $011 RESET: Supervisor/User 4-34 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 132

    Otherwise, the value read is the value of the pin. This register can be read or written at any time. PORTB, PORTB1 $019, 01B RESET: Supervisor/User MOTOROLA MC68340 USER’S MANUAL 4- 35 For More Information On This Product, Go to: www.freescale.com...

  • Page 133

    RESET is asserted by the MC68340 during the time in which V is ramping up, the VCO is locking onto the frequency, and the MC68340 is going through the reset operation. After RESET is negated, four bus cycles are run, with global CS0 being asserted to fetch the 32-bit supervisor stack pointer (SSP) and the 32-bit program counter (PC) from the boot ROM.

  • Page 134: System Protection Control Register (sypcr) (note That This Register Can Only Be Written

    • Program the desired function of the port A signals (PPARA1 and PPARA2 registers). • Program the desired function of the port B signals (PPARB register). MOTOROLA MC68340 USER’S MANUAL 4- 37 For More Information On This Product, Go to: www.freescale.com...

  • Page 135: Sim40 Example Configuration Code

    The following code is an example configuration sequence for the SIM40 module. *************************************************************************** * MC68340 basic SIM40 register initialization example code: * This code is used to initialize the MC68340's internal SIM40 registers, * providing basic functions for operation. * It includes chip select programming for external devices.

  • Page 136

    #7,D Set up a loop counter. CSAM0$,A1 Point to addr mask memory location. LOOP MOVE.L (A1)+,(A0)+ Init. addr mask and base addr reg DBRA D0,LOOP MOTOROLA MC68340 USER’S MANUAL 4- 39 For More Information On This Product, Go to: www.freescale.com...

  • Page 137

    * CS2 - external device - 00FFE8xx, external termination CSAM2$ DC.L $000000F3 CSBAR2$ DC.L $00FFE801 * CS3 - secondary memory - 00000000-0003ffff, 3-wait states, 16-bit term. CSAM3$ DC.L $0003FFFD CSBAR3$ DC.L $00000001 *************************************************************************** 4-40 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 138: Overview

    (HLL) will become the system designer's choice in programming languages. HLL aids in the rapid development of complex algorithms with less error and is readily portable. The CPU32 instruction set will efficiently support HLL. MOTOROLA MC68340 USER’S MANUAL 5- 1 For More Information On This Product, Go to: www.freescale.com...

  • Page 139: Features

    The access to that location is temporarily suspended while the necessary data is fetched from secondary storage and placed in physical memory. The MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 140: Loop Mode Instruction Execution

    –4. Once in loop mode, the processor performs only the data cycles associated with the instruction and suppresses all instruction fetches. The termination MOTOROLA MC68340 USER’S MANUAL 5- 3 For More Information On This Product, Go to: www.freescale.com...

  • Page 141: Vector Base Register

    The processor also marks the frame with a frame format. The format field allows the return-from-exception (RTE) instruction to identify what information is on the stack so that it may be properly restored. MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 142: Addressing Modes

    The CPU32 traps on unimplemented instructions or illegal effective addressing modes, allowing user-supplied code to emulate unimplemented capabilities or to define special- purpose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 core enhancements.

  • Page 143

    Link and Allocate TRAPcc Trap Conditionally (16 Tests) LPSTOP Low-Power Stop TRAPV Trap on Overflow LSL, LSR Logical Shift Left and Right Test MOVE Move UNLK Unlink MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 144: Table Lookup And Interpolate Instructions

    The processor uses the privilege level indicated by the S-bit in the SR to select either the user or supervisor privilege level and either the user stack pointer (USP) or SSP for stack operations. MOTOROLA MC68340 USER’S MANUAL 5- 7 For More Information On This Product, Go to: www.freescale.com...

  • Page 145: Architecture Summary

    The CPU32 has eight 32-bit data registers, seven 32-bit address registers, a 32-bit PC, separate 32-bit SSP and USP, a 16-bit SR, two alternate function code registers, and a 32-bit VBR (see Figures 5-3 and 5-4). MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 146: User Programming Model

    Figure 5-3. User Programming Model A7' (SSP) SUPERVISOR STACK POINTER (CCR) STATUS REGISTER PROGRAM COUNTER ALTERNATE FUNCTION CODE REGISTERS Figure 5-4. Supervisor Programming Model Supplement MOTOROLA MC68340 USER’S MANUAL 5- 9 For More Information On This Product, Go to: www.freescale.com...

  • Page 147: Registers

    DFC to specify the function code of a memory address. USER BYTE SYSTEM BYTE (CONDITION CODE REGISTER) EXTEND TRACE INTERRUPT ENABLE PRIORITY MASK NEGATIVE ZERO SUPERVISOR/USER STATE OVERFLOW CARRY Figure 5-5. Status Register 5-10 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 148: Instruction Set

    The low-power mode is entered by executing the LPSTOP instruction. The processor remains in this mode until a user-specified or higher level interrupt or a reset occurs. MOTOROLA MC68340 USER’S MANUAL 5- 11 For More Information On This Product, Go to: www.freescale.com...

  • Page 149: Table Lookup And Interpolation (tbl)

    5.3.1.2 UNIMPLEMENTED INSTRUCTIONS. The ability to trap on unimplemented instructions allows user-supplied code to emulate unimplemented capabilities or to define special-purpose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 enhancements. See 5.5.2.8 Illegal or Unimplemented Instructions for more details.

  • Page 150

    Immediate data; a literal integer label Assembly program label list List of registers Example: D3–D0 [...] Bits of an operand Examples: [7] is bit 7; [31:24] are bits 31–24 MOTOROLA MC68340 USER’S MANUAL 5- 13 For More Information On This Product, Go to: www.freescale.com...

  • Page 151

    Read/write indicator In a description of an operation, a destination operand is placed to the right of source operands and is indicated by an arrow ( 5-14 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 152: Instruction Summary

    The complete range of instruction capabilities combined with the addressing modes described previously provide flexibility for program development. All CPU32 instructions are summarized in Table 5-2. MOTOROLA MC68340 USER’S MANUAL 5- 15 For More Information On This Product, Go to: www.freescale.com...

  • Page 153

    Destination — Source CMP ea ,Dn CMPA Destination — Source CMPA ea ,An CMPI Destination — Immediate Data CMPI # data ea CMPM Destination — Source CMPM (Ay)+,(Ax)+ 5-16 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 154

    Destination Shifted by count Destination Dx,Dy # data ,Dy MOVE Source Destination MOVE ea ea MOVEA Source Destination MOVEA ea ,An MOVE from Destination MOVE CCR, ea MOTOROLA MC68340 USER’S MANUAL 5- 17 For More Information On This Product, Go to: www.freescale.com...

  • Page 155

    If supervisor state RESET then Assert RESET else TRAP ROd 1 Rx,Dy ROL,ROR Destination Rotated by count Destination ROd 1 # data ,Dy ROd 1 ea 5-18 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 156

    If V then TRAP TRAPV Destination Tested Condition Codes TST ea UNLK SP; (SP) An; SP + 4 UNLK An NOTE 1: d is direction, L or R. MOTOROLA MC68340 USER’S MANUAL 5- 19 For More Information On This Product, Go to: www.freescale.com...

  • Page 157: Condition Code Register

    ROL (r = 0) — ASR, LSR, ROXR C = Dr – 1 ASR, LSR (r = 0) — ROXR (r = 0) — C = X 5-20 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 158: Data Movement Instructions

    Dn [15:8]; (An + d + 6) Dn [7:0] MOVEQ # data Dn Immediate Data Destination SP – 4 SP; ea UNLK SP; (SP) An, SP + 4 MOTOROLA MC68340 USER’S MANUAL 5- 21 For More Information On This Product, Go to: www.freescale.com...

  • Page 159: Integer Arithmetic Operations

    (ADDX), subtract extended (SUBX), sign extend (EXT), and negate binary with extend (NEGX). Refer to Table 5-5 for a summary of the integer arithmetic operations. 5-22 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 160

    256) + Temp TBLSN/TBLUN ea , Dn 8, 16, 32 Dyn – Dym Temp Dym:Dyn, Dn (Temp Dn [7:0]) / 256 Temp Dym + Temp MOTOROLA MC68340 USER’S MANUAL 5- 23 For More Information On This Product, Go to: www.freescale.com...

  • Page 161: Logic Instructions

    ROR and ROL instructions with a shift count of eight allows fast byte swapping. Table 5-7 is a summary of the shift and rotate operations. 5-24 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 162: Bit Manipulation Instructions

    ~( bit number of destination) Z; 1 bit of # data 8, 32 destination BTST Dn, ea 8, 32 ~ bit number of destination) # data 8, 32 MOTOROLA MC68340 USER’S MANUAL 5- 25 For More Information On This Product, Go to: www.freescale.com...

  • Page 163: Binary-coded Decimal (bcd) Instructions

    PC; SP + 4 + d none none (SP) CCR; SP + 2 SP; (SP) PC; SP + 4 none none (SP) PC; SP + 4 5-26 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 164: System Control Instructions

    Table 5-11 summarizes the instructions. The preceding list of condition tests also applies to the TRAPcc instruction. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes. MOTOROLA MC68340 USER’S MANUAL 5- 27 For More Information On This Product, Go to: www.freescale.com...

  • Page 165

    # data CCR Immediate Data EORI # data CCR Immediate Data MOVE ea , CCR Source CCR, ea Destination # data CCR Immediate Data V CCR 5-28 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 166: Condition Tests

    Example 3 (see Figure 5-9) demonstrates use of an 8-bit independent variable with an instruction. MOTOROLA MC68340 USER’S MANUAL 5- 29 For More Information On This Product, Go to: www.freescale.com...

  • Page 167: Table Example 1: Standard Usage

    *These values are the end points of the range. All entries between these points fall on the line. 16384 32768 49152 65536 INDEPENDENT VARIABLE Figure 5-7. Table Example 1 5-30 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 168: Table Example 2: Compressed Table

    Extreme table compression with many levels of interpolation is possible only with highly linear functions. The table entries within the range of interest are listed in Table 5-14. MOTOROLA MC68340 USER’S MANUAL 5- 31 For More Information On This Product, Go to: www.freescale.com...

  • Page 169: Table Example 3: 8-bit Independent Variable

    8-bit result. The subroutine uses the data listed in Table 5-15, based on the function shown in Figure 5-9. 5-32 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 170: Table Example 3

    The first column is the value passed to the subroutine, the second column is the value expected by the table instruction, and the third column is the result returned by the subroutine. MOTOROLA MC68340 USER’S MANUAL 5- 33 For More Information On This Product, Go to: www.freescale.com...

  • Page 171: Table Example 4: Maintaining Precision

    Assume that the result of the three interpolations are as follows (a ".'' indicates the binary radix point). 0010 0000 . 0111 0000 TBL # 1 0011 1111 . 0111 0000 TBL# 2 0000 0001 . 0111 0000 TBL # 3 5-34 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 172

    Long addition avoids problems with carry ADD.L Dm, Dl ASR.L #8, Dl Move radix point BCC.B Fraction MSB in carry ADDQ.B #1, Dl L1: . . . MOTOROLA MC68340 USER’S MANUAL 5- 35 For More Information On This Product, Go to: www.freescale.com...

  • Page 173: Table Example 5: Surface Interpolations

    This section describes the processing states of the CPU32. It includes a functional description of the bits in the supervisor portion of the SR and an overview of actions taken by the processor in response to exception conditions. 5-36 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 174: State Transitions

    FC2–FC0 refer to supervisor address spaces. MOTOROLA MC68340 USER’S MANUAL 5- 37 For More Information On This Product, Go to: www.freescale.com...

  • Page 175: Supervisor Privilege Level

    The following paragraphs discuss system resources related to exception handling, exception processing sequence, and specific features of individual exception processing routines. 5-38 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 176: Exception Vectors

    Level 6 Interrupt Autovector Level 7 Interrupt Autovector 32–47 Trap Instruction Vectors (0–15) — 48–58 (Reserved for Coprocessor) — 59–63 (Unassigned, Reserved) — 64–255 User-Defined Vectors (192) 1020 MOTOROLA MC68340 USER’S MANUAL 5- 39 For More Information On This Product, Go to: www.freescale.com...

  • Page 177: Exception Vectors

    All stack frames contain copies of the SR and the PC for use by RTE. The type of exception and the context in which the exception occurs determine what other information is stored in the stack frame. 5-40 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 178: Exception Processing Sequence

    Exception processing includes steps described in 5.5.1.2 Exception Processing Sequence, but does not include execution of handler routines, which is done in normal mode. MOTOROLA MC68340 USER’S MANUAL 5- 41 For More Information On This Product, Go to: www.freescale.com...

  • Page 179: Bus Error

    For example, if a bus error occurs during trace exception processing, the bus error will be processed and handled before trace exception processing is completed. 5-42 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 180

    The external devices connected to the RESET signal are reset at the completion of the RESET instruction. MOTOROLA MC68340 USER’S MANUAL 5- 43 For More Information On This Product,...

  • Page 181: Reset Operation Flowchart

    (VECTOR # 1) PREFETCH 3 WORDS BUS ERROR/ ADDRESS OTHERWISE BEGIN ERROR INSTRUCTION EXECUTION (DOUBLE BUS FAULT) ASSERT HALT EXIT EXIT Figure 5-11. Reset Operation Flowchart 5-44 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 182

    If the aborted cycle is a data space access, exception processing begins when the processor attempts to use the data, except in the MOTOROLA MC68340 USER’S MANUAL 5- 45 For More Information On This Product,...

  • Page 183: Instruction Traps

    DSACK , the processor uses the data returned to replace the breakpoint in the instruction pipeline and begins execution of that instruction. See Section 3 Bus Operation for a description of CPU space operations. 5-46 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 184: Hardware Breakpoints

    A separate F-line emulation vector (vector 11, offset $2C) is used for the exception vector. MOTOROLA MC68340 USER’S MANUAL 5- 47 For More Information On This Product, Go to: www.freescale.com...

  • Page 185: Privilege Violations

    Freescale Semiconductor, Inc. All unimplemented instructions are reserved for use by Motorola for enhancements and extensions to the basic M68000 architecture. Opcode pattern $4AFC is defined to be illegal on all M68000 family members. Those customers requiring the use of an unimplemented opcode for synthesis of "custom instructions,"...

  • Page 186: Tracing

    At the present time, T1–T0 = 11 is an undefined condition. It is reserved by Motorola for future use. Exception processing for trace starts at the end of normal processing for the traced instruction and before the start of the next instruction.

  • Page 187: Interrupts

    SR. After the copy is made, the processor state bits in the SR are changed—the S-bit is set, establishing supervisor access level, and bits T1 and T0 are cleared, disabling 5-50 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 188: Return From Exception

    For a bus fault frame, the format value on the stack is first checked for validity. In addition, the version number on the stack must match the version number of the processor that is MOTOROLA MC68340 USER’S MANUAL 5- 51 For More Information On This Product,...

  • Page 189: Fault Recovery

    RM—Faulted cycle was read-modify-write IN—Instruction/other RW—Read/write of faulted bus cycle LG—Original operand size was long word SIZ—Remaining size of faulted bus cycle FUNC—Function code of faulted bus cycle 5-52 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 190

    IN bit. If IN is cleared, the error was on an operand cycle; if IN is set, the error was on an instruction prefetch. IN is ignored during unstacking. 0 = Operand 1 = Prefetch MOTOROLA MC68340 USER’S MANUAL 5- 53 For More Information On This Product, Go to: www.freescale.com...

  • Page 191: Types Of Faults

    This action prevents stale data from being used by the instruction. 5-54 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 192: Type Ii-prefetch, Operand, Rmw, And Movep Faults

    If the bus cycle was an RMW, the RM bit will be set, and the RW bit will show whether the fault was on a read or write. MOTOROLA MC68340 USER’S MANUAL 5- 55 For More Information On This Product,...

  • Page 193: Type Iii-faults During Movem Operand Transfer

    The type of exception can be determined from the format/vector word. If the faulted exception stack frame contains six words, the PC of the instruction that caused the initial 5-56 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 194: Correcting A Fault

    If the rerun bus cycle is a read, returned data will be ignored. MOTOROLA MC68340 USER’S MANUAL 5- 57 For More Information On This Product, Go to: www.freescale.com...

  • Page 195: Type Ii-correcting Faults Via Rte

    Clearing the MV bit in the stacked SSW converts a type III fault into a type II fault. Consequently, MOVEM, like all other type II 5-58 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 196: Type Iii-correcting Faults Via Rte

    MOTOROLA MC68340 USER’S MANUAL 5- 59 For More Information On This Product, Go to: www.freescale.com...

  • Page 197: Cpu32 Stack Frames

    M68000 Family members. The only internal machine state required in the CPU32 stack frame is the bus controller state at the time of the error and a single register. 5-60 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 198: Internal Transfer Count Register

    $12). The fault address of a dynamically sized bus cycle is the address of the upper byte, regardless of the byte that caused the error. MOTOROLA MC68340 USER’S MANUAL 5- 61 For More Information On This Product, Go to: www.freescale.com...

  • Page 199: Format $c—berr Stack For Prefetches And Operands

    CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW +$14 INTERNAL TRANSFER COUNT REGISTER +$16 SPECIAL STATUS WORD Figure 5-16. Format $C—BERR Stack on MOVEM Operand 5-62 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 200: Development Support

    In addition to standard MC68000 family capabilities, the CPU32 has features to support advanced integrated system development. These features include background debug mode, deterministic opcode tracking, hardware breakpoints, and internal visibility in a single-chip environment. MOTOROLA MC68340 USER’S MANUAL 5- 63 For More Information On This Product, Go to: www.freescale.com...

  • Page 201: Background Debug Mode (bdm) Overview

    BSA to synchronize with instruction stream activity. Refer to 5.6.3 Deterministic Opcode Tracking for complete information. 5.6.1.3 ON-CHIP HARDWARE BREAKPOINT OVERVIEW. An external breakpoint input and an on-chip hardware breakpoint capability permit breakpoint trap on any 5-64 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 202: Background Debug Mode

    CPU32 since the serial command interface would probably not be available. For this reason, BDM is enabled during reset via the BKPT signal. MOTOROLA MC68340 USER’S MANUAL 5- 65 For More Information On This Product, Go to: www.freescale.com...

  • Page 203: Bdm Sources

    FREEZE assertion is the first indication that the processor has entered BDM. Once FREEZE has been asserted, the CPU enables the serial communication hardware and awaits a command. 5-66 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 204: Bgnd Instruction

    A BKPT asserted during this cycle will not be acknowledged until the end of the instruction MOTOROLA MC68340 USER’S MANUAL 5- 67 For More Information On This Product, Go to: www.freescale.com...

  • Page 205: Returning From Bdm

    The BKPT signal becomes the DSCLK; DSI is received on IFETCH , and DSO is transmitted on IPIPE . 5-68 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 206: Cpu Serial Logic

    FFFF Command and data transfers initiated by the development system should clear bit 16. The current implementation ignores this bit; however, Motorola reserves the right to use this bit for future enhancements. 5.6.2.7.1 CPU Serial Logic. CPU serial logic, shown in the left-hand portion of Figure 5- 22, consists of transmit and receive shift registers and of control logic that includes synchronization, serial clock generation circuitry, and a received bit counter.

  • Page 207: Debug Serial I/o Block Diagram

    (valid data status bit) logic level. However, this level change only occurs if the command completes successfully. Error conditions overwrite the “not ready” response with the appropriate response that also has the status bit set. 5-70 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 208: Development System Serial Logic

    Each method requires a slightly different serial logic design to avoid spurious serial clocks. Figure 5-24 represents the timing required for asserting BKPT during a single bus cycle. MOTOROLA MC68340 USER’S MANUAL 5- 71 For More Information On This Product, Go to: www.freescale.com...

  • Page 209: Bkpt Timing For Single Bus Cycle

    BKPT_TAG should be timed to the bus cycles since it is not latched. If extended past the assertion of FREEZE, the negation of BKPT_TAG appears to the CPU32 as the first DSCLK. 5-72 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 210: Command Set

    One indicates an address register; zero indicates a data register. For other commands, this field may be interpreted differently. MOTOROLA MC68340 USER’S MANUAL 5- 73 For More Information On This Product, Go to: www.freescale.com...

  • Page 211: Command Sequence Diagram

    The data transmitted to the CPU during the final transfer is the opcode for the following command. Should a memory access generate either a bus or address error, an error status is returned in place of the result data. 5-74 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 212: Command Set Summary

    Figure 5-27. Command-Sequence Diagram 5.6.2.8.3 Command Set Summary. The BDM command set is summarized in Table 5-23. Subsequent paragraphs contain detailed descriptions of each command. MOTOROLA MC68340 USER’S MANUAL 5- 75 For More Information On This Product, Go to: www.freescale.com...

  • Page 213: Read A/d Register Rareg/rdreg

    Command Format: REGISTER Command Sequence: RDREG/RAREG NEXT CMD MS RESULT LS RESULT NEXT CMD "ILLEGAL" "NOT READY" Operand Data: None 5-76 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 214

    Command Format: REGISTER Command Sequence: RSREG NEXT CMD MS RESULT LS RESULT NEXT CMD "ILLEGAL" "NOT READY" Operand Data: None MOTOROLA MC68340 USER’S MANUAL 5- 77 For More Information On This Product, Go to: www.freescale.com...

  • Page 215

    The data to be written into the register is always supplied as a 32-bit long word. If the register is less than 32 bits, the least significant word is used. Result Data: “Command complete” status is returned when register write is complete. 5-78 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 216

    $10001. 5.6.2.8.9 Write Memory Location (WRITE). Write the operand data to the memory location specified by the long-word address. The DFC register determines the address MOTOROLA MC68340 USER’S MANUAL 5- 79 For More Information On This Product, Go to: www.freescale.com...

  • Page 217

    5.6.2.8.10 Dump Memory Block (DUMP). DUMP is used in conjunction with the READ command to dump large blocks of memory. An initial READ is executed to set up the 5-80 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 218

    READ DUMP (LONG) MEMORY "NOT READY" LOCATION NEXT CMR NEXT CMD MS RESULT LS RESULT NEXT CMD BERR/AERR "NOT READY" NEXT CMD "ILLEGAL" "NOT READY" MOTOROLA MC68340 USER’S MANUAL 5- 81 For More Information On This Product, Go to: www.freescale.com...

  • Page 219

    The size field is examined each time a FILL command is given, allowing the operand size to be altered dynamically. Command Format: OP SIZE 5-82 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 220

    BDM. For address error, the PC does not reflect the true return PC. Instead, the stacked fault address is the (odd) return PC. Command Format: MOTOROLA MC68340 USER’S MANUAL 5- 83 For More Information On This Product, Go to: www.freescale.com...

  • Page 221

    BDM. For address error, the PC does not reflect the true return PC. Instead, the stacked fault address is the (odd) return PC. Command Format: 5-84 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 222

    The 32-bit operand data is the starting location of the patch routine, which is the initial PC upon exiting BDM. Result Data: None As an example, consider the following code segment. It outputs a character from the MC68340 serial module channel A. CHKSTAT: MOVE.B SRA,D0 Move serial status to D0 BNE.B...

  • Page 223

    NEXT CMD "CMD COMPLETE" NEXT CMD "ILLEGAL" "NOT READY" Operand Data: None Result Data: The “command complete” response ($0FFFF) is returned during the next shift operation. 5-86 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 224: Future Commands

    Freescale Semiconductor, Inc. 5.6.2.8.16 Future Commands. Unassigned command opcodes are reserved by Motorola for future expansion. All unused formats within any revision level will perform a NOP and return the ILLEGAL command response. 5.6.3 Deterministic Opcode Tracking The CPU32 utilizes deterministic opcode tracking to trace program execution. Two signals, IPIPE and IFETCH , provide all information required to analyze instruction pipeline operation.

  • Page 225: Opcode Tracking During Loop Mode

    IFETCH returns to normal operation with the first fetch after exiting loop mode. 5-88 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 226: Instruction Execution Timing

    5.7.1.3 BUS CONTROLLER RESOURCES. The bus controller consists of the instruction prefetch controller, the write pending buffer, and the microbus controller. These three resources transact all reads, writes, and instruction prefetches required for instruction execution. MOTOROLA MC68340 USER’S MANUAL 5- 89 For More Information On This Product, Go to: www.freescale.com...

  • Page 227: Instruction Pipeline

    If instruction prefetches, rather than operand accesses, were given 5-90 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 228: Write Pending Buffer

    A and B is the smaller tail of A and the head of B. INSTRUCTION A INSTRUCTION B INSTRUCTION C OVERLAP OVERLAP Figure 5-31. Simultaneous Instruction Execution MOTOROLA MC68340 USER’S MANUAL 5- 91 For More Information On This Product, Go to: www.freescale.com...

  • Page 229: Effects Of Wait States

    To calculate an instruction time estimate, the entire code sequence must be 5-92 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 230: Effects Of Negative Tails

    Refilling forces a two-clock idle period at the end of the change-of-flow instruction. This idle period can be used to prefetch an additional word on the new instruction path. MOTOROLA MC68340 USER’S MANUAL 5- 93 For More Information On This Product,...

  • Page 231: Instruction Stream Timing Examples

    EA. One clock is saved between instructions since that is the minimum time of the individual head and tail numbers. Instructions MOVE.W A1, (A0) ADDQ.W #1, (A0) CLR.W $30 (A1) 5-94 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 232: Timing Example 2-branch Instructions

    FOR 3 FETCH INSTRUCTION OFFSET NEXT MOVEQ TAKEN TAKEN TAKEN CONTROLLER CALC INST. EXECUTION MOVEQ BLE.B NOT TAKEN TIME #7,D1 D1,D0 Figure 5-34. Example 2—Branch Taken MOTOROLA MC68340 USER’S MANUAL 5- 95 For More Information On This Product, Go to: www.freescale.com...

  • Page 233: Timing Example 3-negative Tails

    CONTROLLER INSTRUCTION INSTRUCTION OFFSET MOVE MOVEQ TAKEN TAKEN CONTROLLER CALC TO D0 EXECUTION BRA.W FARAWAY MOVEQ #7,D1 MOVE.L D1,D0 TIME Figure 5-36. Example 3—Branch Negative Tail 5-96 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 234: Instruction Timing Tables

    Assuming that no trailing write exists from the previous instruction, EA calculation requires six clocks. Replacement fetch for the EA occurs during these six clocks, leaving a head of MOTOROLA MC68340 USER’S MANUAL 5- 97 For More Information On This Product,...

  • Page 235

    MOVES, MOVEP, MUL.L, DIV.L, CHK2, CMP2, and DBcc) are not permitted to begin until the extension word has been in the instruction pipeline for at least one cycle. This does not apply to long offsets or displacements. 5-98 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 236: Fetch Effective Address

    4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the head until the head reaches zero, at which time additional clocks must be added to both the tail and cycle counts. MOTOROLA MC68340 USER’S MANUAL 5- 99 For More Information On This Product, Go to: www.freescale.com...

  • Page 237: Calculate Effective Address

    4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the head until the head reaches zero, at which time additional clocks must be added to both the tail and cycle counts. 5-100 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 238: Move Instruction

    The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. MOTOROLA MC68340 USER’S MANUAL 5- 101 For More Information On This Product, Go to: www.freescale.com...

  • Page 239: Arithmetic/logic Instructions

    Footnotes indicate when to account for the appropriate EA times. The total number of clock cycles is outside the parentheses. 5-102 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 240

    CEA , Dn 3(0/1/0) TBL(su) (Op) CEA , Dn 33-35(2X/1/0) TBLSN Dn:Dm, Dp 30-34(0/2/0) TBLSN (Save) * CEA , Dn 3(0/1/0) TBLSN (Op) CEA , Dn 35-39(2X/1/0) MOTOROLA MC68340 USER’S MANUAL 5- 103 For More Information On This Product, Go to: www.freescale.com...

  • Page 241

    5.7.1.6 Instruction Execution Time Calculations. A save operation is not run for long-word divide and multiply instructions when FEA 5-104 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 242: Immediate Arithmetic/logic Instructions

    For long-word bus cycles, add two clocks to the tail and to the number of cycles. An # fetch EA time must be added for this instruction: FEA OPER MOTOROLA MC68340 USER’S MANUAL 5- 105 For More Information On This Product, Go to: www.freescale.com...

  • Page 243: Binary-coded Decimal And Extended Instructions

    Dn, Dm 4(0/1/0) SBCD (An), (Am) 12(2/1/1) ADDX Dn, Dm 2(0/1/0) ADDX (An), (Am) 10(2/1/1) SUBX Dn, Dm 2(0/1/0) SUBX (An), (Am) 10(2/1/1) CMPM (An)+, (Am)+ 8(2/1/0) 5-106 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 244: Single Operand Instructions

    X = There is one bus cycle for byte and word operands and two bus cycles for long-word operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles. MOTOROLA MC68340 USER’S MANUAL 5- 107 For More Information On This Product, Go to: www.freescale.com...

  • Page 245: Shift/rotate Instructions

    63): max (3 mod (n 1,2), 6). 3. Head and cycle times are calculated as follows: (count 8): max (2 mod (n,2), 6). Clocks Shift Counts 5-108 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 246: Bit Manipulation Instructions

    BTST Dn, Dm 4(0/1/0) BTST #, FEA 4(0/2/0) BTST Dn, FEA 8(0/1/0) An # fetch EA time must be added for this instruction: FEA OPER MOTOROLA MC68340 USER’S MANUAL 5- 109 For More Information On This Product, Go to: www.freescale.com...

  • Page 247: Conditional Branch Instructions

    DBcc (F, not 1, taken) 10(0/2/0) DBcc (T, not taken) 6(0/1/0) DBcc (F, 1, not taken) 8(0/1/0) DBcc (F, not 1, taken) 10(0/0/0) In loop mode 5-110 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 248: Control Instructions

    EA, and the operation execution times, and combine in the order listed using the equations given in 5.7.1.6 Instruction Execution Time Calculation. MOTOROLA MC68340 USER’S MANUAL 5- 111 For More Information On This Product, Go to: www.freescale.com...

  • Page 249: Exception-related Instructions And Operations

    To calculate the total operation time, calculate the save, the calculate EA, and the operation execution times, and combine in the order listed, using the equations given in 5.7.1.6 Instruction Execution Time Calculation. 5-112 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 250: Save And Restore Operations

    = Maximum time is indicated (certain data or mode combinations execute faster). Y = If a bus error occurred during a write cycle, the cycle is rerun by the RTE. MOTOROLA MC68340 USER’S MANUAL 5- 113 For More Information On This Product,...

  • Page 251: Dma Controller Module

    • Operand Packing and Unpacking for Dual-Address Transfers • Supports All Bus-Termination Modes • Provides Two-Clock-Cycle Internal Module Access • Provides Two-Clock-Cycle External Access Using MC68340 Chip Selects • Provides Full DMA Handshake for Burst Transfers and Cycle Steal INTERRUPT...

  • Page 252: Dma Module Overview

    DMA operations can greatly increase overall system performance. The MC68340 DMA module consists of two, independent, programmable channels. The term DMA is used throughout this section to reference either channel 1 or channel 2 since the two are functionally equivalent.

  • Page 253: Single-address Transfers

    Freescale Semiconductor, Inc. PERIPHERAL MEMORY PERIPHERAL PERIPHERAL MEMORY Figure 6-2. Single-Address Transfers MEMORY MEMORY .. . Figure 6-3. Dual-Address Transfer MOTOROLA MC68340 USER’S MANUAL 6- 3 For More Information On This Product, Go to: www.freescale.com...

  • Page 254: Dma Module Signal Definitions

    Only internal requests can limit the amount of bus utilization. The percentage of the bandwidth that the DMA channel can use during a transfer can be selected by the CCR BB field. MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 255: Internal Request, Maximum Rate

    The DREQ pulse generated by the device must be asserted during two consecutive falling edges of the clock to be recognized as valid. MOTOROLA MC68340 USER’S MANUAL 6- 5 For More Information On This Product,...

  • Page 256: Data Transfer Modes

    For serial transmit, the DMA reads data from memory and writes data to the serial transmit buffer (TB) register. Only dual-address mode can be used with the serial module. The MC68340 on-chip peripherals do not support single-address transfers.

  • Page 257: Single-address Read

    See 6.7 Register Description for more information. If external 32-bit devices and a 32-bit bus are used with the MC68340, the DMA can control 32-bit transfers between devices that use the 32-bit bus in single-address mode only.

  • Page 258: Single-address Read Timing (external Burst)

    3. DREQx must be asserted while DACKx is asserted and meet the setup and hold times for more than one DMA transfer to be recognized. Figure 6-5. Single-Address Read Timing (External Burst) MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 259

    Freescale Semiconductor, Inc. MOTOROLA MC68340 USER’S MANUAL 6- 9 For More Information On This Product, Go to: www.freescale.com...

  • Page 260: Single-address Write

    2. DREQx must be asserted while DACKx is asserted, and meet the setup and hold times for more than one DMA transfer to be recognized. Figure 6-7. Single-Address Write Timing (External Burst) 6-10 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 261

    Freescale Semiconductor, Inc. MOTOROLA MC68340 USER’S MANUAL 6- 11 For More Information On This Product, Go to: www.freescale.com...

  • Page 262: Dual-address Mode

    (read) cycle when the source device makes a request. See Figures 6-9 and 6-10 for timing diagrams of dual-address read for external burst and cycle steal modes. 6-12 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 263

    Freescale Semiconductor, Inc. MOTOROLA MC68340 USER’S MANUAL 6- 13 For More Information On This Product, Go to: www.freescale.com...

  • Page 264: Dual-address Write

    DHR. The data in the DHR is written to the device or memory selected by the address in the DAR, the destination function codes in 6-14 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 265

    (write) cycle when the destination device makes a request. See Figures 6-11 and 6-12 for timing diagrams of dual-address write for external burst and cycle steal modes. MOTOROLA MC68340 USER’S MANUAL 6- 15 For More Information On This Product, Go to: www.freescale.com...

  • Page 266

    Freescale Semiconductor, Inc. 6-16 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 267

    Freescale Semiconductor, Inc. MOTOROLA MC68340 USER’S MANUAL 6- 17 For More Information On This Product, Go to: www.freescale.com...

  • Page 268: Dma Channel Operation

    If the transfer is from memory to a peripheral device, the DAR is loaded with the address of the peripheral data register. This address may be any byte 6-18 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 269: Data Transfers

    CCR. The sequencing of the address bus follows the programming of the CCR and address register (SAR or DAR) for the channel. MOTOROLA MC68340 USER’S MANUAL 6- 19 For More Information On This Product, Go to: www.freescale.com...

  • Page 270: Channel Termination

    The fast termination option is described in Section 3 Bus Operation and Section 4 System Integration Module. 6-20 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 271: Fast Termination Option (cycle Steal)

    DMA cycle may result on every burst transfer. Normally, DREQ is negated when DACK is returned. In the burst mode with fast termination selected, a new cycle starts even if DREQ is negated simultaneously with DACK assertion. MOTOROLA MC68340 USER’S MANUAL 6- 21 For More Information On This Product, Go to: www.freescale.com...

  • Page 272: Register Description

    S/U indicates that access is governed by the SUPV bit in the module configuration register (MCR). Unimplemented memory locations return logic zero when accessed. All registers support both byte and word transfers. 6-22 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 273: Module Configuration Register (mcr)

    The MCR is not affected by a CPU32 RESET instruction. MOTOROLA MC68340 USER’S MANUAL 6- 23 For More Information On This Product,...

  • Page 274

    The DMA module uses only one set of FRZx bits for both channels. A read or write to either MCR accesses the same FRZx control bits. 6-24 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 275

    These bits establish bus arbitration priority level among modules that have the capability of becoming bus master. For the MC68340, the MAID bits are used to arbitrate between DMA channel 1 and channel 2. If both channels are programmed with the same MAID level, channel 1 will have priority.

  • Page 276: Interrupt Register (intr)

    The CCR can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). 6-26 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 277

    (write to memory), and the control signals ( DREQ , DACK , and DONE ) are used by the requesting device to provide data during the destination (write) portion of the transfer. MOTOROLA MC68340 USER’S MANUAL 6- 27 For More Information On This Product, Go to: www.freescale.com...

  • Page 278

    Table 6-2 defines these bits. Table 6-2. SSIZEx Encoding Bit 9 Bit 8 Definition Long Word* Byte Word Not Used *External logic is required to complete a long- word transfer. 6-28 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 279

    Table 6-5. BBx Encoding and Bus Bandwidth REQ Field BB Field Bus Bandwidth Bit 5 Bit 4 Bit 3 Bit 2 Definition (Clock Periods) 100% 1024 MOTOROLA MC68340 USER’S MANUAL 6- 29 For More Information On This Product, Go to: www.freescale.com...

  • Page 280: Channel Status Register (csr)

    The destination holding register is not used for these transfers because the data is transferred directly into the destination location. The MC68340 on-chip peripherals do not support single-address transfers. 0 = The DMA channel runs dual-address transfers.

  • Page 281

    The CSR is cleared by writing $7C to its location. The DMA channel cannot be started until the CSR DONE, BES, BED, CONF and BRKP bits are cleared. MOTOROLA MC68340 USER’S MANUAL 6- 31 For More Information On This Product, Go to: www.freescale.com...

  • Page 282: Function Code Register (fcr)

    3-bit SFC and DFC capability, it cannot emulate FC3 = 1 at this time. However, it is recommended that FC3 be set to one to distinguish DMA or CPU access during debug. 6-32 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 283: Source Address Register (sar)

    The DAR can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). MOTOROLA MC68340 USER’S MANUAL 6- 33 For More Information On This Product,...

  • Page 284: Byte Transfer Counter Register (btc)

    DMA module is enabled (i.e., the STP bit in the MCR is cleared). BTC1, BTC2 $794, $7B4 RESET: RESET: U = Unaffected by reset Supervisor/User 6-34 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 285: Data Packing

    BYTE1 BYTE1 BYTE0 BYTE1 BYTE0 BYTE1 BYTE2 BYTE3 BYTE2 BYTE3 BYTE0 BYTE1 BYTE0 BYTE1 BYTE2 BYTE3 BYTE2 BYTE3 Figure 6-16. Packing and Unpacking of Operands MOTOROLA MC68340 USER’S MANUAL 6- 35 For More Information On This Product, Go to: www.freescale.com...

  • Page 286: Dma Channel Initialization Sequence

    6.9 DMA CHANNEL INITIALIZATION SEQUENCE The following paragraphs describe DMA channel initialization and operation. If the DMA capability of the MC68340 is being used, the initialization steps should be performed during the part initialization sequence. The mode operation steps should be performed to start a DMA transfer.

  • Page 287: Dma Channel Operation In Single-address Mode

    • Select the source and destination sizes (SSIZE and DSIZE fields). • Select internal request, external burst request mode, or external cycle steal request mode (REQ field). MOTOROLA MC68340 USER’S MANUAL 6- 37 For More Information On This Product, Go to: www.freescale.com...

  • Page 288: Dma Channel Example Configuration Code

    The following are examples of configuration sequences for a DMA channel in single- and dual-addressing modes. *************************************************************************** * MC68340 basic DMA channel register initialization example code. * This code is used to initialize the 68340's internal DMA channel * registers, providing basic functions for operation.

  • Page 289

    * The number of bytes to be transferred is $C or 3 long words MOVE.L NUMBYTE,DMABTC1(A0) * Channel control reg. init. and Start DMA transfers MOTOROLA MC68340 USER’S MANUAL 6- 39 For More Information On This Product, Go to: www.freescale.com...

  • Page 290

    *************************************************************************** Example 2: Internal Request Generation, Memory to Memory Transfers. *************************************************************************** * MC68340 basic DMA channel register initialization example code. * This code is used to initialize the 68340's internal DMA channel * registers, providing basic functions for operation. * The code sets up channel 1 for internal request generation * memory to memory transfers.

  • Page 291

    * start the DMA transfers. MOVE.W #$0E8D,DMACCR1(A0) *************************************************************************** *************************************************************************** Example 3: Internal Request Generation, Memory Block Initialization. *************************************************************************** * MC68340 basic DMA channel register initialization example code. MOTOROLA MC68340 USER’S MANUAL 6- 41 For More Information On This Product, Go to: www.freescale.com...

  • Page 292

    * Clear STR (start) bit to prevent the channel from starting a transfer early. CLR.W DMACCR1(A0) * Initialize interrupt reg. * Interrupt priority at 7, interrupt vector at $42. 6-42 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 293

    *************************************************************************** Example 4: Cycle Steal Request Generation, Dual-Address Transfers. *************************************************************************** * MC68340 basic DMA channel register initialization example code. * This code is used to initialize the 68340's internal DMA channel * registers, providing basic functions for operation. * The code sets up channel 1 for external cycle steal request generation, * dual-address transfers.

  • Page 294

    * Clear the DONE, BES, BED, CONF and BRKP bits to allow channel to startup. MOVE.B #$7C,DMACSR1(A0) * Initialize function code reg. * DMA space, supervisor data space for source and destination. MOVE.B #$DD,DMAFCR1(A0) * Initialize source operand address 6-44 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 295

    * Source size is byte, destination size is word. REQ is external cycle steal. * dual-address transfers, start the DMA transfers. MOVE.W #$1DB1,DMACCR1(A0) *************************************************************************** *************************************************************************** MOTOROLA MC68340 USER’S MANUAL 6- 45 For More Information On This Product, Go to: www.freescale.com...

  • Page 296: Simplified Block Diagram

    Freescale Semiconductor, Inc. SECTION 7 SERIAL MODULE The MC68340 serial module is a dual universal asynchronous/synchronous receiver/transmitter that interfaces directly to the CPU32 processor via the intermodule bus (IMB). The serial module, shown in Figure 7-1, consists of the following major functional areas: •...

  • Page 297: Module Overview

    • False-Start Bit Detection • Line-Break Detection and Generation • Detection of Breaks Originating in the Middle of a Character • Start/End Break Interrupt/Status • On-Chip Crystal Oscillator MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 298: Serial Communication Channels A And B

    These interrupts are described in 7.4 Register Description and Programming. The interrupt status register (ISR) is read by the CPU32 to determine all MOTOROLA MC68340 USER’S MANUAL 7- 3 For More Information On This Product, Go to: www.freescale.com...

  • Page 299: Comparison Of Serial Module To Mc68681

    The serial module is code compatible with the MC68681 with some modifications. The following paragraphs describe the differences. The programming model is slightly altered. The supervisor/user block in the MC68340 closely follows the MC68681. The supervisor-only block has the following changes: •...

  • Page 300: Crystal Input Or External Clock (x1)

    X1, the X2 output must be left open. Refer to Section 10 Applications for an example of a clock driver circuit. MOTOROLA MC68340 USER’S MANUAL 7- 5 For More Information On This Product, Go to: www.freescale.com...

  • Page 301: External Input (sclk)

    (OP). 7.2.9 Channel B Request-To-Send ( RTSB ) This active-low output signal is programmable as the channel B request-to-send or as a dedicated parallel output. MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 302: Rtsb

    FIFO is full. 7.2.13.3 OP4. When used for this function, this output is controlled by bit 4 in the OP. MOTOROLA MC68340 USER’S MANUAL 7- 7 For More Information On This Product, Go to: www.freescale.com...

  • Page 303: Operation

    Figure 7-4. The paragraphs that follow contain descriptions for both these functions in reference to this diagram. For detailed register information, refer to 7.4 Register Description and Programming. MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 304: Transmitter And Receiver Functional Diagram

    ....Figure 7-4. Transmitter and Receiver Functional Diagram MOTOROLA MC68340 USER’S MANUAL 7- 9 For More Information On This Product, Go to: www.freescale.com...

  • Page 305: Transmitter

    CPU32 loads a new character into the transmitter buffer (TB). If a disable command is sent to the transmitter, it continues operating until the character in the 7-10 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 306: Receiver

    RxRDY bits in the SR are set. The RxDx signal must return to a high condition for at least one-half bit time before a search for the next start bit begins. MOTOROLA MC68340 USER’S MANUAL 7- 11 For More Information On This Product,...

  • Page 307: Fifo Stack

    The receive buffer consists of the FIFO and a receiver shift register connected to the RxDx (refer to Figure 7-4). Data is 7-12 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 308

    FIFO can still be read by the CPU32. If the receiver is reset, the FIFO stack and all receiver status bits, corresponding output ports, and interrupt request are reset. No additional characters are received until the receiver is re-enabled. MOTOROLA MC68340 USER’S MANUAL 7- 13 For More Information On This Product, Go to: www.freescale.com...

  • Page 309: Looping Modes

    Received parity is not checked and is not recalculated for transmission. Stop bits are transmitted as received. A received break is echoed as received until the next valid start bit is detected. 7-14 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 310: Multidrop Mode

    After a slave receives a block of data, the slave station's CPU disables the receiver and initiates the process again. MOTOROLA MC68340 USER’S MANUAL 7- 15 For More Information On This Product, Go to: www.freescale.com...

  • Page 311: Multidrop Mode Timing Diagram

    In multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the 7-16 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 312: Read Cycles

    A list of serial module registers and their associated addresses are shown in Figure 7-9. The mode, status, command, and clock-select registers are duplicated for each channel to provide independent operation and control. MOTOROLA MC68340 USER’S MANUAL 7- 17 For More Information On This Product, Go to: www.freescale.com...

  • Page 313

    The module is enabled when the STP bit in the MCR is cleared. The module is disabled when the STP bit in the MCR is set. 7-18 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 314: Serial Module Programming Model

    Only the MCR can be accessed when the module is disabled (i.e., the STP bit in the MCR is set). $700 FRZ1 FRZ0 ICCS SUPV IARB RESET: Read/Write Supervisor Only MOTOROLA MC68340 USER’S MANUAL 7- 19 For More Information On This Product, Go to: www.freescale.com...

  • Page 315

    4 in MR2. The data is captured on the CTS pins on the rising edge of the clock. 0 = The crystal clock is the clear-to-send input capture clock for both channels. 7-20 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 316: Interrupt Level Register (ilr)

    When the serial module is enabled (i.e., the STP bit in the MCR is cleared), this register can be read or written to at any time while in supervisor mode. MOTOROLA MC68340 USER’S MANUAL 7- 21 For More Information On This Product,...

  • Page 317: Mode Register 1 (mr1)

    0 = Bit 5 for channel B and bit 1 for channel A in the ISR reflect the channel receiver- ready status. These ISR bits are set when a character has been received and are cleared when the CPU32 reads the receive buffer. 7-22 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 318

    These bits select the number of data bits per character to be transmitted. The character length listed in Table 7-3 does not include start, parity, or stop bits. MOTOROLA MC68340 USER’S MANUAL 7- 23 For More Information On This Product,...

  • Page 319: Status Register (sr)

    A/D bit. This bit is valid only when the RxRDY bit is set. 0 = No parity error has occurred. 7-24 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 320

    CPU32. This bit is set when a character is transferred from the receiver shift register to the FIFO. 0 = The CPU32 has read the receiver buffer, and no characters remain in the FIFO after this read. MOTOROLA MC68340 USER’S MANUAL 7- 25 For More Information On This Product, Go to: www.freescale.com...

  • Page 321: Clock-select Register (csr)

    Set 1 Set 2 134.5 134.5 1200 1200 1050 2000 2400 2400 4800 4800 7200 1800 9600 9600 38.4k 19.2k 76.8k 38.4k SCLK/16 SCLK/16 SCLK/1 SCLK/1 7-26 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 322: Command Register (cr)

    This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). CRA, CRB $712, $71A MISC3 MISC2 MISC1 MISC0 RESET: Write Only Supervisor/User MOTOROLA MC68340 USER’S MANUAL 7- 27 For More Information On This Product, Go to: www.freescale.com...

  • Page 323

    OE bits (in the SR). This command is also used in the block mode to clear all error bits after a data block is received. Reset Break-Change Interrupt—The reset break-change interrupt command clears the delta break (DBx) bits in the ISR. 7-28 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 324

    If the transmitter is already disabled, this command has no effect. Do Not Use—Do not use this bit combination because the result is indeterminate. MOTOROLA MC68340 USER’S MANUAL 7- 29 For More Information On This Product, Go to: www.freescale.com...

  • Page 325: Receiver Buffer (rb)

    TxRDY bit in the channel's SR is set. A write to the transmitter buffer clears the TxRDY bit, inhibiting any more 7-30 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 326: Input Port Change Register (ipcr)

    1 = The current state of the respective CTS input is negated. 0 = The current state of the respective CTS input is asserted. MOTOROLA MC68340 USER’S MANUAL 7- 31 For More Information On This Product, Go to: www.freescale.com...

  • Page 327: Auxiliary Control Register (acr)

    1 = A change-of-state has occurred at one of the CTS inputs and has been selected to cause an interrupt by programming bit 1 and/or bit 0 of the ACR. 0 = The CPU32 has read the IPCR. 7-32 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 328

    0 = The CPU32 has issued a channel A reset break-change interrupt command. Refer to 7.4.1.7 Command Register (CR) for more information on the reset break-change interrupt command. MOTOROLA MC68340 USER’S MANUAL 7- 33 For More Information On This Product, Go to: www.freescale.com...

  • Page 329: Interrupt Enable Register (ier)

    RxRDYA TxRDYA RESET: Write Only Supervisor/User COS—Change-of-State 1 = Enable interrupt 0 = Disable interrupt DBB—Delta Break B 1 = Enable interrupt 0 = Disable interrupt 7-34 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 330: Input Port (ip)

    The information contained in these bits is latched and reflects the state of the input pins at the time that the IP is read. NOTE These bits have the same function and value of the IPCR bits 1 and 0. MOTOROLA MC68340 USER’S MANUAL 7- 35 For More Information On This Product, Go to: www.freescale.com...

  • Page 331: Output Port Control Register (opcr)

    Write Only Supervisor/User NOTE OP bits 7, 5, 3, and 2 are not pinned out on the MC68340; thus changing bits 7, 5, 3, and 2 of this register has no effect. OP6—Output Port 6/ T RDYA 1 = The OP6/ T RDYA pin functions as the transmitter-ready signal for channel A.

  • Page 332: Output Port Data Register (op)

    Write Only Supervisor/User NOTE OP bits 7, 5, 3, and 2 are not pinned out on the MC68340; thus, changing these bits has no effect. OP6, OP4, OP1, OP0 —Output Port Parallel Outputs 1 = These bits can be set by writing a one to the bit position(s) at this address.

  • Page 333: Mode Register 2 (mr2)

    RTS control, RTS control is disabled for both since this is an incorrect configuration. 0 = Clearing this bit has no effect on the transmitter RTS . 7-38 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 334

    1.250 0.813 1.313 0.875 1.375 0.938 1.438 1.000 1.500 1.563 1.563 1.625 1.625 1.688 1.688 1.750 1.750 1.813 1.813 1.875 1.875 1.938 1.938 2.000 2.000 MOTOROLA MC68340 USER’S MANUAL 7- 39 For More Information On This Product, Go to: www.freescale.com...

  • Page 335: Programming

    (beginning of a break). SIRQ then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor. 7-40 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 336: Serial Module Programming Flowchart

    POINT TO CHANNEL B CALL CHCHK ENABLE CHANNEL B'S TRANSMITTER SINITR SAVE CHANNEL B STATUS RETURN Figure 7-10. Serial Module Programming Flowchart (1 of 5) MOTOROLA MC68340 USER’S MANUAL 7- 41 For More Information On This Product, Go to: www.freescale.com...

  • Page 337

    READY SNDCHR SEND CHARACTER TO TRANSMITTER RxCHK RECEIVER WAITED SET RECEIVER- RECEIVED TOO LONG NEVER-READY FLAG CHARACTER Figure 7-10. Serial Module Programming Flowchart (2 of 5) 7-42 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 338

    SET PARITY ERROR FLAG CHRCHK GET CHARACTER FROM RECEIVER SAME AS CHARACTER TRANSMITTED SET INCORRECT CHARACTER FLAG Figure 7-10. Serial Module Programming Flowchart (3 of 5) MOTOROLA MC68340 USER’S MANUAL 7- 43 For More Information On This Product, Go to: www.freescale.com...

  • Page 339

    REMOVE BREAK CHARACTER FROM RECEIVER FIFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS SIRQR Figure 7-10. Serial Module Programming Flowchart (4 of 5) 7-44 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 340

    FEED CHARACTER TO FEED CHARACTER TO CHANNEL A CHANNEL B TRANSMITTER TRANSMITTER OUTCHR POUTCHR RETURN RETURN Figure 7-10. Serial Module Programming Flowchart (5 of 5) MOTOROLA MC68340 USER’S MANUAL 7- 45 For More Information On This Product, Go to: www.freescale.com...

  • Page 341: Serial Module Initialization Sequence

    7.5 SERIAL MODULE INITIALIZATION SEQUENCE The following paragraphs discuss a suggested method for initializing the serial module. 7.5.1 Serial Module Configuration If the serial capability of the MC68340 is being used, the following steps are required to properly initialize the serial module. NOTE The serial module registers can only be accessed by byte operations.

  • Page 342: Serial Module Example Configuration Code

    The following code is an example of a configuration sequence for the serial module. *************************************************************************** * MC68340 basic serial module register initialization example code. * This code is used to initialize the 68340's internal serial module registers, * providing basic functions for operation.

  • Page 343

    #$30,CRA(A0) Issue reset transmitter command * SET BAUD RATE SET 2 MOVE.B #$80,ACR(A0) * MODE REGISTER 1 MOVE.B #$93,MR1A(A0) 8 bits, no parity, auto RTS control 7-48 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 344

    Set 9600 baud for RX and TX * SET RTSA ACTIVE MOVE.B #$01,OP_BS(A0) set RTSA /OP0 output * ENABLE PORT MOVE.B #$45,CRA(A0) Reset error status, enable RX & TX *************************************************************************** *************************************************************************** MOTOROLA MC68340 USER’S MANUAL 7- 49 For More Information On This Product, Go to: www.freescale.com...

  • Page 345: Module Overview

    SECTION 8 TIMER MODULES Each MC68340 timer module contains a counter/timer (timer 1 and timer 2) as shown in Figure 8-1. Each timer interfaces directly to the CPU32 via the intermodule bus (IMB). Each timer consists of the following major areas: •...

  • Page 346: Timer And Counter Functions

    (TOUTx). Refer to 8.3.1 Input Capture/Output Compare for additional information on this mode. MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 347: Clock Selection Logic

    This mechanism allows the timer registers to be accessed and programmed. Refer to 8.4 Register Description for additional information. MOTOROLA MC68340 USER’S MANUAL 8- 3 For More Information On This Product, Go to: www.freescale.com...

  • Page 348: Interrupt Control Logic

    The term negate or negation indicates that a signal is inactive or false. MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 349: Timer Input (tin1, Tin2)

    TINx is internally synchronized to the system clock to guarantee that a valid TINx level is recognized. Additionally, the high and low levels of TINx must each be stable MOTOROLA MC68340 USER’S MANUAL 8- 5 For More Information On This Product,...

  • Page 350: Timer Gate ( Tgate1 , Tgate2 )

    If the timing gate is enabled (TGE bit of the CR is set), the TG bit is set by the rising edge of TGATE . Shadowing is disabled until the TG bit is cleared by writing a one MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 351: Input Capture/output Compare Mode

    The value in the PREL1 specifies the frequency, and the COM determines the pulse width. The pulse widths can be changed by writing a new value to the COM. MOTOROLA MC68340 USER’S MANUAL 8- 7 For More Information On This Product, Go to: www.freescale.com...

  • Page 352: Square-wave Generator

    If TGATE is negated when it is enabled to control the timer (TGE = 1), the prescaler and counter are disabled. Additionally, the SR TG bit is set, indicating that TGATE negated. The SR ON bit is cleared, indicating that the timer is disabled. If TGATE is MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 353: Variable Duty-cycle Square-wave Generator

    PREL2 (N2) to be loaded into the counter, and the counter begins counting down from this value. Each MOTOROLA MC68340 USER’S MANUAL 8- 9 For More Information On This Product,...

  • Page 354: Variable-width Single-shot Pulse Generator

    This mode can be selected by programming the CR MODE bits to 011. 8-10 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 355: Variable-width Single-shot Pulse Generator Mode

    If TGATE is not enabled (TGE = 0), TGATE has no effect on the operation of the timer. In this case, the counter would begin counting on the falling edge of the counter clock MOTOROLA MC68340 USER’S MANUAL 8- 11 For More Information On This Product,...

  • Page 356: Pulse-width Measurement

    SR are set. If the counter counts down to $0000, a timeout is detected. This sets the SR TO, and the clears the COM bit. At timeout, the next falling edge of the counter clock 8-12 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 357: Period Measurement

    Subsequent transitions on TGATE do not re-enable the counter. See Figure 8-9 for a depiction of this mode. The SR TGL bit reflects the level of TGATE at all times. MOTOROLA MC68340 USER’S MANUAL 8- 13 For More Information On This Product,...

  • Page 358: Event Count

    As another example, by connecting AS to TINx, the number of bus cycles to complete a sequence of instructions could be counted. This mode can be selected by programming the CR MODEx bits to 110. 8-14 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 359: Event Count Mode

    POx bits in the SR are readable and can be thought of as an extension of the least significant bits in the CNTR. MOTOROLA MC68340 USER’S MANUAL 8- 15 For More Information On This Product,...

  • Page 360: Timer Bypass

    SWR must be a zero to change the value of TOUTx. Changing the value of the CR OCx bits determines the level of TOUTx as shown in Table 8-1. 8-16 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 361: Write Cycles

    An FC column designation of S indicates that register access is restricted to supervisor only. A designation of S/U indicates that access is governed by the SUPV bit in the module configuration register (MCR). MOTOROLA MC68340 USER’S MANUAL 8- 17 For More Information On This Product, Go to: www.freescale.com...

  • Page 362: Timer Module Programming Model

    The MCR is not affected by a CPU32 RESET instruction. $600, $640 FRZ1 FRZ0 SUPV IARB3 IARB2 IARB1 IARB0 RESET: Supervisor Only 8-18 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 363

    IARB field is $0, which prevents this module from arbitrating during the interrupt acknowledge cycle. The system software should initialize the IARB field to a value from $F (highest priority) to $1 (lowest priority). MOTOROLA MC68340 USER’S MANUAL 8- 19 For More Information On This Product, Go to: www.freescale.com...

  • Page 364: Interrupt Register (ir)

    TG, and TC bits in the SR. The prescaler is loaded with $FF, the counter is set to $0000, and the SR COM bit is cleared. When this bit is zero, the timer is disabled. 8-20 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 365

    The TOUTx of one timer can be fed externally into the TINx input of the other timer, resulting in a 32-bit counter if the prescalers are not used and a 48-bit counter if they are used. MOTOROLA MC68340 USER’S MANUAL 8- 21 For More Information On This Product, Go to: www.freescale.com...

  • Page 366

    Caution should be used when modifying the OC bits near timer events. Table 8-6. OCx Encoding TOUTx MODE Disabled Toggle Mode Zero Mode One Mode 8-22 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 367: Status Register (sr)

    0 = The bit(s) that caused the interrupt condition has been cleared. If an IRQ signal has been asserted, it is negated when this bit is cleared. MOTOROLA MC68340 USER’S MANUAL 8- 23 For More Information On This Product, Go to: www.freescale.com...

  • Page 368

    0 = TOUTx is a logic zero, or the pin is three-stated. COM—Compare Bit This bit is used to indicate when the counter output value is at or between the value in the COM and $0000 (timeout). 8-24 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 369: Counter Register (cntr)

    (i.e. the STP bit in the MCR is cleared). However, a write to this register must be completed before timeout for the new value to be reliably loaded into the counter. MOTOROLA MC68340 USER’S MANUAL 8- 25 For More Information On This Product,...

  • Page 370: Preload 2 Register (prel2)

    The COM can also be used to indicate that the timer is approaching timeout. 8-26 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 371: Timer Module Initialization Sequence

    Since both timers are functionally equivalent, only one timer module will be referenced. 8.5.1 Timer Module Configuration If the timer capability of the MC68340 is being used, the following steps should be followed to initialize a timer module properly. Note that this sequence must be done for each timer module used.

  • Page 372: Timer Module Example Configuration Code

    The following code is an example of a configuration sequence for the timer module. *************************************************************************** * MC68340 basic timer module register initialization example code. * This code is used to initialize the 68340's internal timer module * registers, providing basic functions for operation.

  • Page 373

    *************************************************************************** *************************************************************************** *************************************************************************** * MC68340 basic timer module register initialization example code. * This code is used to initialize the 68340's internal timer module * registers, providing basic functions for operation. * It sets up timer1 for pulse-width measurement. In this mode, the number * of clock cycles during a particular event are counted.

  • Page 374

    * the counter. Use the selected clock for the counter clock, and enable it. * Selected clock is 1/2 system's freq. Pulse-width measurement, * disable TOUT. 8-30 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 375

    * in CNTR1 must be read, inverted, and incremented by 1. MOVE.W CNTR1(A0),D0 NOT.W ADDQ.W #$1,DO * D0 contains the number of cycles counted. *************************************************************************** *************************************************************************** MOTOROLA MC68340 USER’S MANUAL 8- 31 For More Information On This Product, Go to: www.freescale.com...

  • Page 376: Overview

    16-state controller, an instruction register, and two test data registers. A boundary scan register links all device signal pins into a single shift register. The test logic, implemented using static logic design, is independent of the device system logic. The MC68340 implementation provides the following capabilities: a.

  • Page 377: Tap Controller

    Freescale Semiconductor, Inc. An overview of the MC68340 implementation of IEEE 1149.1 is shown in Figure 9-1. The MC68340 implementation includes a 16-state controller, a 3-bit instruction register, and two test registers (a 1-bit bypass register and a 132-bit boundary scan register). This implementation includes a dedicated TAP consisting of the following signals: —...

  • Page 378: Boundary Scan Register

    The XTAL, X2, and XFC pins are associated with analog signals and are not included in the boundary scan register. All MC68340 bidirectional pins, except the open-drain I/O pins ( DONE1, DONE2, HALT, and RESET ), have a single register bit for pin data and an associated control bit in the boundary scan register.

  • Page 379

    (i.e., first to be shifted out) is defined as bit 0; the last bit to be shifted out is 131. The second column references one of the five MC68340 cell types depicted in Figures 9-3–9-7, which describe the cell structure for each type.

  • Page 380

    RxDA Input — IO.Ctl0 cs0.ctl — — O.Latch TxDA Output — IO.Cell db.ctl O.Latch RTSA Output — IO.Cell db.ctl CTSA I.Pin Input — IO.Cell db.ctl MOTOROLA MC68340 USER’S MANUAL 9- 5 For More Information On This Product, Go to: www.freescale.com...

  • Page 381

    I.Pin Input — NOTES: The noted pins are implemented differently than defined in the signal definition description: Input during Motorola factory test Output during Motorola factory test MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 382: Output Latch Cell (o.latch)

    1 – EXTEST TO NEXT 0 – OTHERWISE CELL INPUT UPDATE DR CLOCK DR FROM LAST SHIFT DR CELL Figure 9-4. Input Pin Cell (I.Pin) MOTOROLA MC68340 USER’S MANUAL 9- 7 For More Information On This Product, Go to: www.freescale.com...

  • Page 383: Active-high Output Control Cell (io.ctl1)

    CONTROL FROM TO OUTPUT SYSTEM ENABLE LOGIC (1 = DRIVE) SHIFT DR FROM CLOCK DR RESET LAST CELL UPDATE DR Figure 9-6. Active-Low Output Control Cell (IO.Ctl0) MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 384: Instruction Register

    The MC68340 IEEE 1149.1 implementation includes the three mandatory public instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS), but does not support any of the optional public instructions defined by IEEE 1149.1. One additional public instruction (HI-Z) provides the capability for disabling all device output drivers. The MC68340 MOTOROLA MC68340 USER’S MANUAL...

  • Page 385: Extest (000)

    9.4.1 EXTEST (000) The external test (EXTEST) instruction selects the 132-bit boundary scan register. EXTEST asserts internal reset for the MC68340 system logic to force a predictable benign internal state while performing external boundary scan operations. By using the TAP, the register is capable of a) scanning user-defined values into the output buffers, b) capturing values presented to input pins, c) controlling the direction of bidirectional pins, and d) controlling the output drive of three-state output pins.

  • Page 386: Bypass (x1x, 101)

    This creates a shift-register path from TDI to the bypass register and, finally, to TDO, circumventing the 132-bit boundary scan register. This instruction is used to enhance test efficiency when a component other than the MC68340 becomes the device under test. SHIFT DR...

  • Page 387: Non-ieee 1149.1 Operation

    Freescale Semiconductor, Inc. The MC68340 includes on-chip circuitry to detect the initial application of power to the device. Power-on reset (POR), the output of this circuitry, is used to reset both the system and IEEE 1149.1 logic. The purpose for applying POR to the IEEE 1149.1 circuitry is to avoid the possibility of bus contention during power-on.

  • Page 388: Minimum System Configuration

    10.1 MINIMUM SYSTEM CONFIGURATION One of the powerful features of the MC68340 is the small number of external components needed to create an entire system. The information contained in the following paragraphs details a simple high-performance MC68340 system (see Figure 10-1). This system configuration features the following hardware: •...

  • Page 389: Sample Crystal Circuit

    PLL, and larger values provide greater frequency stability. Figure 10-4 depicts examples of both an external filter capacitor and bypass capacitors for V CCSYN 10-2 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 390: Reset Circuitry

    CCSYN 10.1.2 Reset Circuitry Because it is optional, reset circuitry is not shown in Figure 10-1. The MC68340 holds itself in reset after power-up and asserts RESET to the rest of the system. If an external reset pushbutton switch is desired, an external reset circuit is easily constructed by using open-collector cross-coupled NAND gates to debounce the output from the switch.

  • Page 391: Rom Interface

    Figure 10-6. ROM Interface 10.1.5 Serial Interface The necessary circuitry to create an RS-232 interface with the MC68340 includes an external crystal and an RS-232 receiver/driver (see Figure 10-7). The resistor and capacitor values shown are typical; the crystal manufacturer's documentation should be consulted for specific recommendations on external component values.

  • Page 392: Memory Interface Information

    16-bit memory using the DMA channel single-address mode. 10.2.1 Using an 8-Bit Boot ROM Upon power-up, the MC68340 uses CS0 to begin operation. CS0 is a three-wait-state, 16- bit chip select, until otherwise programmed. If an 8-bit ROM is desired, external circuitry can be added to return an 8-bit DSACK in two wait states (see Figure 10-8).

  • Page 393: Access Time Calculations

    Figure 10-9. 8-bit Boot ROM Timing 10.2.2 Access Time Calculations The two time paths that are critical in an MC68340 application using the CS signals are shown in Figure 10-10. The first path is the time from address valid to when data must be available to the processor;...

  • Page 394: Calculating Frequency-adjusted Output

    3 to 30 ns after the rising edge of S0. This specification does not change even if the device frequency is less than 16.78 MHz. MOTOROLA MC68340 USER’S MANUAL 10-7 For More Information On This Product,...

  • Page 395: Signal Width Specifications

    ' = 100 + 3(40 – 30) + (40 – 30) = 140 ns The third type of specification used is a skew between two outputs (see Figure 10-13). 10-8 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product,...

  • Page 396: Skew Between Two Outputs

    = 30 ns maximum therefore: t s ' = 15 + 0(62.5 – 30) + (62.5 – 30) = 47.5 ns minimum In this manner, new specifications for lower frequencies can be derived for an MC68340. MOTOROLA MC68340 USER’S MANUAL...

  • Page 397: Interfacing An 8-bit Device To 16-bit Memory Using Single-address Dma Mode

    One of the requirements of single-address mode is that the source and destination must be the same port size. However, the MC68340 can perform direct memory accesses in single-address mode between an 8-bit device and 16-bit memory. The port size must be specified as 8 bits, and some external logic is required as shown in Figure 10-14.

  • Page 398: Mc68340 Power Reduction At 5v

    Typical values 32KHz xtal 16.78 MHz 24 C INITIALIZATION SERIAL +TIMER 1 +TIMER 2 +DMA +LPSTOP CURRENT Figure 10-15. MC68340 Current vs. Activity at 5 V MOTOROLA MC68340 USER’S MANUAL 10-11 For More Information On This Product, Go to: www.freescale.com...

  • Page 399: Mc68340 Current Vs. Voltage/temperature

    Figure 10-16. MC68340 Current vs. Voltage/Temperature Typical values 32KHz xtal peak current 24 C Clock Frequency (MHz) Figure 10-17. MC68340 Current vs. Clock Frequency at 5 V 10-12 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 400: Mc68340v (3.3 V)

    The MC68340V can operate with a 3.3-V power supply for significant power savings. The formula for power dissipation is f + dc Table 10-2 shows typical electrical characteristics for both the MC68340 and MC68340V. Table 10-2. Typical Electrical Characteristics Parameter MC68340 (5.0 V)

  • Page 401: Thermal Characteristics

    ELECTRICAL CHARACTERISTICS This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of the MC68340. Refer to Section 12 Ordering Information and Mechanical Data for specific part numbers corresponding to voltage, frequency, and temperature ratings.

  • Page 402: Power Considerations

    The measurement of the AC specifications is defined by the waveforms shown in Figure 11-1. To test the parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in the figure. Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown.

  • Page 403

    0.3 V supply. Separate part numbers are used to distinguish the operation of the parts according to the supply voltage. Refer to Section 12 Ordering Information and Mechanical Data for the part numbering schemes. MC68340 is used throughout this section to refer to the 16.78- or 25.16-MHz parts at 5.0 V 5%.

  • Page 404: Drive Levels And Test Points For Ac Specifications

    E. Signal valid to signal valid specification (maximum or minimum). F. Signal valid to signal invalid specification (maximum or minimum). Figure 11-1. Drive Levels and Test Points for AC Specifications 11-4 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 405: Dc Electrical Specifications

    (a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V 0.3 V are preliminary and apply only to the appropriate MC68340V low voltage part. (b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V 5% operation. (c) The 25.16 MHz @ 5.0 V 5% electrical specifications are preliminary.

  • Page 406: Ac Electrical Specifications Control Timing

    (a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V 0.3 V are preliminary and apply only to the appropriate MC68340V low voltage part. (b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V 5% operation. (c) The 25.16 MHz @ 5.0 V 5% electrical specifications are preliminary.

  • Page 407

    MC68340. Clock skew is measured from the rising edges of the clock signals. 12. For external clock mode w/PLL, there is a 5 ns skew between the input clock signal and the output CLKOUT signal from the MC68340. Clock skew is measured from the rising edges of the clock signals. MOTOROLA MC68340 USER’S MANUAL...

  • Page 408: Ac Timing Specifications

    DS , CS Negated to Data-In Invalid (Data-In t SNDI — — — Hold) 29A 4 DS , CS Negated to Data-In High Impedance t SHDI — — — 11-8 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 409

    DSCLK Hold Time t DSCH — — — DSO Delay Time t DSOD — t cyc — t cyc — t cyc + 50 + 25 + 16 MOTOROLA MC68340 USER’S MANUAL 11-9 For More Information On This Product, Go to: www.freescale.com...

  • Page 410

    (a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V 0.3 V are preliminary and apply only to the appropriate MC68340V low voltage part. (b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V 5% operation. (c) The 25.16 MHz @ 5.0 V 5% electrical specifications are preliminary.

  • Page 411: Read Cycle Timing Diagram

    DSACK1 D15–D0 BERR HALT IFETCH ASYNCHRONOUS INPUTS BKPT NOTE: All timing is shown with respect to 0.8V and 2.0V levels. Figure 11-2. Read Cycle Timing Diagram MOTOROLA MC68340 USER’S MANUAL 11-11 For More Information On This Product, Go to: www.freescale.com...

  • Page 412: Write Cycle Timing Diagram

    FC3–FC0 SIZ1–SIZ0 DSACK0 DSACK1 D15–D0 BERR HALT BKPT NOTE: All timing is shown with respect to 0.8-V and 2.0-V levels. Figure 11-3. Write Cycle Timing Diagram 11-12 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 413: Fast Termination Read Cycle Timing Diagram

    Freescale Semiconductor, Inc. CLKOUT A31–A0 FC3–FC0 SIZ1–SIZ0 D15–D0 BKPT Figure 11-4. Fast Termination Read Cycle Timing Diagram MOTOROLA MC68340 USER’S MANUAL 11-13 For More Information On This Product, Go to: www.freescale.com...

  • Page 414: Fast Termination Write Cycle Timing Diagram

    Freescale Semiconductor, Inc. CLKOUT A31–A0 FC3–FC0 SIZ1–SIZ0 D15-D0 BKPT Figure 11-5. Fast Termination Write Cycle Timing Diagram 11-14 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 415: Bus Arbitation Timing—active Bus Case

    Freescale Semiconductor, Inc. CLKOUT A31–A0 D15–D0 DSACK0 DSACK1 BGACK Figure 11-6. Bus Arbitation Timing—Active Bus Case MOTOROLA MC68340 USER’S MANUAL 11-15 For More Information On This Product, Go to: www.freescale.com...

  • Page 416: Bus Arbitration Timing—idle Bus Case

    A31–A0 D15–D0 BGACK Figure 11-7. Bus Arbitration Timing—Idle Bus Case CLKOUT A31–A0 D15–D0 BKPT SHOW CYCLE START OF EXTERNAL CYCLE Figure 11-8. Show Cycle Timing Diagram 11-16 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 417: Iack Cycle Timing Diagram

    IACKx DSACK0 DSACK1 D15-D0 Up to two wait states may be inserted by the processor between states S0 and S1. Figure 11-9. IACK Cycle Timing Diagram MOTOROLA MC68340 USER’S MANUAL 11-17 For More Information On This Product, Go to: www.freescale.com...

  • Page 418: Background Debug Mode Serial Port Timing

    Freescale Semiconductor, Inc. CLKOUT FREEZE BKPT/DSCLK IFETCH/DSI IPIPE/DSO Figure 11-10. Background Debug Mode Serial Port Timing CLKOUT FREEZE IFETCH/DSI Figure 11-11. Background Debug Mode FREEZE Timing 11-18 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 419: Dma Module Ac Electrical Specifications

    (a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V 0.3 V are preliminary and apply only to the appropriate MC68340V low voltage part. (b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V 5% operation. (c) The 25.16 MHz @ 5.0 V 5% electrical specifications are preliminary.

  • Page 420: Timer Module Electrical Specifications

    (a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V 0.3 V are preliminary and apply only to the appropriate MC68340V low voltage part. (b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V 5% operation. (c) The 25.16 MHz @ 5.0 V 5% electrical specifications are preliminary.

  • Page 421: Timer Module Signal Timing Diagram

    Freescale Semiconductor, Inc. CLKOUT TGATE TOUT Figure 11-14. Timer Module Signal Timing Diagram MOTOROLA MC68340 USER’S MANUAL 11-21 For More Information On This Product, Go to: www.freescale.com...

  • Page 422: Serial Module Electrical Specifications

    (a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V 0.3 V are preliminary and apply only to the appropriate MC68340V low voltage part. (b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V 5% operation. (c) The 25.16 MHz @ 5.0 V 5% electrical specifications are preliminary.

  • Page 423

    Figure 11-16. Serial Module Asynchronous Mode Timing (X1) SCLK (16x) Figure 11-17. Serial Module Asynchronous Mode Timing (SCLK–16X) SCLK (1x) Figure 11-18. Serial Module Synchronous Mode Timing Diagram MOTOROLA MC68340 USER’S MANUAL 11-23 For More Information On This Product, Go to: www.freescale.com...

  • Page 424: Ieee 1149.1 Electrical Specifications

    (a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V 0.3 V are preliminary, and apply only to the appropriate MC68340V low voltage part. (b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V 5% operation. (c) The 25.16 MHz @ 5.0 V 5% electrical specifications are preliminary.

  • Page 425

    OUTPUT DATA VALID OUTPUTS Figure 11-20. Boundary Scan Timing Diagram TCLK INPUT DATA VALID OUTPUT DATA VALID OUTPUT DATA VALID Figure 11-21. Test Access Port Timing Diagram MOTOROLA MC68340 USER’S MANUAL 11-25 For More Information On This Product, Go to: www.freescale.com...

  • Page 426: Standard Mc68340 Ordering Information

    Freescale Semiconductor, Inc. SECTION 12 ORDERING INFORMATION AND MECHANICAL DATA This section contains ordering information, pin assignments and package dimensions of the MC68340. 12.1 STANDARD MC68340 ORDERING INFORMATION Supply Voltage Package Type Frequency (MHz) Temperature Order Number 5.0 V Ceramic Quad Flat Pack 0 –...

  • Page 427: Lead Ceramic Quad Flat Pack (fe Suffix)

    CTSB V CC RTSB IPIPE TxDB IFETCH RxDB BKPT RxRDYA FREEZE TxRDYA TIN1 CTSA TOUT1 RTSA TGATE1 V CC TxDA RxDA TIN2 V CC TOUT2 TGATE2 12-2 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 428

    Freescale Semiconductor, Inc. The V CC and GND pins are separated into groups to help electrically isolate the output drivers for different functions of the MC68340. These groups are shown in the following table for the FE suffix package. Pin Group — FE Suffix...

  • Page 429: Lead Plastic Pin Grid Array (rp Suffix)

    DACK1 IRQ7 V CC TOUT2 TxDA RTSA TxRDYA RTSB DONE1 DONE2 V CC RxDA CTSA RxRDYA RxDB CTSB SCLK DREQ1 DREQ2 DACK2 IRQ6 IRQ5 IRQ3 TIN2 12-4 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 430

    Freescale Semiconductor, Inc. The V CC and GND pins are separated into groups to help electrically isolate the different output drivers of the MC68340. These groups are shown in the following table for the RP suffix package. Pin Group — RP Suffix...

  • Page 431: Package Dimensions

    6. DIM S AND V TO BE DETERMINED AT SEATING PLANE 7. DIM A AND B TO BE DETERMINED AT DATUM PLANE - 0.325 BS 0.0128 BS 12-6 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 432: Rp Suffix

    0.115 0.135 1.02 1.52 0.040 0.060 0.43 0.55 0.017 0.022 4.32 4.95 0.170 0.195 35.56 BASIC 1.400 BASIC ..MOTOROLA MC68340 USER’S MANUAL 12-7 For More Information On This Product, Go to: www.freescale.com...

  • Page 433

    Timing, without DSACK , 3-35 Battery Operation, 10-10 Timing, Late Bus Error, 3-36 Baud Rate Resulting in Double Bus Faults, 3-39 Clock, 7-2, 7-26–7-27 Generator, 7-3, 7-8 MOTOROLA MC68330 USER’S MANUAL Index-1 For More Information On This Product, Go to: www.freescale.com...

  • Page 434

    Command Transfer Capabilities, 3-5, 3-8–3-15 Format, 5-73–5-74 DBA Bit, 7-33, 7-35 Register, 7-10–7-11, 7-23, 7-27, 7-46–7-47 DBB Bit, 7-33, 7-34 Sequence Diagram, 5-74–5-75 DBcc Instruction, 5-3 Index-2 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 435

    ECO Bit, 6-7, 6-27–6-28, 6-37 DFC Bits, 6-32 Effects of Wait States on Instruction Timing, 5-92 Differences between MC68020 Instruction Set and Electrical Characteristics, 11-1 MC68340 Instruction Set, 5-5 AC Electrical Specifications DIV Instructions, Definitions, 11-2, 11-4 Control Timing, 11-6–11-7 Acknowledge Signals, 2-10, 6-4–6-7, 6-10, 6-12,...

  • Page 436

    Instruction Encoding, 9-10 IRQ Bit, 6-20, 6-31, 8-23 Control Bits, 9-4 ISM Bits, 6-25, 6-36 Restrictions, 9-11 IVR Bits, 7-22, 8-20, 8-27 IFETCH Signal, 5-64, 5-68–5-69, 5-87–5-88 Index-4 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 437

    PM Bits, 7-23, 7-47 MOVEP Faults, 5-55–5-56 PO Bits, 8-25 Multidrop Mode, 7-15–7-16, 7-23 Port A Timing, 7-16 Data Direction Register, 4-34 Multiprocessor Systems, 5-61 Data Register, 4-34 MOTOROLA MC68340 USER’S MANUAL Index-5 For More Information On This Product, Go to: www.freescale.com...

  • Page 438

    RW Bit, 5-54 Retry Operation, 3-36 RxDx Signal, 7-6, 7-11, 7-14, 7-24 Interruption, 3-36, 3-43 RxRDA Bit, 7-11, 7-13, 7-15, 7-24, 7-25 Operation, 3-4 RxRDYA Bit, 7-34–7-35 Index-6 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 439

    Slave Station, 7-15 5-12, 5-29–5-36 SLIMP Bit, 4-11, 4-29 TAP Controller, 9-2–9-3 SLOCK, 4-11, 4-29 TC Bits, 8-7, 8-24 Software TCK Signal, 2-13, 9-2, 9-11, 9-12 Breakpoints, 5-53–5-54 MOTOROLA MC68340 USER’S MANUAL Index-7 For More Information On This Product, Go to: www.freescale.com...

  • Page 440

    TxRDY Bit, 7-10, 7-25, 7-28, 7-31 XTAL Pin, 2-9, 4-9–4-11, 10-1–10-2 TxRDYA Bit, 7-34–7-35 XTAL_RDY Bit, 7-4, 7-26, 7-33–7-34, 7-46 TxRDYA Signal, 7-7, 7-36 TxRDYB Bit, 7-33, 7-35 Index-8 MC68340 USER’S MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...

  • Page 441

    Freescale Semiconductor, Inc. — Y — Y Bits, 4-12–4-13, 4-28, 4-36 — Z — Zero Mode, 8-23 MOTOROLA MC68340 USER’S MANUAL Index-9 For More Information On This Product, Go to: www.freescale.com...

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