Motorola PowerQUICC II MPC8280 Series Reference Manual page 1005

Table 30-6. FCRx Field Descriptions (continued)
Bits Name
5 TC2 Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
6 DTB Indicates on what bus the data is located.
0 On the 60x bus.
1 On the local.
7 BDB Indicates on what bus the BDs are located.
0 On the 60x bus.
1 On the local bus.
30.8 Interrupts from the FCCs
Interrupt handling for each of the FCC channels is configured on a global (per channel)
basis in the interrupt pending register (SIPNR_L) and interrupt mask register (SIMR_L).
One bit in each register is used to either mask, enable, or report an interrupt in an FCC
channel. The interrupt priority between the FCCs is programmable in the CPM interrupt
priority register (SCPRR_H). The interrupt vector register (SIVEC) indicates which
pending channel has highest priority. Registers within the FCCs manage interrupt handling
for FCC-specific events.
Events that can cause the FCC to interrupt the processor vary slightly among protocols and
are described with each protocol. These events are handled independently for each channel
by the FCC event and mask registers (FCCE and FCCM).
30.8.1 FCC Event Registers (FCCEx)
Each FCC has an FCC event register (FCCE) used to report events. On recognition of an
event, the FCC sets its corresponding FCCE bit regardless of the corresponding mask bit.
To the user it appears as a memory-mapped register that can be read at any time. Bits are
cleared by writing ones; writing zeros has no effect on bit values. FCCE is cleared at reset.
Fields of this register are protocol-dependent and are described in the respective protocol
sections.
30.8.2 FCC Mask Registers (FCCMx)
Each FCC has a read/write FCC mask register (FCCM) used to enable or disable CP
interrupts to the core for events reported in an event register (FCCE). Bit positions in
FCCM are identical to those in FCCE. Note that an interrupt is generated only if the FCC
interrupts are also enabled in the SIU; see Section 4.3.1.5, "SIU Interrupt Mask Registers
(SIMR_H and SIMR_L)."
If an FCCM bit is zero, the CP does not proceed with its usual interrupt handling whenever
that event occurs. Any time a bit in the FCCM register is set, a 1 in the corresponding bit
MOTOROLA Chapter 30. Fast Communications Controllers (FCCs)
Freescale Semiconductor, Inc.
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Interrupts from the FCCs
Description
30-15