Motorola PowerQUICC II MPC8280 Series Reference Manual page 468

Register Descriptions
0
Field
Reset
R/W
Addr
16
Field
Reset
R/W
Addr
1
Undefined at reset.
Table 11-11 describes MDR fields.
Bits Name
0–31 MD Memory data. The data to be read or written into the RAM array when a
supplied to the UPM.
11.3.7 Memory Address Register (MAR)
The memory address register (MAR) is shown in Figure 11-13.
0
Field
Reset
R/W
Addr
16
Field
Reset
R/W
Addr
1
Undefined at reset.
Figure 11-13. Memory Address Register (MAR)
11-30
Freescale Semiconductor, Inc.
xxxx_xxxx_xxxx_xxxx
xxxx_xxxx_xxxx_xxxx
Figure 11-12. Memory Data Register (MDR)
Table 11-11. MDR Field Descriptions
xxxx_xxxx_xxxx_xxxx
xxxx_xxxx_xxxx_xxxx
MPC8280 PowerQUICC II Family Reference Manual
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MD
1
R/W
0x10188
MD
1
R/W
0x1018A
Description
A
1
R/W
0x10168
A
1
R/W
0x10116A
15
31
or command is
WRITE READ
15
31
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