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4 Configuration Registers
4.1
Overview
The configuration of CC11x1-Q1 is done by programming 8-bit registers. The optimum configuration data
based on selected system parameters are most easily found by using the SmartRF Studio software.
Complete descriptions of the registers are given in the following tables. After chip reset, all the registers
have default values as shown in the tables. The optimum register setting might differ from the default
value. After a reset, all registers that should be different from the default value, therefore, need to be
programmed through the SPI interface.
There are 13 command strobe registers, listed in
of an internal state or mode. There are 47 normal 8-bit configuration registers, listed in
these registers are for test purposes only and need not be written for normal operation of CC11x1-Q1.
There are also 12 status registers, listed in
information about the status of CC11x1-Q1.
The two FIFOs are accessed through one 8-bit register. Write operations write to the TX FIFO, while read
operations read from the RX FIFO.
During the header byte transfer and while writing data to a register or the TX FIFO, a status byte is
returned on the SO line. This status byte is described in
Table 4-7
summarizes the SPI address space. The address to use is given by adding the base address to
the left and the burst and read/write bits on the top. Note that the burst bit has different meaning for base
addresses above and below 0x2F.
ADDRESS
STROBE NAME
0x30
SRES
0x31
SFSTXON
0x32
SXOFF
0x33
SCAL
0x34
SRX
0x35
STX
0x36
SIDLE
0x38
SWOR
0x39
SPWD
0x3A
SFRX
0x3B
SFTX
0x3C
SWORRST
0x3D
SNOP
Copyright © 2009–2010, Texas Instruments Incorporated
Table
Table
Table 4-1. Command Strobes
Reset chip.
Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL = 1). If in RX (with CCA), go
to a wait state where only the synthesizer is running (for quick RX/TX turnaround).
Turn off crystal oscillator.
Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without
setting manual calibration mode (MCSM0.FS_AUTOCAL = 0).
Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL = 1.
In IDLE state, enable TX. Perform calibration first if MCSM0.FS_AUTOCAL = 1.
If in RX state and CCA is enabled, only go to TX if channel is clear.
Exit RX/TX, turn off frequency synthesizer, and exit WOR mode, if applicable.
Start automatic RX polling sequence (WOR) as described in
= 0.
Enter power-down mode when CS goes high.
Flush the RX FIFO buffer. Only issue SFRX in IDLE or RXFIFO_OVERFLOW states.
Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states.
Reset real-time clock to Event1 value.
No operation. May be used to access the chip status byte.
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SWRS076B – 11-07-22-013 - APRIL 2009 – REVISED APRIL 2010
4-1. Accessing these registers initiates the change
4-3. These registers, which are read-only, contain
Table
3-3.
DESCRIPTION
Section 3.15.5
CC11x1-Q1
Table
4-2. Many of
if WORCTRL.RC_PD
Configuration Registers
63
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