Download Print this page

Texas Instruments TM4C1294NCPDT Datasheet

page of 1890

/ 1890
Contents
Table of Contents
Bookmarks

Table of Contents

Advertisement

Quick Links

Download this manual

TE X AS I NS TRUM E NT S -P RO DUC TI O N D ATA

Tiva TM4C1294NCPDT Microcontroller

D ATA S H E E T

D S- TM 4C1294NCPDT- 1 5 8 6 3. 2 7 43

Cop yri gh t © 2 007-2014

S P MS 433B

Texas In stru men ts In corporated

Table of Contents

Advertisement

Chapters

Table of Contents

Need help?

Need help?

Do you have a question about the TM4C1294NCPDT and is the answer not in the manual?

Questions and answers

Summary of Contents for Texas Instruments TM4C1294NCPDT

Page 1 TE X AS I NS TRUM E NT S -P RO DUC TI O N D ATA Tiva TM4C1294NCPDT Microcontroller D ATA S H E E T D S- TM 4C1294NCPDT- 1 5 8 6 3. 2 7 43 Cop yri gh t © 2 007-2014...
Page 2 Cortex is a trademark of ARM Limited. All other trademarks are the property of others. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Page 3: Table Of Contents
Analog .......................... 76 1.3.9 JTAG and ARM Serial Wire Debug ................78 1.3.10 Packaging and Temperature ..................78 TM4C1294NCPDT Microcontroller Hardware Details ............78 Kits ..........................79 Support Information ....................... 79 The Cortex-M4F Processor ................... 80 Block Diagram ......................81 Overview ........................
Page 4 Instruction Register (IR) ....................216 4.5.2 Data Registers ......................217 System Control ..................... 220 Signal Description ....................... 220 Functional Description ....................220 5.2.1 Device Identification ....................220 5.2.2 Reset Control ......................221 5.2.3 Non-Maskable Interrupt ....................228 June 18, 2014 Texas Instruments-Production Data...
Page 5 Tiva TM4C1294NCPDT Microcontroller 5.2.4 Power Control ......................229 5.2.5 Clock Control ......................230 5.2.6 System Control ......................239 Initialization and Configuration ..................246 Register Map ......................247 System Control Register Descriptions (System Control Offset) ........254 Processor Support and Exception Module ............523 Functional Description ....................
Page 6 11.3.3 DMA Operation ......................820 11.4 Initialization and Configuration ..................821 11.4.1 EPI Interface Options ....................822 11.4.2 SDRAM Mode ......................822 11.4.3 Host Bus Mode ......................826 11.4.4 General-Purpose Mode ....................847 11.5 Register Map ......................854 June 18, 2014 Texas Instruments-Production Data...
Page 7 Tiva TM4C1294NCPDT Microcontroller 11.6 Register Descriptions ....................856 Cyclical Redundancy Check (CRC) ..............946 12.1 Functional Description ....................946 12.1.1 CRC Support ......................946 12.2 Initialization and Configuration ..................948 12.2.1 CRC Initialization and Configuration ................948 12.3 Register Map ......................949 12.4...
Page 8 C Bus Functional Overview ..................1278 18.3.2 Available Speed Modes ..................... 1284 18.3.3 Interrupts ........................1286 18.3.4 Loopback Operation ....................1287 18.3.5 FIFO and µDMA Operation ..................1287 18.3.6 Command Sequence Flow Charts ................1289 June 18, 2014 Texas Instruments-Production Data...
Page 9 Tiva TM4C1294NCPDT Microcontroller 18.4 Initialization and Configuration ..................1297 18.4.1 Configure the I C Module to Transmit a Single Byte as a Master ........1297 18.4.2 Configure the I C Master to High Speed Mode ............1298 18.5 Register Map ......................1299 18.6...
Page 10 Signal Tables ...................... 1772 26.1 Signals by Pin Number ....................1773 26.2 Signals by Signal Name ..................... 1785 26.3 Signals by Function, Except for GPIO ................. 1797 26.4 GPIO Pins and Alternate Functions ................1808 June 18, 2014 Texas Instruments-Production Data...
Page 11 Tiva TM4C1294NCPDT Microcontroller 26.5 Possible Pin Assignments for Alternate Functions ............1811 26.6 Connections for Unused Signals ................. 1816 Electrical Characteristics .................. 1818 27.1 Maximum Ratings ...................... 1818 27.2 Operating Characteristics ................... 1819 27.3 Recommended Operating Conditions ................. 1820 27.3.1 DC Operating Conditions ................... 1820 27.3.2 Recommended GPIO Operating Characteristics ............
Page 12 Table of Contents List of Figures Figure 1-1. Tiva TM4C1294NCPDT Microcontroller High-Level Block Diagram ....... 54 Figure 2-1. CPU Block Diagram ..................... 82 Figure 2-2. TPIU Block Diagram .................... 83 Figure 2-3. Cortex-M4F Register Set ..................86 Figure 2-4. Bit-Band Mapping ....................111 Figure 2-5.
Page 13 Tiva TM4C1294NCPDT Microcontroller Figure 10-4. GPIODATA Read Example ................. 749 Figure 11-1. EPI Block Diagram ..................... 817 Figure 11-2. SDRAM Non-Blocking Read Cycle ..............824 Figure 11-3. SDRAM Normal Read Cycle ................825 Figure 11-4. SDRAM Write Cycle ................... 826 Figure 11-5.
Page 14 TX DMA OSF Mode Operation Using Descriptors ..........1428 Figure 20-7. RX DMA Operation Flow .................. 1431 Figure 20-8. Networked Time Synchronization ..............1441 Figure 20-9. System Time Update Using Fine Correction Method .......... 1443 June 18, 2014 Texas Instruments-Production Data...
Page 15 Tiva TM4C1294NCPDT Microcontroller Figure 20-10. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path Correction ....................... 1446 Figure 20-11. Wake-Up Frame Filter Register Bank ..............1454 Figure 20-12. Integrated PHY Diagram .................. 1458 Figure 20-13. Interface to Ethernet Jack ................. 1464 Figure 21-1.
Page 16 Figure 27-39. Auto-Negotiation Fast Link Pulse Timing ............1874 Figure 27-40. 100Base-TX Signal Detect Timing ..............1874 Figure 27-41. ULPI Interface Timing Diagram ................. 1876 Figure A-1. Key to Part Numbers ..................1885 Figure A-2. TM4C1294NCPDT 128-Pin TQFP Package Diagram ......... 1887 June 18, 2014 Texas Instruments-Production Data...
Page 17 Table 1. Revision History ....................45 Table 2. Documentation Conventions ................49 Table 1-1. TM4C1294NCPDT Microcontroller Features ............52 Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ........ 85 Table 2-2. Processor Register Map ..................86 Table 2-3.
Page 18 GPIO Drive Strength Options ................753 Table 10-4. GPIO Pad Configuration Examples ..............754 Table 10-5. GPIO Interrupt Configuration Example ..............755 Table 10-6. GPIO Pins With Special Considerations .............. 756 Table 10-7. GPIO Register Map ................... 757 June 18, 2014 Texas Instruments-Production Data...
Page 19 Tiva TM4C1294NCPDT Microcontroller Table 10-8. GPIO Pins With Special Considerations .............. 770 Table 10-9. GPIO Pins With Special Considerations .............. 776 Table 10-10. GPIO Pins With Special Considerations .............. 778 Table 10-11. GPIO Pins With Special Considerations .............. 781 Table 10-12. GPIO Pins With Special Considerations .............. 787 Table 10-13.
Page 20 Analog Comparator Voltage Reference Characteristics, V = 3.3V, EN= 1, and RNG = 0 ......................1657 Table 22-4. Analog Comparator Voltage Reference Characteristics, V = 3.3V, EN= 1, and RNG = 1 ......................1658 June 18, 2014 Texas Instruments-Production Data...
Page 21 Tiva TM4C1294NCPDT Microcontroller Table 22-5. Analog Comparators Register Map ..............1659 Table 23-1. PWM Signals (128TQFP) ................. 1672 Table 23-2. PWM Register Map ..................1679 Table 24-1. QEI Signals (128TQFP) ................... 1750 Table 24-2. QEI Register Map .................... 1754 Table 26-1.
Page 22 Table 27-61. Analog Comparator Voltage Reference Characteristics, V = 3.3V, EN= 1, and RNG = 1 ......................1878 Table 27-62. PWM Timing Characteristics ................1879 Table 27-63. Current Consumption ..................1880 Table 27-64. Peripheral Current Consumption ............... 1884 June 18, 2014 Texas Instruments-Production Data...
Page 23 Tiva TM4C1294NCPDT Microcontroller List of Registers The Cortex-M4F Processor ......................80 Register 1: Cortex General-Purpose Register 0 (R0) ................88 Register 2: Cortex General-Purpose Register 1 (R1) ................88 Register 3: Cortex General-Purpose Register 2 (R2) ................88 Register 4: Cortex General-Purpose Register 3 (R3) ................
Page 24 Hard Fault Status (HFAULTSTAT), offset 0xD2C .............. 190 Register 67: Memory Management Fault Address (MMADDR), offset 0xD34 ........191 Register 68: Bus Fault Address (FAULTADDR), offset 0xD38 .............. 192 Register 69: MPU Type (MPUTYPE), offset 0xD90 ................193 June 18, 2014 Texas Instruments-Production Data...
Page 25 Tiva TM4C1294NCPDT Microcontroller Register 70: MPU Control (MPUCTRL), offset 0xD94 ................194 Register 71: MPU Region Number (MPUNUMBER), offset 0xD98 ............196 Register 72: MPU Region Base Address (MPUBASE), offset 0xD9C ........... 197 Register 73: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ........197 Register 74: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ........
Page 26 Register 77: Universal Serial Bus Software Reset (SRUSB), offset 0x528 ..........369 Register 78: Ethernet PHY Software Reset (SREPHY), offset 0x530 ............ 370 Register 79: Controller Area Network Software Reset (SRCAN), offset 0x534 ........371 June 18, 2014 Texas Instruments-Production Data...
Page 27 Tiva TM4C1294NCPDT Microcontroller Register 80: Analog-to-Digital Converter Software Reset (SRADC), offset 0x538 ........372 Register 81: Analog Comparator Software Reset (SRACMP), offset 0x53C .......... 373 Register 82: Pulse Width Modulator Software Reset (SRPWM), offset 0x540 ........374 Register 83: Quadrature Encoder Interface Software Reset (SRQEI), offset 0x544 ....... 375 Register 84: EEPROM Software Reset (SREEPROM), offset 0x558 ............
Page 28 Register 150: Universal Asynchronous Receiver/Transmitter Power Control (PCUART), offset 0x918 ..467 Register 151: Synchronous Serial Interface Power Control (PCSSI), offset 0x91C ........470 Register 152: Inter-Integrated Circuit Power Control (PCI2C), offset 0x920 ..........472 June 18, 2014 Texas Instruments-Production Data...
Page 29 Tiva TM4C1294NCPDT Microcontroller Register 153: Universal Serial Bus Power Control (PCUSB), offset 0x928 ..........476 Register 154: Ethernet PHY Power Control (PCEPHY), offset 0x930 ............. 478 Register 155: Controller Area Network Power Control (PCCAN), offset 0x934 ........480 Register 156: Analog-to-Digital Converter Power Control (PCADC), offset 0x938 ........482 Register 157: Analog Comparator Power Control (PCACMP), offset 0x93C ..........
Page 30 EEPROM Current Offset (EEOFFSET), offset 0x008 ............653 Register 20: EEPROM Read-Write (EERDWR), offset 0x010 .............. 654 Register 21: EEPROM Read-Write with Increment (EERDWRINC), offset 0x014 ........655 Register 22: EEPROM Done Status (EEDONE), offset 0x018 .............. 656 June 18, 2014 Texas Instruments-Production Data...
Page 31 Tiva TM4C1294NCPDT Microcontroller Register 23: EEPROM Support Control and Status (EESUPP), offset 0x01C ........658 Register 24: EEPROM Unlock (EEUNLOCK), offset 0x020 ..............659 Register 25: EEPROM Protection (EEPROT), offset 0x030 ..............660 Register 26: EEPROM Password (EEPASS0), offset 0x034 ..............662 Register 27: EEPROM Password (EEPASS1), offset 0x038 ..............
Page 32 GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ............765 Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ........... 767 Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ..............769 Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ..........770 June 18, 2014 Texas Instruments-Production Data...
Page 33 Tiva TM4C1294NCPDT Microcontroller Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ............772 Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ............773 Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ............774 Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ............775 Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ..............
Page 34 GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ............. 996 Register 8: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ..........999 Register 9: GPTM Interrupt Clear (GPTMICR), offset 0x024 ............1002 Register 10: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ..........1004 June 18, 2014 Texas Instruments-Production Data...
Page 35 Tiva TM4C1294NCPDT Microcontroller Register 11: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ..........1005 Register 12: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 ..........1006 Register 13: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ..........1007 Register 14: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ............. 1008 Register 15: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C .............
Page 36 ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ........1153 Register 52: ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ........1153 Register 53: ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ........1153 June 18, 2014 Texas Instruments-Production Data...
Page 37 Tiva TM4C1294NCPDT Microcontroller Register 54: ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ........1153 Register 55: ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ........1153 Register 56: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ........1156 Register 57: ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ........
Page 38 C Slave ACK Control (I2CSACKCTL), offset 0x820 ............1347 Register 23: C FIFO Data (I2CFIFODATA), offset 0xF00 ..............1348 Register 24: C FIFO Control (I2CFIFOCTL), offset 0xF04 ............... 1350 Register 25: C FIFO Status (I2CFIFOSTATUS), offset 0xF08 ............1352 June 18, 2014 Texas Instruments-Production Data...
Page 39 Tiva TM4C1294NCPDT Microcontroller Register 26: C Peripheral Properties (I2CPP), offset 0xFC0 ............1354 Register 27: C Peripheral Configuration (I2CPC), offset 0xFC4 ............1355 Controller Area Network (CAN) Module ................... 1356 Register 1: CAN Control (CANCTL), offset 0x000 ................1378 Register 2: CAN Status (CANSTS), offset 0x004 ................
Page 40 Register 47: Ethernet MAC System Time-Higher Word Seconds (EMACHWORDSEC), offset 0x724 ..1546 Register 48: Ethernet MAC Timestamp Status (EMACTIMSTAT), offset 0x728 ........1547 Register 49: Ethernet MAC PPS Control (EMACPPSCTRL), offset 0x72C .......... 1548 June 18, 2014 Texas Instruments-Production Data...
Page 41 Tiva TM4C1294NCPDT Microcontroller Register 50: Ethernet MAC PPS0 Interval (EMACPPS0INTVL), offset 0x760 ........1551 Register 51: Ethernet MAC PPS0 Width (EMACPPS0WIDTH), offset 0x764 ........1552 Register 52: Ethernet MAC DMA Bus Mode (EMACDMABUSMOD), offset 0xC00 ......1553 Register 53: Ethernet MAC Transmit Poll Demand (EMACTXPOLLD), offset 0xC04 ......1557 Register 54: Ethernet MAC Receive Poll Demand (EMACRXPOLLD), offset 0xC08 ......
Page 42 PWM3 Interrupt Status and Clear (PWM3ISC), offset 0x10C .......... 1718 Register 28: PWM0 Load (PWM0LOAD), offset 0x050 ..............1720 Register 29: PWM1 Load (PWM1LOAD), offset 0x090 ..............1720 Register 30: PWM2 Load (PWM2LOAD), offset 0x0D0 ..............1720 June 18, 2014 Texas Instruments-Production Data...
Page 43 Tiva TM4C1294NCPDT Microcontroller Register 31: PWM3 Load (PWM3LOAD), offset 0x110 ..............1720 Register 32: PWM0 Counter (PWM0COUNT), offset 0x054 ............... 1721 Register 33: PWM1 Counter (PWM1COUNT), offset 0x094 ............... 1721 Register 34: PWM2 Counter (PWM2COUNT), offset 0x0D4 .............. 1721 Register 35: PWM3 Counter (PWM3COUNT), offset 0x114 ...............
Page 44 QEI Velocity (QEISPEED), offset 0x01C ................ 1764 Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............. 1765 Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............1767 Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ........... 1769 June 18, 2014 Texas Instruments-Production Data...
Page 45: Revision History
Tiva TM4C1294NCPDT Microcontroller Revision History The revision history table notes changes made between the indicated revisions of the TM4C1294NCPDT data sheet. Table 1. Revision History Date Revision Description June 2014 15863.2743 ■ In ADC chapter, clarified section "Sample and Hold Window Control".
Page 46: Texas Instruments-Production Data
LDO Sleep Power Control (LDOSPCTL) register • LMINERR bit from Sleep/Deep-Sleep Power Mode Status (SDPMST) register – Added LDOSME, TSPDE, PIOSCPDE, SRAMSM, SRAMLPM, FLASHLPM, and LDOSEQ bits in SYSPROP register. ■ In Internal Memory chapter: June 18, 2014 Texas Instruments-Production Data...
Page 47: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Table 1. Revision History (continued) Date Revision Description – Added subsections to "Flash Memory" section about Execute-Only Protection, Read-Only Protection and Permanently Disabling Debug. – Removed INVPL bit from EEPROM Done Status (EEDONE) register. – Updated table "MEMTIM0 Register Configuration vs. Frequency" with lower wait states, and improved performance values.
Page 48: About This Document
About This Document About This Document This data sheet provides reference information for the TM4C1294NCPDT microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M4F core. Audience This manual is intended for system software developers, hardware designers, and application developers.
Page 49: Documentation Conventions
Tiva TM4C1294NCPDT Microcontroller Documentation Conventions This document uses the conventions shown in Table 2 on page 49. Table 2. Documentation Conventions Notation Meaning General Register Notation REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register.
Page 50: Texas Instruments-Production Data
All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. June 18, 2014 Texas Instruments-Production Data...
Page 51: Architectural Overview
■ “Tiva™ C Series Overview” on page 51 ■ “TM4C1294NCPDT Microcontroller Overview” on page 52 ■ “TM4C1294NCPDT Microcontroller Features” on page 55 ■ “TM4C1294NCPDT Microcontroller Hardware Details” on page 78 ■ “Kits” on page 79 ■ “Support Information” on page 79 Tiva™...
Page 52: Tm4C1294Ncpdt Microcontroller Overview
Tiva™ C Series, providing flexibility to fit precise needs. Texas Instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network.
Page 53: Texas Instruments-Production Data
Industrial (-40°C to 85°C) temperature range Extended (-40°C to 105°C) temperature range Figure 1-1 on page 54 shows the features on the TM4C1294NCPDT microcontroller. Note that there are two on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB) bus is the legacy bus.
Page 54: Figure 1-1. Tiva Tm4C1294Ncpdt Microcontroller High-Level Block Diagram
Architectural Overview Figure 1-1. Tiva TM4C1294NCPDT Microcontroller High-Level Block Diagram JTAG/SWD ARM® Boot Loader Cortex™-M4F DriverLib (120MHz) AES & CRC Ethernet Boot Loader System Control and Flash DCode bus Clocks (1024KB) (w/ Precis. Osc.) NVIC ICode bus System Bus TM4C1294NCPDT SRAM Bus Matrix...
Page 55: Tm4C1294Ncpdt Microcontroller Features
1.3.1 ARM Cortex-M4F Processor Core All members of the Tiva™ C Series, including the TM4C1294NCPDT microcontroller, are designed around an ARM Cortex-M processor core. The ARM Cortex-M processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.
Page 56: Texas Instruments-Production Data
1.3.1.3 Nested Vectored Interrupt Controller (NVIC) (see page 136) The TM4C1294NCPDT controller includes the ARM Nested Vectored Interrupt Controller (NVIC). The NVIC and Cortex-M4F prioritize and handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine (ISR).
Page 57: On-Chip Memory
■ 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers ■ Decoupled three stage pipeline 1.3.2 On-Chip Memory The TM4C1294NCPDT microcontroller is integrated with the following set of on-chip memory and features: ■ 256 KB single-cycle SRAM ■ 1024 KB Flash memory ■...
Page 58: Texas Instruments-Production Data
The Texas Instruments encryption package is available with full source code, and is based on Lesser General Public License (LGPL) source. An LGPL means that the code can be used within an application without any copyleft implications for the application (the code does not automatically become open source).
Page 59: External Peripheral Interface
Tiva TM4C1294NCPDT Microcontroller 1.3.2.4 EEPROM (see page 615) The TM4C1294NCPDT microcontroller includes an EEPROM with the following features: ■ 6Kbytes of memory accessible as 1536 32-bit words ■ 96 blocks of 16 words (64 bytes) each ■ Built-in wear leveling ■...
Page 60: Texas Instruments-Production Data
– Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable input ■ General parallel GPIO – 1 to 32 bits, FIFOed with speed control – Useful for custom peripherals or for digital data acquisition and actuator controls June 18, 2014 Texas Instruments-Production Data...
Page 61: Cyclical Redundancy Check (Crc)
Tiva TM4C1294NCPDT Microcontroller 1.3.4 Cyclical Redundancy Check (CRC) (see page 946) The TM4C1294NCPDT microcontroller includes a CRC computation module for uses such as message transfer and safety system checks. The CRC has the following features: ■ Support four major CRC forms: –...
Page 62: Texas Instruments-Production Data
– Dual-buffer (ring) or linked-list (chained) descriptors – Round-robin or fixed priority arbitration between TX/RX – Descriptors support up to 8 kB transfer blocks size – Programmable interrupts for flexible system implementation ■ Physical media manipulation – MDI/MDI-X cross-over support June 18, 2014 Texas Instruments-Production Data...
Page 63: Texas Instruments-Production Data
Universal Serial Bus (USB) is a serial bus standard designed to allow peripherals to be connected and disconnected using a standardized interface without rebooting the system. The TM4C1294NCPDT microcontroller has one USB controller that supports high and full speed multi-point communications and complies with the USB 2.0 standard for high-speed function. The USB controller can have three configurations: USB Device, USB Host, and USB On-The-Go (negotiated on-the-go as host or device when connected to other USB-enabled systems).
Page 64: Texas Instruments-Production Data
(parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The TM4C1294NCPDT microcontroller includes eight fully programmable 16C550-type UARTs. Although the functionality is similar to a 16C550 UART, this UART design is not register compatible.
Page 65: Texas Instruments-Production Data
Both the I C master and slave can generate interrupts. The TM4C1294NCPDT microcontroller includes I C modules with the following features: ■ Devices on the I C bus can be designated as either a master or a slave –...
Page 66: Texas Instruments-Production Data
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Ability to execute single data transfers or burst data transfers using the RX and TX FIFOs in the I June 18, 2014 Texas Instruments-Production Data...
Page 67: System Integration
QSSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. The TM4C1294NCPDT microcontroller includes four QSSI modules with the following features: ■ Four QSSI channels with Advanced, Bi- and Quad-SSI functionality ■...
Page 68: Texas Instruments-Production Data
1.3.6.1 Direct Memory Access (see page 678) The TM4C1294NCPDT microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex-M4F processor, allowing for more efficient use of the processor and the available bus bandwidth.
Page 69: Texas Instruments-Production Data
A PLL is provided for the generation of system clock frequencies in excess of the reference clock provided. The reference clocks for the PLL are the PIOSC and the main crystal oscillator. The following clock sources are provided to the TM4C1294NCPDT microcontroller: –...
Page 70: Texas Instruments-Production Data
PWM signal – The System Clock or a global Alternate Clock (ALTCLK) resource can be used as timer clock source. The global ALTCLK can be: • PIOSC • Hibernation Module Real-time clock output (RTCOSC) June 18, 2014 Texas Instruments-Production Data...
Page 71: Texas Instruments-Production Data
CCP pin as an input. Alternatively, the GPTM can generate a simple PWM output on the CCP pin. The TM4C1294NCPDT microcontroller includes twelve 16/32-bit CCP pins that can be programmed to operate in the following modes: ■...
Page 72: Texas Instruments-Production Data
■ Clock source from an internal low frequency oscillator (HIB LFIOSC) or a 32.768-kHz external crystal or oscillator ■ Sixteen 32-bit words of battery-backed memory to save state during hibernation ■ Programmable interrupts for: – RTC match – External wake – Low battery June 18, 2014 Texas Instruments-Production Data...
Page 73: Texas Instruments-Production Data
A watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The TM4C1294NCPDT Watchdog Timer can generate an interrupt, a non-maskable interrupt, or a reset when a time-out value is reached.
Page 74: Advanced Motion Control
1.3.7.1 PWM (see page 1669) The TM4C1294NCPDT microcontroller contains one PWM module, with four PWM generator blocks and a control block, for a total of 8 PWM outputs. Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal.
Page 75: Texas Instruments-Production Data
In addition, a third channel, or index signal, can be used to reset the position counter. The TM4C1294NCPDT quadrature encoder with index (QEI) module interprets the code produced by a quadrature encoder wheel to integrate position...
Page 76: Analog
The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 30 MHz for a 120-MHz system). The TM4C1294NCPDT microcontroller includes one QEI module providing control of one motor with the following features: ■...
Page 77: Texas Instruments-Production Data
An analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. The TM4C1294NCPDT microcontroller provides three independent integrated analog comparators that can be configured to drive an output or generate an interrupt or ADC event.
Page 78: Jtag And Arm Serial Wire Debug
■ 128-pin RoHS-compliant TQFP package ■ Industrial (-40°C to 85°C) ambient temperature range ■ Extended (-40°C to 105°C) ambient temperature range TM4C1294NCPDT Microcontroller Hardware Details Details on the pins and package can be found in the following sections: June 18, 2014...
Page 79: Kits
■ Reference Design Kits accelerate product development by providing ready-to-run hardware and comprehensive documentation including hardware design files ■ Evaluation Kits provide a low-cost and effective means of evaluating TM4C1294NCPDT microcontrollers before purchase ■ Development Kits provide you with all the tools you need to develop and prototype embedded...
Page 80: The Cortex-M4F Processor
■ Migration from the ARM7 processor family for better performance and power efficiency ■ Optimized for single-cycle Flash memory usage up to specific frequencies; see “Internal Memory” on page 600 for more information. ■ Ultra-low power consumption with integrated sleep modes June 18, 2014 Texas Instruments-Production Data...
Page 81: Block Diagram
The Cortex-M4F processor closely integrates a nested interrupt controller (NVIC), to deliver industry-leading interrupt performance. The TM4C1294NCPDT NVIC includes a non-maskable interrupt (NMI) and provides eight interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency.
Page 82: Overview
To enable simple and cost-effective profiling of the system trace events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. June 18, 2014 Texas Instruments-Production Data...
Page 83: Trace Port Interface Unit (Tpiu)
Tiva TM4C1294NCPDT Microcontroller The Embedded Trace Macrocell (ETM) delivers unrivaled instruction trace capture in an area smaller than traditional trace units, enabling full instruction trace. For more details on the ARM ETM, see the ARM® Embedded Trace Macrocell Architecture Specification.
Page 84: Programming Model
In this mode, software can use all the instructions and has access to all resources. In Thread mode, the CONTROL register (see page 99) controls whether software execution is privileged or unprivileged. In Handler mode, software execution is always privileged. June 18, 2014 Texas Instruments-Production Data...
Page 85: Stacks
Tiva TM4C1294NCPDT Microcontroller Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software.
Page 86: Figure 2-3. Cortex-M4F Register Set
Cortex General-Purpose Register 3 Cortex General-Purpose Register 4 Cortex General-Purpose Register 5 Cortex General-Purpose Register 6 Cortex General-Purpose Register 7 Cortex General-Purpose Register 8 Cortex General-Purpose Register 9 Cortex General-Purpose Register 10 Cortex General-Purpose Register 11 June 18, 2014 Texas Instruments-Production Data...
Page 87: Register Descriptions
Tiva TM4C1294NCPDT Microcontroller Table 2-2. Processor Register Map (continued) Offset Name Type Reset Description page Cortex General-Purpose Register 12 Stack Pointer 0xFFFF.FFFF Link Register Program Counter 0x0100.0000 Program Status Register PRIMASK 0x0000.0000 Priority Mask Register FAULTMASK 0x0000.0000 Fault Mask Register BASEPRI 0x0000.0000...
Page 88: Register 1: Cortex General-Purpose Register 0 (R0)
The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode. Cortex General-Purpose Register 0 (R0) Type RW, reset - DATA Type Reset DATA Type Reset Bit/Field Name Type Reset Description 31:0 DATA Register data. June 18, 2014 Texas Instruments-Production Data...
Page 89: Register 14: Stack Pointer (Sp)
Tiva TM4C1294NCPDT Microcontroller Register 14: Stack Pointer (SP) The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear, this register is the Main Stack Pointer (MSP).
Page 90: Register 15: Link Register (Lr)
EXC_RETURN is loaded into the LR on exception entry. See Table 2-10 on page 123 for the values and description. Link Register (LR) Type RW, reset 0xFFFF.FFFF LINK Type Reset LINK Type Reset Bit/Field Name Type Reset Description 31:0 LINK 0xFFFF.FFFF This field is the return address. June 18, 2014 Texas Instruments-Production Data...
Page 91: Register 16: Program Counter (Pc)
Tiva TM4C1294NCPDT Microcontroller Register 16: Program Counter (PC) The Program Counter (PC) is register R15, and it contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1.
Page 92: Table 2-3. Psr Register Combinations
Reads of the EPSR bits return zero, and the processor ignores writes to these bits. Program Status Register (PSR) Type RW, reset 0x0100.0000 ICI / IT THUMB reserved Type Reset ICI / IT reserved ISRNUM Type Reset June 18, 2014 Texas Instruments-Production Data...
Page 93: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description APSR Negative or Less Flag Value Description The previous operation result was negative or less than. The previous operation result was positive, zero, greater than, or equal. The value of this bit is only meaningful when accessing PSR or APSR.
Page 94: Texas Instruments-Production Data
See the description of the SEL instruction in the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information. The value of this field is only meaningful when accessing PSR or APSR. June 18, 2014 Texas Instruments-Production Data...
Page 95: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 15:10 ICI / IT EPSR ICI / IT status These bits, along with bits 26:25, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction.
Page 96: Register 18: Priority Mask Register (Primask)
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PRIMASK Priority Mask Value Description Prevents the activation of all exceptions with configurable priority. No effect. June 18, 2014 Texas Instruments-Production Data...
Page 97: Register 19: Fault Mask Register (Faultmask)
Tiva TM4C1294NCPDT Microcontroller Register 19: Fault Mask Register (FAULTMASK) The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK register.
Page 98: Register 20: Base Priority Mask Register (Basepri)
All exceptions with priority level 7 are masked. reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 99: Register 21: Control Register (Control)
Tiva TM4C1294NCPDT Microcontroller Register 21: Control Register (CONTROL) The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode, and indicates whether the FPU state is active. This register is only accessible in privileged mode.
Page 100: Texas Instruments-Production Data
In Handler mode, this bit reads as zero and ignores writes. The Cortex-M4F updates this bit automatically on exception return. TMPL Thread Mode Privilege Level Value Description Unprivileged software can be executed in Thread mode. Only privileged software can be executed in Thread mode. June 18, 2014 Texas Instruments-Production Data...
Page 101: Register 22: Floating-Point Status Control (Fpsc)
Tiva TM4C1294NCPDT Microcontroller Register 22: Floating-Point Status Control (FPSC) The FPSC register provides all necessary user-level control of the floating-point system. Floating-Point Status Control (FPSC) Type RW, reset - reserved RMODE reserved Type Reset reserved reserved Type Reset Bit/Field Name...
Page 102: Texas Instruments-Production Data
When set, indicates this exception has occurred since 0 was last written to this bit. Invalid Operation Cumulative Exception When set, indicates this exception has occurred since 0 was last written to this bit. June 18, 2014 Texas Instruments-Production Data...
Page 103: Exceptions And Interrupts
The processor has a fixed memory map that provides up to 4 GB of addressable memory. The memory map for the TM4C1294NCPDT controller is provided in Table 2-4 on page 103. In this manual, register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map.
Page 104: Texas Instruments-Production Data
0x4003.3000 0x4003.3FFF 16/32-bit Timer 3 0x4003.4000 0x4003.4FFF 16/32-bit Timer 4 0x4003.5000 0x4003.5FFF 16/32-bit Timer 5 0x4003.6000 0x4003.7FFF Reserved 0x4003.8000 0x4003.8FFF ADC0 1073 0x4003.9000 0x4003.9FFF ADC1 1073 0x4003.A000 0x4003.BFFF Reserved 0x4003.C000 0x4003.CFFF Analog Comparators 1659 June 18, 2014 Texas Instruments-Production Data...
Page 105: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Table 2-4. Memory Map (continued) Start Description For details, see page ... 0x4003.D000 0x4003.DFFF GPIO Port J 0x4003.E000 0x4003.FFFF Reserved 0x4004.0000 0x4004.0FFF CAN0 Controller 1375 0x4004.1000 0x4004.1FFF CAN1 Controller 1375 0x4004.2000 0x4004.FFFF Reserved 0x4005.0000 0x4005.0FFF 1646 0x4005.1000 0x4005.7FFF...
Page 106: Memory Regions, Types And Attributes
■ Normal: The processor can re-order transactions for efficiency and perform speculative reads. ■ Device: The processor preserves transaction order relative to other transactions to Device or Strongly Ordered memory. ■ Strongly Ordered: The processor preserves transaction order relative to all other transactions. June 18, 2014 Texas Instruments-Production Data...
Page 107: Memory System Ordering Of Memory Accesses
Tiva TM4C1294NCPDT Microcontroller The different ordering requirements for Device and Strongly Ordered memory mean that the memory system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory. An additional memory attribute is Execute Never (XN), which means the processor prevents instruction accesses.
Page 108: Software Ordering Of Memory Accesses
■ Self-modifying code If a program contains self-modifying code, use an ISB instruction immediately after the code modification in the program. The ISB instruction ensures subsequent instruction execution uses the updated program. ■ Memory map switching June 18, 2014 Texas Instruments-Production Data...
Page 109: Bit-Banding
Tiva TM4C1294NCPDT Microcontroller If the system contains a memory map switching mechanism, use a DSB instruction after switching the memory map in the program. The DSB instruction ensures subsequent instruction execution uses the updated memory map. ■ Dynamic exception priority change When an exception priority has to change when the exception is pending or active, use DSB instructions after the change.
Page 110: Texas Instruments-Production Data
■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000: 0x2200.0000 = 0x2200.0000 + (0*32) + (0*4) ■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000: 0x2200.001C = 0x2200.0000+ (0*32) + (7*4) June 18, 2014 Texas Instruments-Production Data...
Page 111: Data Storage
Tiva TM4C1294NCPDT Microcontroller Figure 2-4. Bit-Band Mapping 32-MB Alias Region 0x23FF.FFFC 0x23FF.FFF8 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x23FF.FFE4 0x23FF.FFE0 0x2200.001C 0x2200.0018 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 0x2200.0004 0x2200.0000 1-MB SRAM Bit-Band Region 0x200F.FFFF 0x200F.FFFE 0x200F.FFFD 0x200F.FFFC 0x2000.0003 0x2000.0002 0x2000.0001 0x2000.0000 2.4.5.1 Directly Accessing an Alias Region Writing to a word in the alias region updates a single bit in the bit-band region.
Page 112: Synchronization Primitives
1. Use a Load-Exclusive instruction to read the value of the location. 2. Modify the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location. 4. Test the returned status bit. June 18, 2014 Texas Instruments-Production Data...
Page 113: Exception Model
Tiva TM4C1294NCPDT Microcontroller If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no write was performed, which indicates that the value returned at step 1 might be out of date. The software must retry the entire read-modify-write sequence.
Page 114: Exception States
■ Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. This fault can be enabled or disabled. June 18, 2014 Texas Instruments-Production Data...
Page 115: Table 2-8. Exception Types
NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-9 on page 116 lists the interrupts on the TM4C1294NCPDT controller. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler.
Page 116: Table 2-9. Interrupts
0x0000.0078 ADC0 Sequence 0 0x0000.007C ADC0 Sequence 1 0x0000.0080 ADC0 Sequence 2 0x0000.0084 ADC0 Sequence 3 0x0000.0088 Watchdog Timers 0 and 1 0x0000.008C 16/32-Bit Timer 0A 0x0000.0090 16/32-Bit Timer 0B 0x0000.0094 16/32-Bit Timer 1A June 18, 2014 Texas Instruments-Production Data...
Page 117: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Table 2-9. Interrupts (continued) Vector Number Interrupt Number (Bit Vector Address or Description in Interrupt Registers) Offset 0x0000.0098 16/32-Bit Timer 1B 0x0000.009C 16/32-Bit Timer 2A 0x0000.00A0 16/32-Bit Timer 2B 0x0000.00A4 Analog Comparator 0 0x0000.00A8 Analog Comparator 1 0x0000.00AC...
Page 118: Texas Instruments-Production Data
GPIO Port Q6 0x0000.01AC GPIO Port Q7 108-113 92-97 Reserved 0x0000.01C8 16/32-Bit Timer 6A 0x0000.01CC 16/32-Bit Timer 6B 0x0000.01D0 16/32-Bit Timer 7A 0x0000.01D4 16/32-Bit Timer 7B 0x0000.01D8 0x0000.01DC 120-124 104-108 Reserved 0x0000.01F4 0x0000.01F8 127-129 111-113 Reserved June 18, 2014 Texas Instruments-Production Data...
Page 119: Exception Handlers
Tiva TM4C1294NCPDT Microcontroller 2.5.3 Exception Handlers The processor handles exceptions using: ■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs. ■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault exceptions handled by the fault handlers.
Page 120: Exception Priorities
See “Interrupt Priority Grouping” on page 120 for more information about preemption by an interrupt. When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” on page 121 more information. June 18, 2014 Texas Instruments-Production Data...
Page 121: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller ■ Return. Return occurs when the exception handler is completed, and there is no pending exception with sufficient priority to be serviced and the completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred.
Page 122: Figure 2-7. Exception Stack Frame
2.5.7.2 Exception Return Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC: June 18, 2014 Texas Instruments-Production Data...
Page 123: Fault Handling
Tiva TM4C1294NCPDT Microcontroller ■ An LDM or POP instruction that loads the PC ■ A BX instruction using any register ■ An LDR instruction with the PC as the destination EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler.
Page 124: Fault Types
Fault Escalation and Hard Faults All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on page 177). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on page 180). June 18, 2014 Texas Instruments-Production Data...
Page 125: Fault Status Registers And Fault Address Registers
Tiva TM4C1294NCPDT Microcontroller Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler as described in “Exception Model” on page 113.
Page 126: Power Management
2.7.2 Wake Up from Sleep Mode The conditions for the processor to wake up depend on the mechanism that caused it to enter sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 127: Instruction Set Summary
Tiva TM4C1294NCPDT Microcontroller 2.7.2.1 Wake Up from WFI or Sleep-on-Exit Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit.
Page 128: Texas Instruments-Production Data
Move from general register to special spec_reg, Rm N,Z,C,V register Multiply, 32-bit result MUL, MULS {Rd,} Rn, Rm Move NOT MVN, MVNS Rd, Op2 N,Z,C No operation Logical OR NOT ORN, ORNS {Rd,} Rn, Op2 N,Z,C June 18, 2014 Texas Instruments-Production Data...
Page 129: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Table 2-13. Cortex-M4F Instruction Summary (continued) Mnemonic Operands Brief Description Flags Logical OR ORR, ORRS {Rd,} Rn, Op2 N,Z,C Pack halfword PKHTB, PKHBT {Rd,} Rn, Rm, Op2 Pop registers from stack reglist Push registers onto stack PUSH...
Page 130: Texas Instruments-Production Data
Rd, #n, Rm Saturating subtract and add with SSAX {Rd,} Rn, Rm exchange Signed subtract 16 SSUB16 {Rd,} Rn, Rm Signed subtract 8 SSUB8 {Rd,} Rn, Rm Store multiple registers, increment after Rn{!}, reglist June 18, 2014 Texas Instruments-Production Data...
Page 131: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Table 2-13. Cortex-M4F Instruction Summary (continued) Mnemonic Operands Brief Description Flags Store multiple registers, decrement STMDB, STMEA Rn{!}, reglist before Store multiple registers, increment after STMFD, STMIA Rn{!}, reglist Store register word Rt, [Rn {, #offset}] Store register byte...
Page 132: Texas Instruments-Production Data
Sd, Sm integer with rounding Converts half-precision value to VCVT<B|H>.F32.F16 Sd, Sm single-precision Converts single-precision register to VCVTT<B|T>.F32.F16 Sd, Sm half-precision Floating-point Divide VDIV.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Accumulate VFMA.F32 {Sd,} Sn, Sm June 18, 2014 Texas Instruments-Production Data...
Page 133: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Table 2-13. Cortex-M4F Instruction Summary (continued) Mnemonic Operands Brief Description Flags Floating-point Fused Negate Multiply VFNMA.F32 {Sd,} Sn, Sm Accumulate Floating-point Fused Multiply Subtract VFMS.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply VFNMS.F32 {Sd,} Sn, Sm Subtract Load Multiple extension registers VLDM.F<32|64>...
Page 134: Cortex-M4 Peripherals
System Control Block 0xE000.ED00-0xE000.ED3F 0xE000.ED90-0xE000.EDB8 Memory Protection Unit 0xE000.EF30-0xE000.EF44 Floating Point Unit Functional Description This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor peripherals: SysTick, NVIC, SCB, MPU, FPU. June 18, 2014 Texas Instruments-Production Data...
Page 135: System Timer (Systick)
Tiva TM4C1294NCPDT Microcontroller 3.1.1 System Timer (SysTick) Cortex-M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example as: ■...
Page 136: Nested Vectored Interrupt Controller (Nvic)
Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit in the PEND0 register on page 156 or SWTRIG on page 163. A pending interrupt remains pending until one of the following: June 18, 2014 Texas Instruments-Production Data...
Page 137: System Control Block (Scb)
Tiva TM4C1294NCPDT Microcontroller ■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to active. Then: – For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR.
Page 138: Table 3-2. Memory Attributes Summary
Disable a region before writing new region settings to the MPU if you have previously enabled the region being changed. For example: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register June 18, 2014 Texas Instruments-Production Data...
Page 139: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller STR R1, [R0, #0x0] ; Region Number BIC R2, R2, #1 ; Disable STRH R2, [R0, #0x8] ; Region Size and Enable STR R4, [R0, #0x4] ; Region Base Address STRH R3, [R0, #0xA] ; Region Attribute ORR R2, #1 ;...
Page 140: Figure 3-1. Srd Use Example
Refer to the section called “MPU Configuration for a Tiva™ C Series Microcontroller” on page 142 for information on programming the MPU for TM4C1294NCPDT implementations. Table 3-3. TEX, S, C, and B Bit Field Encoding...
Page 141: Table 3-4. Cache Policy For Memory Attribute Encoding
Tiva TM4C1294NCPDT Microcontroller Table 3-3. TEX, S, C, and B Bit Field Encoding (continued) Memory Type Shareability Other Attributes Normal Not shareable Outer and inner Normal Shareable write-through. No write Normal Not shareable allocate. Normal Shareable Normal Not shareable Outer and inner non-cacheable.
Page 142: Floating-Point Unit (Fpu)
ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard. The FPU's single-precision extension registers can also be accessed as 16 doubleword registers for load, store, and move operations. June 18, 2014 Texas Instruments-Production Data...
Page 143: Figure 3-2. Fpu Register Bank
Tiva TM4C1294NCPDT Microcontroller 3.1.5.1 FPU Views of the Register Bank The FPU provides an extension register file containing 32 single-precision registers. These can be viewed as: ■ Sixteen 64-bit doubleword registers, D0-D15 ■ Thirty-two 32-bit single-word registers, S0-S31 ■ A combination of registers from the above views Figure 3-2.
Page 144: Texas Instruments-Production Data
NaN regardless of the fractions of any NaN operands. SNaNs in an arithmetic CDP operation set the IOC flag, FPSCR[0]. NaN handling by data transfer and non-arithmetic CDP instructions is the same as in full-compliance mode. June 18, 2014 Texas Instruments-Production Data...
Page 145: Table 3-7. Qnan And Snan Handling
Tiva TM4C1294NCPDT Microcontroller Table 3-7. QNaN and SNaN Handling Instruction Type Default NaN With QNaN Operand With SNaN Operand Mode The QNaN or one of the QNaN operands, set. The SNaN is quieted and the if there is more than one, is returned...
Page 146: Register Map
DIS3 0x0000.0000 Interrupt 96-113 Clear Enable 0x200 PEND0 0x0000.0000 Interrupt 0-31 Set Pending 0x204 PEND1 0x0000.0000 Interrupt 32-63 Set Pending 0x208 PEND2 0x0000.0000 Interrupt 64-95 Set Pending 0x20C PEND3 0x0000.0000 Interrupt 96-113 Set Pending June 18, 2014 Texas Instruments-Production Data...
Page 147: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Table 3-8. Peripherals Register Map (continued) Offset Name Type Reset Description page 0x280 UNPEND0 0x0000.0000 Interrupt 0-31 Clear Pending 0x284 UNPEND1 0x0000.0000 Interrupt 32-63 Clear Pending 0x288 UNPEND2 0x0000.0000 Interrupt 64-95 Clear Pending 0x28C UNPEND3 0x0000.0000 Interrupt 96-113 Clear Pending...
Page 148: Texas Instruments-Production Data
MPU Region Base Address Alias 1 0xDA8 MPUATTR1 0x0000.0000 MPU Region Attribute and Size Alias 1 0xDAC MPUBASE2 0x0000.0000 MPU Region Base Address Alias 2 0xDB0 MPUATTR2 0x0000.0000 MPU Region Attribute and Size Alias 2 June 18, 2014 Texas Instruments-Production Data...
Page 149: System Timer (Systick) Register Descriptions
Tiva TM4C1294NCPDT Microcontroller Table 3-8. Peripherals Register Map (continued) Offset Name Type Reset Description page 0xDB4 MPUBASE3 0x0000.0000 MPU Region Base Address Alias 3 0xDB8 MPUATTR3 0x0000.0000 MPU Region Attribute and Size Alias 3 Floating-Point Unit (FPU) Registers 0xD88 CPAC 0x0000.0000...
Page 150: Register 1: Systick Control And Status Register (Stctrl), Offset 0X010
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CLK_SRC Clock Source Value Description Precision internal oscillator (PIOSC) divided by 4 System clock June 18, 2014 Texas Instruments-Production Data...
Page 151: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description INTEN Interrupt Enable Value Description Interrupt generation is disabled. Software can use the COUNT bit to determine if the counter has ever reached 0. An interrupt is generated to the NVIC when SysTick counts to 0.
Page 152: Register 2: Systick Reload Value Register (Streload), Offset 0X014
23:0 RELOAD 0x00.0000 Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. June 18, 2014 Texas Instruments-Production Data...
Page 153: Nvic Register Descriptions
Tiva TM4C1294NCPDT Microcontroller Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 Note: This register can only be accessed from privileged mode. The STCURRENT register contains the current value of the SysTick counter. SysTick Current Value Register (STCURRENT) Base 0xE000.E000...
Page 154: Register 4: Interrupt 0-31 Set Enable (En0), Offset 0X100
On a write, no effect. On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DISn register. June 18, 2014 Texas Instruments-Production Data...
Page 155: Register 8: Interrupt 0-31 Clear Enable (Dis0), Offset 0X180
Tiva TM4C1294NCPDT Microcontroller Register 8: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 Register 9: Interrupt 32-63 Clear Enable (DIS1), offset 0x184 Register 10: Interrupt 64-95 Clear Enable (DIS2), offset 0x188 Register 11: Interrupt 96-113 Clear Enable (DIS3), offset 0x18C Note: This register can only be accessed from privileged mode.
Page 156: Register 12: Interrupt 0-31 Set Pending (Pend0), Offset 0X200
If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND0 register. June 18, 2014 Texas Instruments-Production Data...
Page 157: Register 16: Interrupt 0-31 Clear Pending (Unpend0), Offset 0X280
Tiva TM4C1294NCPDT Microcontroller Register 16: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 Register 17: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 Register 18: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 Register 19: Interrupt 96-113 Clear Pending (UNPEND3), offset 0x28C Note: This register can only be accessed from privileged mode.
Page 158: Register 20: Interrupt 0-31 Active Bit (Active0), Offset 0X300
Type RO, reset 0x0000.0000 Type Reset Type Reset Bit/Field Name Type Reset Description 31:0 0x0000.0000 Interrupt Active Value Description The corresponding interrupt is not active. The corresponding interrupt is active, or active and pending. June 18, 2014 Texas Instruments-Production Data...
Page 159: Register 24: Interrupt 0-3 Priority (Pri0), Offset 0X400
Tiva TM4C1294NCPDT Microcontroller Register 24: Interrupt 0-3 Priority (PRI0), offset 0x400 Register 25: Interrupt 4-7 Priority (PRI1), offset 0x404 Register 26: Interrupt 8-11 Priority (PRI2), offset 0x408 Register 27: Interrupt 12-15 Priority (PRI3), offset 0x40C Register 28: Interrupt 16-19 Priority (PRI4), offset 0x410...
Page 160: Texas Instruments-Production Data
PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 161: Register 40: Interrupt 64-67 Priority (Pri16), Offset 0X440
Tiva TM4C1294NCPDT Microcontroller Register 40: Interrupt 64-67 Priority (PRI16), offset 0x440 Register 41: Interrupt 68-71 Priority (PRI17), offset 0x444 Register 42: Interrupt 72-75 Priority (PRI18), offset 0x448 Register 43: Interrupt 76-79 Priority (PRI19), offset 0x44C Register 44: Interrupt 80-83 Priority (PRI20), offset 0x450...
Page 162: Texas Instruments-Production Data
PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 163: System Control Block (Scb) Register Descriptions
Tiva TM4C1294NCPDT Microcontroller Register 53: Software Trigger Interrupt (SWTRIG), offset 0xF00 Note: Only privileged software can enable unprivileged access to the SWTRIG register. Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI). See Table 2-9 on page 116 for interrupt assignments.
Page 164: Register 54: Auxiliary Control (Actlr), Offset 0X008
IT block while it is still executing the IT instruction. This behavior is called IT folding, and improves performance, However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit before executing the task, to disable IT folding. June 18, 2014 Texas Instruments-Production Data...
Page 165: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description DISWBUF Disable Write Buffer Value Description No effect. Disables write buffer use during default memory map accesses. In this situation, all bus faults are precise bus faults but performance is decreased because any store to memory must complete before the processor can execute the next instruction.
Page 166: Register 55: Cpu Id Base (Cpuid), Offset 0Xd00
Description Always reads as 0xF. 15:4 PARTNO 0xC24 Part Number Value Description 0xC24 Cortex-M4 processor. Revision Number Value Description The pn value in the rnpn product revision identifier, for example, the 1 in r0p1. June 18, 2014 Texas Instruments-Production Data...
Page 167: Register 56: Interrupt Control And State (Intctrl), Offset 0Xd04
Tiva TM4C1294NCPDT Microcontroller Register 56: Interrupt Control and State (INTCTRL), offset 0xD04 Note: This register can only be accessed from privileged mode. The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate...
Page 168: Texas Instruments-Production Data
This bit provides status for all interrupts excluding NMI and Faults. 21:20 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 169: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 19:12 VECPEND 0x00 Interrupt Pending Vector Number This field contains the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register.
Page 170: Register 57: Vector Table Offset (Vtable), Offset 0Xd08
1024-byte boundary. reserved 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 171: Table 3-9. Interrupt Priority Levels
Tiva TM4C1294NCPDT Microcontroller Register 58: Application Interrupt and Reset Control (APINT), offset 0xD0C Note: This register can only be accessed from privileged mode. The APINT register provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, 0x05FA must be written to the VECTKEY field, otherwise the write is ignored.
Page 172: Texas Instruments-Production Data
0, otherwise behavior is unpredictable. VECTRESET System Reset This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. June 18, 2014 Texas Instruments-Production Data...
Page 173: Register 59: System Control (Sysctrl), Offset 0Xd10
Tiva TM4C1294NCPDT Microcontroller Register 59: System Control (SYSCTRL), offset 0xD10 Note: This register can only be accessed from privileged mode. The SYSCTRL register controls features of entry to and exit from low-power state. System Control (SYSCTRL) Base 0xE000.E000 Offset 0xD10 Type RW, reset 0x0000.0000...
Page 174: Texas Instruments-Production Data
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 175: Register 60: Configuration And Control (Cfgctrl), Offset 0Xd14
Tiva TM4C1294NCPDT Microcontroller Register 60: Configuration and Control (CFGCTRL), offset 0xD14 Note: This register can only be accessed from privileged mode. The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero and unaligned accesses;...
Page 176: Texas Instruments-Production Data
The processor can enter Thread mode only when no exception is active. The processor can enter Thread mode from any level under the control of an EXC_RETURN value (see “Exception Return” on page 122 for more information). June 18, 2014 Texas Instruments-Production Data...
Page 177: Register 61: System Handler Priority 1 (Syspri1), Offset 0Xd18
Tiva TM4C1294NCPDT Microcontroller Register 61: System Handler Priority 1 (SYSPRI1), offset 0xD18 Note: This register can only be accessed from privileged mode. The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory management fault exception handlers.
Page 178: Register 62: System Handler Priority 2 (Syspri2), Offset 0Xd1C
0-7, with lower values having higher priority. 28:0 reserved 0x000.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 179: Register 63: System Handler Priority 3 (Syspri3), Offset 0Xd20
Tiva TM4C1294NCPDT Microcontroller Register 63: System Handler Priority 3 (SYSPRI3), offset 0xD20 Note: This register can only be accessed from privileged mode. The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV handlers. This register is byte-accessible.
Page 180: Register 64: System Handler Control And State (Syshndctrl), Offset 0Xd24
USAGE Usage Fault Enable Value Description Disables the usage fault exception. Enables the usage fault exception. Bus Fault Enable Value Description Disables the bus fault exception. Enables the bus fault exception. June 18, 2014 Texas Instruments-Production Data...
Page 181: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description Memory Management Fault Enable Value Description Disables the memory management fault exception. Enables the memory management fault exception. SVC Call Pending Value Description An SVC call exception is not pending. An SVC call exception is pending.
Page 182: Texas Instruments-Production Data
Description Bus fault is not active. Bus fault is active. This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit. June 18, 2014 Texas Instruments-Production Data...
Page 183: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description MEMA Memory Management Fault Active Value Description Memory management fault is not active. Memory management fault is active. This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit.
Page 184: Register 65: Configurable Fault Status (Faultstat), Offset 0Xd28
Description 31:26 reserved 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 185: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description DIV0 RW1C Divide-by-Zero Usage Fault Value Description No divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled. The processor has executed an SDIV or UDIV instruction with a divisor of 0.
Page 186: Texas Instruments-Production Data
Bus Fault on Floating-Point Lazy State Preservation Value Description No bus fault has occurred during floating-point lazy state preservation. A bus fault has occurred during floating-point lazy state preservation. This bit is cleared by writing a 1 to it. June 18, 2014 Texas Instruments-Production Data...
Page 187: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description BSTKE RW1C Stack Bus Fault Value Description No bus fault has occurred on stacking for exception entry. Stacking for an exception entry has caused one or more bus faults. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect.
Page 188: Texas Instruments-Production Data
When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it. June 18, 2014 Texas Instruments-Production Data...
Page 189: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description MUSTKE RW1C Unstack Access Violation Value Description No memory management fault has occurred on unstacking for a return from exception. Unstacking for a return from exception has caused one or more access violations.
Page 190: Register 66: Hard Fault Status (Hfaultstat), Offset 0Xd2C
This bit is cleared by writing a 1 to it. reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 191: Register 67: Memory Management Fault Address (Mmaddr), Offset 0Xd34
Tiva TM4C1294NCPDT Microcontroller Register 67: Memory Management Fault Address (MMADDR), offset 0xD34 Note: This register can only be accessed from privileged mode. The MMADDR register contains the address of the location that generated a memory management fault. When an unaligned access faults, the address in the MMADDR register is the actual address that faulted.
Page 192: Memory Protection Unit (Mpu) Register Descriptions
Memory Protection Unit (MPU) Register Descriptions This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by address offset. The MPU registers can only be accessed from privileged mode. June 18, 2014 Texas Instruments-Production Data...
Page 193: Register 69: Mpu Type (Mputype), Offset 0Xd90
Tiva TM4C1294NCPDT Microcontroller Register 69: MPU Type (MPUTYPE), offset 0xD90 Note: This register can only be accessed from privileged mode. The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it supports. MPU Type (MPUTYPE) Base 0xE000.E000...
Page 194: Register 70: Mpu Control (Mpuctrl), Offset 0Xd94
Description 31:3 reserved 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 195: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description PRIVDEFEN MPU Default Region This bit enables privileged software access to the default memory map. Value Description If the MPU is enabled, this bit disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault.
Page 196: Register 71: Mpu Region Number (Mpunumber), Offset 0Xd98
NUMBER MPU Region to Access This field indicates the MPU region referenced by the MPUBASE and MPUATTR registers. The MPU supports eight memory regions. June 18, 2014 Texas Instruments-Production Data...
Page 197: Register 72: Mpu Region Base Address (Mpubase), Offset 0Xd9C
Tiva TM4C1294NCPDT Microcontroller Register 72: MPU Region Base Address (MPUBASE), offset 0xD9C Register 73: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 Register 74: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC Register 75: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 Note: This register can only be accessed from privileged mode.
Page 198: Texas Instruments-Production Data
REGION Region Number On a write, contains the value to be written to the MPUNUMBER register. On a read, returns the current region number in the MPUNUMBER register. June 18, 2014 Texas Instruments-Production Data...
Page 199: Register 76: Mpu Region Attribute And Size (Mpuattr), Offset 0Xda0
Tiva TM4C1294NCPDT Microcontroller Register 76: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 Register 77: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 Register 78: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 Register 79: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 Note: This register can only be accessed from privileged mode.
Page 200: Texas Instruments-Production Data
SIZE Region Size Mask The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. Refer to Table 3-10 on page 199 for more information. June 18, 2014 Texas Instruments-Production Data...
Page 201: Floating-Point Unit (Fpu) Register Descriptions
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description ENABLE Region Enable Value Description The region is disabled. The region is enabled. Floating-Point Unit (FPU) Register Descriptions This section lists and describes the Floating-Point Unit (FPU) registers, in numerical order by address offset.
Page 202: Register 80: Coprocessor Access Control (Cpac), Offset 0Xd88
Full Access 19:0 reserved 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 203: Register 81: Floating-Point Context Control (Fpcc), Offset 0Xf34
Tiva TM4C1294NCPDT Microcontroller Register 81: Floating-Point Context Control (FPCC), offset 0xF34 The FPCC register sets or returns FPU control data. Floating-Point Context Control (FPCC) Base 0xE000.E000 Offset 0xF34 Type RW, reset 0xC000.0000 ASPEN LSPEN reserved Type Reset reserved MONRDY reserved...
Page 204: Texas Instruments-Production Data
When set, privilege level was user when the floating-point stack frame was allocated. LSPACT Lazy State Preservation Active When set, Lazy State preservation is active. Floating-point stack frame has been allocated but saving state to it has been deferred. June 18, 2014 Texas Instruments-Production Data...
Page 205: Register 82: Floating-Point Context Address (Fpca), Offset 0Xf38
Tiva TM4C1294NCPDT Microcontroller Register 82: Floating-Point Context Address (FPCA), offset 0xF38 The FPCA register holds the location of the unpopulated floating-point register space allocated on an exception stack frame. Floating-Point Context Address (FPCA) Base 0xE000.E000 Offset 0xF38 Type RW, reset -...
Page 206: Register 83: Floating-Point Default Status Control (Fpdsc), Offset 0Xf3C
Round towards Zero (RZ) mode 21:0 reserved 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 207: Jtag Interface
TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The TM4C1294NCPDT JTAG controller works with the ARM JTAG controller built into the Cortex-M4F core by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while JTAG instructions select the TDO output.
Page 208: Block Diagram
SWCLK PC1 (1) JTAG TMS and SWDIO. SWDIO PC3 (1) JTAG TDO and SWO. PC0 (1) JTAG/SWD CLK. PC2 (1) JTAG TDI. PC3 (1) JTAG TDO and SWO. PC1 (1) JTAG TMS and SWDIO. June 18, 2014 Texas Instruments-Production Data...
Page 209: Functional Description
Tiva TM4C1294NCPDT Microcontroller Functional Description A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 208. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs.
Page 210: Table 4-2. Jtag Port Pins State After Power-On Reset Or Rst Assertion
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost (see page 776). June 18, 2014 Texas Instruments-Production Data...
Page 211: Jtag Tap Controller
Tiva TM4C1294NCPDT Microcontroller 4.3.1.4 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed.
Page 212: Shift Registers
Port C GPIO Digital Enable (GPIODEN) register), enabling the pull-up resistors (PUE[3:0] set in the Port C GPIO Pull-Up Select (GPIOPUR) register), disabling the pull-down resistors (PDE[3:0] cleared in the Port C GPIO Pull-Down Select (GPIOPDR) register) and enabling the June 18, 2014 Texas Instruments-Production Data...
Page 213: Texas Instruments-Production Data
In the case that the software routine is not implemented and the device is locked out of the part, this issue can be solved by using the TM4C1294NCPDT Flash Programmer "Unlock" feature. Please refer to...
Page 214: Texas Instruments-Production Data
The 16-bit TMS/SWDIO command for switching to SWD mode is defined as b1110.0111.1001.1110, transmitted LSB first. This command can also be represented as 0xE79E when transmitted LSB first. The June 18, 2014 Texas Instruments-Production Data...
Page 215: Initialization And Configuration
Tiva TM4C1294NCPDT Microcontroller complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD are in their reset states.
Page 216: Instruction Register (Ir)
This preloaded data can be used with the EXTEST instruction to drive data into or out of the controller. See “Boundary Scan Data Register” on page 218 for more information. June 18, 2014 Texas Instruments-Production Data...
Page 217: Data Registers
Tiva TM4C1294NCPDT Microcontroller 4.5.1.3 ABORT Instruction The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request.
Page 218: Figure 4-3. Idcode Register Format
Figure 4-5. Boundary Scan Register Format GPIO GPIO (m+1) GPIO GPIO n 4.5.2.4 APACC Data Register The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. June 18, 2014 Texas Instruments-Production Data...
Page 219: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller 4.5.2.5 DPACC Data Register The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 4.5.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification.
Page 220: System Control
The Device Identification 0 (DID0) (page 255) and Device Identification 1 (DID1) (page 257) registers provide details about the device's version, package, temperature range, and so on. The Peripheral Present registers starting at system control offset 0x300, such as the Watchdog June 18, 2014 Texas Instruments-Production Data...
Page 221: Reset Control
This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 5.2.2.1 Reset Sources The TM4C1294NCPDT microcontroller has the following reset sources: 1. Power-on reset (POR) (see page 222). 2. External reset input pin (RST) assertion (see page 223). 3. A brown-out detection of V...
Page 222: Texas Instruments-Production Data
This is useful in in-circuit testing and other situations where it is desirable to delay the operation of the device until an external supervisor has released. The Power-On Reset sequence is as follows: 1. The microcontroller waits for internal POR to go inactive. June 18, 2014 Texas Instruments-Production Data...
Page 223: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller 2. The internal reset is released and the core executes a full initialization of the device. Upon completion, the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution.
Page 224: Figure 5-1. Basic Rst Configuration
(analog) power supply drops below its corresponding brown-out threshold voltage. If a brown-out condition is detected, the system may generate an interrupt, a system reset or a Power-On Reset. The default value at reset is to generate an interrupt. June 18, 2014 Texas Instruments-Production Data...
Page 225: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller The application can identify the type of BOR event that occurred by reading the Power-Temperature Cause (PWRTC) register. The BOR detection circuits can be programmed to generate a reset, System Control interrupt, or NMI in the Power-Temp Brown Out Control (PTBOCTL) register.
Page 226: Texas Instruments-Production Data
5.2.2.7 Watchdog Timer Reset The Watchdog Timer module's function is to prevent system hangs. The TM4C1294NCPDT microcontroller has two Watchdog Timer modules in case one watchdog clock source fails. One watchdog is run off the system clock and the other is run off the Precision Internal Oscillator (PIOSC).
Page 227: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller generation has been enabled through the RESEN bit in the Watchdog Control Register (WDTCTL), the watchdog timer asserts its reset signal to the microcontroller. The reset generated can be a full Power-On Reset or a system reset depending on the value programmed in WDOGn bit field of the Reset Behavior Control Register (RESBEHAVCTL).
Page 228: Non-Maskable Interrupt
5.2.3.2 Main Oscillator Verification Failure The TM4C1294NCPDT microcontroller provides a main oscillator verification circuit that generates an error condition if the oscillator is running too fast or too slow. If the main oscillator verification circuit is enabled and a failure occurs, either a power-on reset is generated and control is transferred to the NMI handler, or an interrupt is generated.
Page 229: Power Control
5.2.4 Power Control The TM4C1294NCPDT microcontroller provides an integrated LDO regulator that is used to provide power to the majority of the microcontroller's internal logic. Figure 5-4 shows the power architecture. The voltage output has a maximum voltage of 1.2 V. Refer to “Dynamic Power Management”...
Page 230: Clock Control
Deep-Sleep or Hibernate mode power savings. Note that the HIB LFIOSC is a different clock source than the LFIOSC. Refer to the Electrical Characteristic Chapter for more information on frequency range. June 18, 2014 Texas Instruments-Production Data...
Page 231: Table 5-3. Clock Source Options
Tiva TM4C1294NCPDT Microcontroller The internal system clock (SysClk), is derived from any of the above sources. An internal PLL can also be used by the PIOSC or MOSC clock to generate the system clock and peripheral clocks. Table 5-3 on page 231 shows how the various clock sources can be used in a system.
Page 232: Texas Instruments-Production Data
System Control Note: The clock sources in Figure 5-5 include a superset of peripherals available in the family. Some peripheral clock sources may not be present on your specific device. June 18, 2014 Texas Instruments-Production Data...
Page 233: Figure 5-5. Main Clock Tree
Tiva TM4C1294NCPDT Microcontroller Figure 5-5. Main Clock Tree GPIO (PM4) mosc PHY Clock ÷N CLKDIV PTP REF_CLK MII/RMII CLK OSC0 mosc SYSCLK MOSC OSC1 CLKDIV NOXTAL ADCCLK ÷N mosc piosc ADCCLK DIVSCLK mosc piosc DIVSCLK ÷N RTCCLK ULPIEN &!CSD USB0CLK...
Page 234: Texas Instruments-Production Data
■ A gated system clock acts as the clock source to the Control and Status registers (CSR) of the Ethernet MAC. The SysClk frequency for Run, Sleep and Deep Sleep mode is programmed in the System Control module. June 18, 2014 Texas Instruments-Production Data...
Page 235: Table 5-5. System Clock Frequency
Tiva TM4C1294NCPDT Microcontroller ■ The PHY receives the main oscillator (MOSC) which must be 25 MHz ± 50 ppm for proper operation. The MOSC source can be a single-ended source or a crystal. PWM Clock Control The PWMCC register can be used to select the System Clock as the PWM clock source or a divided System Clock.
Page 236: Texas Instruments-Production Data
4. Reset is deasserted and the processor is directed to the NMI handler during the reset sequence. 5.2.5.5 The PLL has two modes of operation: Normal and Power-Down ■ Normal: The PLL oscillates based on the values in the PLLFREQ0 and PLLFREQ1 registers and drives the output. June 18, 2014 Texas Instruments-Production Data...
Page 237: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the PLLPWR bit in the PLLFREQ0 register (see page 292). PLL Configuration The PLL is disabled by default during power-on reset and is enabled later by software if required.
Page 238: Table 5-7. Actual Pll Frequency
All changes to the PLL must be performed using a different clock source until the PLL has locked frequency. Thus, changing the PLL VCO frequency must be done as a sequence from PLL to PIOSC/MOSC and then PIOSC/MOSC to new PLL. June 18, 2014 Texas Instruments-Production Data...
Page 239: System Control
Tiva TM4C1294NCPDT Microcontroller Hardware is provided to keep the PLL from being used as a system clock until the T condition READY is met after one of the two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RSCLKCFG register is re-programmed to enable the PLL.
Page 240: Texas Instruments-Production Data
If the PLL is running at the time of the WFI instruction, hardware shuts down the PLL for power savings. June 18, 2014 Texas Instruments-Production Data...
Page 241: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller For further power savings the PIOSC can be disabled through the PIOSCPD bit in the DSCLKCFG register. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration.
Page 242: Figure 5-6. Module Clock Selection
■ LDO Sleep Power Control (LDOSPCTL): Controls the LDO value in Sleep mode ■ LDO Deep-Sleep Power Control (LDODPCTL): Controls the LDO value in Deep-Sleep mode ■ LDO Sleep Power Calibration (LDOSPCAL): Provides factory recommendations for the LDO value in Sleep mode June 18, 2014 Texas Instruments-Production Data...
Page 243: Table 5-8. Peripheral Memory Power Control
Tiva TM4C1294NCPDT Microcontroller ■ LDO Deep-Sleep Power Calibration (LDODPCAL): Provides factory recommendations for the LDO value in Deep-Sleep mode ■ Sleep Power Configuration (SLPPWRCFG): Controls the power saving modes for Flash memory and SRAM in Sleep mode ■ Deep-Sleep Power Configuration (DSLPPWRCFG): Controls the power saving modes for Flash memory and SRAM in Deep-Sleep mode ■...
Page 244: Table 5-9. Maximum System Clock And Piosc Frequency With Respect To Ldo Voltage
DSCLKCFG register. These options are not available for Sleep mode. ■ The LDO voltage can be changed using the LDOSPCTL or LDODPCTL register. ■ The Flash memory can be put into low power mode. June 18, 2014 Texas Instruments-Production Data...
Page 245: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller ■ The SRAM can be put into standby or low power mode. For typical power consumption and sleep/wake-up times, refer to “Current Consumption ” on page 1880 and “Sleep Modes” on page 1843. The SDPMST register provides results on the Dynamic Power Management command issued. It also has some real time status that can be viewed by a debugger or the core if it is running.
Page 246: Initialization And Configuration
(or that a timeout period has passed and lock has failed, in which case an error condition exists and this sequence is abandoned and error processing is initiated). 9. Write the RSCLKCFG register's PSYSDIV value, set the USEPLL bit to enabled, and MEMTIMU bit. June 18, 2014 Texas Instruments-Production Data...
Page 247: Register Map
Tiva TM4C1294NCPDT Microcontroller If it is necessary to keep the MOSC powered on during automatic (deep-sleep) or accidental power down, then the MOSCDPD bit should be set to 0x1. Otherwise, if the MOSCDPD bit is set to 0x0, the MOSC is powered off when deep-sleep is entered or automatic power down occurs. The following...
Page 248: Texas Instruments-Production Data
Hardware System Service Request 0x280 USBPDS 0x0000.003F USB Power Domain Status 0x284 USBMPC 0x0000.0003 USB Memory Power Control 0x288 EMACPDS 0x0000.003F Ethernet MAC Power Domain Status 0x28C EMACMPC 0x0000.0003 Ethernet MAC Memory Power Control June 18, 2014 Texas Instruments-Production Data...
Page 249: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Table 5-11. System Control Register Map (continued) Offset Name Type Reset Description page 0x298 CAN0PDS 0x0000.003F CAN 0 Power Domain Status 0x29C CAN0MPC 0x0000.0003 CAN 0 Memory Power Control 0x2A0 CAN1PDS 0x0000.003F CAN 1 Power Domain Status...
Page 250: Texas Instruments-Production Data
EPI Run Mode Clock Gating Control 0x614 RCGCHIB 0x0000.0001 Hibernation Run Mode Clock Gating Control Universal Asynchronous Receiver/Transmitter Run Mode 0x618 RCGCUART 0x0000.0000 Clock Gating Control Synchronous Serial Interface Run Mode Clock Gating 0x61C RCGCSSI 0x0000.0000 Control June 18, 2014 Texas Instruments-Production Data...
Page 251: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Table 5-11. System Control Register Map (continued) Offset Name Type Reset Description page 0x620 RCGCI2C 0x0000.0000 Inter-Integrated Circuit Run Mode Clock Gating Control 0x628 RCGCUSB 0x0000.0000 Universal Serial Bus Run Mode Clock Gating Control 0x630 RCGCEPHY 0x0000.0000...
Page 252: Texas Instruments-Production Data
DCGCCCM 0x0000.0000 CRC Module Deep-Sleep Mode Clock Gating Control 0x89C DCGCEMAC 0x0000.0000 Ethernet MAC Deep-Sleep Mode Clock Gating Control 0x900 PCWD 0x0000.0003 Watchdog Timer Power Control 0x904 PCTIMER 0x0000.00FF 16/32-Bit General-Purpose Timer Power Control June 18, 2014 Texas Instruments-Production Data...
Page 253: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Table 5-11. System Control Register Map (continued) Offset Name Type Reset Description page 0x908 PCGPIO 0x0000.7FFF General-Purpose Input/Output Power Control 0x90C PCDMA 0x0000.0001 Micro Direct Memory Access Power Control 0x910 PCEPI 0x0000.0001 External Peripheral Interface Power Control...
Page 254: System Control Register Descriptions (System Control Offset)
UNIQUEID1 Unique ID 1 0xF28 UNIQUEID2 Unique ID 2 0xF2C UNIQUEID3 Unique ID 3 System Control Register Descriptions (System Control Offset) All addresses given are relative to the System Control base address of 0x400F.E000. June 18, 2014 Texas Instruments-Production Data...
Page 255: Register 1: Device Identification 0 (Did0), Offset 0X000
Tiva TM4C1294NCPDT Microcontroller Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the microcontroller. Each microcontroller is uniquely identified by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1 register.
Page 256: Texas Instruments-Production Data
The MINOR field value is reset when the MAJOR field is changed. This field is numeric and is encoded as follows: Value Description Initial device, or a major revision update. First metal layer change. Second metal layer change. and so on. June 18, 2014 Texas Instruments-Production Data...
Page 257: Register 2: Device Identification 1 (Did1), Offset 0X004
TM4Cor LM3S. 23:16 PARTNO 0x1F Part Number This field provides the part number of the device within the family. This value indicates the TM4C1294NCPDT microcontroller. June 18, 2014 Texas Instruments-Production Data...
Page 258: Texas Instruments-Production Data
RoHS-compliant. QUAL Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): Value Description Engineering Sample (unqualified) Pilot Production (unqualified) Fully Qualified June 18, 2014 Texas Instruments-Production Data...
Page 259: Register 3: Power-Temp Brown Out Control (Ptboctl), Offset 0X038
Tiva TM4C1294NCPDT Microcontroller Register 3: Power-Temp Brown Out Control (PTBOCTL), offset 0x038 This register determines, based on an individual event level, the appropriate next level of action (for example, NONE, System Control Interrupt, NMI, or reset) when an event occurs.
Page 260: Texas Instruments-Production Data
An event occurs when V trips under the V threshold found in DD_BOR Table 27-13 on page 1826. This field determines the action to take on the event. Value Description No Action System control interrupt Reset June 18, 2014 Texas Instruments-Production Data...
Page 261: Register 4: Raw Interrupt Status (Ris), Offset 0X050
Tiva TM4C1294NCPDT Microcontroller Register 4: Raw Interrupt Status (RIS), offset 0x050 This register indicates the status for system control raw interrupts. An interrupt is sent to the interrupt controller if the corresponding bit in the Interrupt Mask Control (IMC) register is set. Writing a 1 to the corresponding bit in the Masked Interrupt Status and Clear (MISC) register clears an interrupt status bit.
Page 262: Texas Instruments-Production Data
This bit is cleared by writing a 1 to the BORMIS bit in the MISC register. reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 263: Register 5: Interrupt Mask Control (Imc), Offset 0X054
Tiva TM4C1294NCPDT Microcontroller Register 5: Interrupt Mask Control (IMC), offset 0x054 This register contains the mask bits for system control raw interrupts. A raw interrupt, indicated by a bit being set in the Raw Interrupt Status (RIS) register, is sent to the interrupt controller if the corresponding bit in this register is set.
Page 264: Texas Instruments-Production Data
RIS register is set. reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 265: Register 6: Masked Interrupt Status And Clear (Misc), Offset 0X058
Tiva TM4C1294NCPDT Microcontroller Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 On a read, this register gives the current masked status value of the corresponding interrupt in the Raw Interrupt Status (RIS) register. All of the bits are RW1C, thus writing a 1 to a bit clears the corresponding raw interrupt bit in the RIS register (see page 261).
Page 266: Texas Instruments-Production Data
Writing a 1 to this bit clears it and also the BORRIS bit in the RIS register. reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 267: Register 7: Reset Cause (Resc), Offset 0X05C
Tiva TM4C1294NCPDT Microcontroller Register 7: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences. If a full POK-POR is initiated, the POR bit in the RESC register is set and all other bits are cleared.
Page 268: Texas Instruments-Production Data
When read, this bit indicates that Watchdog Timer 0 has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. When read, this bit indicates that Watchdog Timer 0 timed out and generated a reset. June 18, 2014 Texas Instruments-Production Data...
Page 269: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description Brown-Out Reset Note that for this bit, the BOR event that causes the Brown-Out Reset can be any of the following: ■ The V supply drops below its acceptable operating range. ■...
Page 270: Register 8: Power-Temperature Cause (Pwrtc), Offset 0X060
VDD_UBOR RW1C Under BOR Status Value Description has not tripped under voltage BOR comparison. has tripped under voltage BOR comparison. June 18, 2014 Texas Instruments-Production Data...
Page 271: Register 9: Nmi Cause Register (Nmic), Offset 0X064
Tiva TM4C1294NCPDT Microcontroller Register 9: NMI Cause Register (NMIC), offset 0x064 This register provides the detailed information on the cause of an NMI interrupt. These bits are set via hardware when the event occurs AND the higher level control indicates that it should be NMI event.
Page 272: Texas Instruments-Production Data
EXTERNAL External Pin NMI Value Description No NMI pin event has occurred. The NMI pin was asserted by external hardware. June 18, 2014 Texas Instruments-Production Data...
Page 273: Register 10: Main Oscillator Control (Moscctl), Offset 0X07C
Tiva TM4C1294NCPDT Microcontroller Register 10: Main Oscillator Control (MOSCCTL), offset 0x07C This register provides control over the features of the main oscillator, including the ability to enable the MOSC clock verification circuit, what action to take when the MOSC fails, and whether or not a crystal is connected.
Page 274: Texas Instruments-Production Data
Regardless of the action taken, if the MOSC fails, the oscillator source is switched to the PIOSC automatically. CVAL Clock Validation for MOSC Value Description The MOSC monitor circuit is disabled. The MOSC monitor circuit is enabled. June 18, 2014 Texas Instruments-Production Data...
Page 275: Register 11: Run And Sleep Mode Configuration Register (Rsclkcfg), Offset 0X0B0
Tiva TM4C1294NCPDT Microcontroller Register 11: Run and Sleep Mode Configuration Register (RSCLKCFG), offset 0x0B0 Important: When transitioning the system clock configuration to use the MOSC as the fundamental clock source, the PWRDN bit must be set in the MOSCCTL register prior to reselecting the MOSC for proper operation.
Page 276: Texas Instruments-Production Data
The divisor value is the OSYSDIV field value + 1 PSYSDIV PLL System Clock Divisor This field specifies the system clock divisor value for the PLL. This field is used when the USEPLL bit is 1. /(PSYSDIV+ 1) syclk June 18, 2014 Texas Instruments-Production Data...
Page 277: Register 12: Memory Timing Parameter Register 0 For Main Flash And Eeprom (Memtim0), Offset 0X0C0
Tiva TM4C1294NCPDT Microcontroller Register 12: Memory Timing Parameter Register 0 for Main Flash and EEPROM (MEMTIM0), offset 0x0C0 The MEMTIM0 register provides timing parameters for the main Flash and EEPROM memories. The timing parameters apply to the memory while the system is in run or sleep mode; the clocking for these modes is consistent and unchanged since the system clock frequency and source remains unchanged during transitions between run-to-sleep and sleep-back-to-run.
Page 278: Texas Instruments-Production Data
0x8-0xF reserved 15:10 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 279: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description FBCHT Flash Bank Clock High Time Specifies the length of the flash bank clock high time Value Description 1/2 system clock period 1 system clock period 1.5 system clock periods 2 system clock periods 2.5 system clock periods...
Page 280: Register 13: Alternate Clock Configuration (Altclkcfg), Offset 0X138
Hibernation Real-time Clock Output is selected, the clock source must also be enabled in the Hibernation module. Value Description PIOSC 0x1-0x2 reserved Hibernation Module Real-time clock output (RTCOSC) Low-frequency internal oscillator (LFIOSC) 0x5-0x15 reserved June 18, 2014 Texas Instruments-Production Data...
Page 281: Register 14: Deep Sleep Clock Configuration Register (Dsclkcfg), Offset 0X144
Tiva TM4C1294NCPDT Microcontroller Register 14: Deep Sleep Clock Configuration Register (DSCLKCFG), offset 0x144 The DSCLKCFG register specifies the behavior of the clock system while in deep sleep. Note that the MOSCDPD bit not only affects deep-sleep mode, but all other modes as well depending on the value of the bit.
Page 282: Texas Instruments-Production Data
19:10 reserved 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 283: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description DSSYSDIV Deep Sleep Clock Divisor This field specifies the system clock divisor value during deep sleep mode. The clock source selected by DSOSCSRC is divided by DSSYSDIV + 1: /(DSSYSDIV + 1)
Page 284: Register 15: Divisor And Source Clock Configuration (Divsclk), Offset 0X148
MOSC reserved 15:8 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 285: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description Divisor Value This field controls the ratio of the source clock to the output clock. The output clock frequency is equal to the source clock frequency divided by the DIV field value plus 1.
Page 286: Register 16: System Properties (Sysprop), Offset 0X14C
PIOSC in Deep-Sleep mode. Value Description The status of the PIOSCPD bit is ignored. The PIOSCPD bit can be set to power down the PIOSC in Deep-Sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 287: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description SRAMSM SRAM Sleep/Deep-Sleep Standby Mode Present This bit determines whether the SRAMPM field in the SLPPWRCFG and DSLPPWRCFG registers can be configured to put the SRAM into Standby mode while in Sleep or Deep-Sleep mode.
Page 288: Texas Instruments-Production Data
FPU Present This bit indicates if the FPU is present in the Cortex-M4 core. Value Description FPU is not present. FPU is present. June 18, 2014 Texas Instruments-Production Data...
Page 289: Register 17: Precision Internal Oscillator Calibration (Piosccal), Offset 0X150
Tiva TM4C1294NCPDT Microcontroller Register 17: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 This register provides the ability to update or recalibrate the precision internal oscillator. Note that a 32.768-kHz oscillator must be used as the Hibernation module clock source for the user to be able to calibrate the PIOSC.
Page 290: Texas Instruments-Production Data
System Control Bit/Field Name Type Reset Description User Trim Value User trim value that can be loaded into the PIOSC. June 18, 2014 Texas Instruments-Production Data...
Page 291: Register 18: Precision Internal Oscillator Statistics (Pioscstat), Offset 0X154
Tiva TM4C1294NCPDT Microcontroller Register 18: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 This register provides the user information on the PIOSC calibration. Note that a 32.768-kHz oscillator must be used as the Hibernation module clock source for the user to be able to calibrate the PIOSC.
Page 292: Register 19: Pll Frequency 0 (Pllfreq0), Offset 0X160
19:10 MFRAC PLL M Fractional Value MINT 0x00 PLL M Integer Value This field contains the integer value of the PLL M value. June 18, 2014 Texas Instruments-Production Data...
Page 293: Register 20: Pll Frequency 1 (Pllfreq1), Offset 0X164
Tiva TM4C1294NCPDT Microcontroller Register 20: PLL Frequency 1 (PLLFREQ1), offset 0x164 This register always contains the current Q and N values presented to the system PLL. If the PLL is reconfigured, it must go through a relock sequence which takes about 128 PIOSC clocks. When controlling this register directly, software must change this value while the PLL is powered down.
Page 294: Register 21: Pll Status (Pllstat), Offset 0X168
LOCK PLL Lock Value Description The PLL is unpowered or is not yet locked. The PLL powered and locked. June 18, 2014 Texas Instruments-Production Data...
Page 295: Register 22: Sleep Power Configuration (Slppwrcfg), Offset 0X188
Tiva TM4C1294NCPDT Microcontroller Register 22: Sleep Power Configuration (SLPPWRCFG), offset 0x188 This register provides configuration information for the power control of the SRAM and Flash memory while in Sleep mode. Sleep Power Configuration (SLPPWRCFG) Base 0x400F.E000 Offset 0x188 Type RW, reset 0x0000.0000...
Page 296: Texas Instruments-Production Data
SRAM is placed in standby mode while in Sleep mode. Reserved Low Power Mode SRAM is placed in low power mode. This mode provides the slowest time to sleep and wakeup but the lowest power consumption while in Sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 297: Register 23: Deep-Sleep Power Configuration (Dslppwrcfg), Offset 0X18C
Tiva TM4C1294NCPDT Microcontroller Register 23: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C This register provides configuration information for the power control of the SRAM and Flashmemory while in Deep-Sleep mode. Deep-Sleep Power Configuration (DSLPPWRCFG) Base 0x400F.E000 Offset 0x18C Type RW, reset 0x0000.0000...
Page 298: Texas Instruments-Production Data
SRAM is place in standby mode while in Deep-Sleep mode. Reserved Low Power Mode SRAM is placed in low power mode. This mode provides the slowest time to sleep and wakeup but the lowest power consumption while in Deep-Sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 299: Register 24: Non-Volatile Memory Information (Nvmstat), Offset 0X1A0
Tiva TM4C1294NCPDT Microcontroller Register 24: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 This register is predefined by the part and can be used to verify features. Non-Volatile Memory Information (NVMSTAT) Base 0x400F.E000 Offset 0x1A0 Type RO, reset 0x0000.0001 reserved Type Reset...
Page 300: Register 25: Ldo Sleep Power Control (Ldospctl), Offset 0X1B4
VLDO field. 30:8 reserved 0x000.00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 301: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description VLDO 0x18 LDO Output Voltage This field provides program control of the LDO output voltage in Sleep mode. The value of the field is only used for the LDO voltage when the VADJEN bit is set.
Page 302: Register 26: Ldo Sleep Power Calibration (Ldospcal), Offset 0X1B8
The value in this field is the suggested value for the VLDO field in the LDOSPCTL register when not using the PLL. This value provides the lowest recommended LDO output voltage for use without the PLL. June 18, 2014 Texas Instruments-Production Data...
Page 303: Register 27: Ldo Deep-Sleep Power Control (Ldodpctl), Offset 0X1Bc
Tiva TM4C1294NCPDT Microcontroller Register 27: LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC This register specifies the LDO output voltage in Sleep mode. This register should be configured while in Run Mode. If the VADJEN bit is set, writes can be made to the VLDO field within the provided encodings.
Page 304: Texas Instruments-Production Data
Deep-Sleep mode. The value of the field is only used for the LDO voltage when the VADJEN bit is set. Value Description 0x12 0.90 V 0x13 0.95 V 0x14 1.00 V 0x15 1.05 V 0x16 1.10 V 0x17 1.15 V 0x18 1.20 V 0x19 - 0xFF reserved June 18, 2014 Texas Instruments-Production Data...
Page 305: Register 28: Ldo Deep-Sleep Power Calibration (Ldodpcal), Offset 0X1C0
Tiva TM4C1294NCPDT Microcontroller Register 28: LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0 This register provides factory determined values that are recommended for the VLDO field in the LDODPCTL register while in Deep-Sleep mode. The reset value of this register cannot be determined until the product has been characterized.
Page 306: Register 29: Sleep / Deep-Sleep Power Mode Status (Sdpmst), Offset 0X1Cc
The microcontroller is currently in Sleep or Deep-Sleep mode and is waiting for an interrupt or is in the process of powering up. The status of this bit is not affected by the power state of the Flash memory or SRAM. June 18, 2014 Texas Instruments-Production Data...
Page 307: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description PRACT Sleep or Deep-Sleep Power Request Active Value Description A power request is not active. The microcontroller is currently in Deep-Sleep mode or is in Sleep mode and a request to put the SRAM and/or Flash memory into a lower power mode is currently active as configured by the SLPPWRCFG register.
Page 308: Texas Instruments-Production Data
SRAM Power Down Request Error Value Description No error. An error has occurred because software has requested an SRAM power down mode that is not available using the SRAMPM field in the SLPPWRCFG or the DSLPPWRCFG register. June 18, 2014 Texas Instruments-Production Data...
Page 309: Register 30: Reset Behavior Control Register (Resbehavctl), Offset 0X1D8
Tiva TM4C1294NCPDT Microcontroller Register 30: Reset Behavior Control Register (RESBEHAVCTL), offset 0x1D8 The Reset Behavior Control Register contains system management controls. The RESBEHAVCTL register effect occurs immediately when the register is changed. The next power-on reset sequence returns the reset value.
Page 310: Texas Instruments-Production Data
Brown Out Reset issues a simulated POR sequence (default). EXTRES External RST Pin Operation Value Description 0x0 - 0x1 Reserved. Default operation is performed. External RST assertion issues a system reset. External RST assertion issues a simulated POR sequence (default). June 18, 2014 Texas Instruments-Production Data...
Page 311: Register 31: Hardware System Service Request (Hssr), Offset 0X1F4
Tiva TM4C1294NCPDT Microcontroller Register 31: Hardware System Service Request (HSSR), offset 0x1F4 The HSSR register is used to control system configuration functions, such as Return-to-Factory settings. A write to the HSSR register stores a command descriptor pointer (CDOFF) value if the KEY field is correct (0xCA).
Page 312: Register 32: Usb Power Domain Status (Usbpds), Offset 0X280
MEMSTAT Memory Array Power Status Displays status of USB SRAM memory Value Description Array OFF SRAM Retention Reserved Array On PWRSTAT Power Domain Status Value Description 0x1-0x2 Reserved June 18, 2014 Texas Instruments-Production Data...
Page 313: Register 33: Usb Memory Power Control (Usbmpc), Offset 0X284
Tiva TM4C1294NCPDT Microcontroller Register 33: USB Memory Power Control (USBMPC), offset 0x284 This register provides power control to the peripheral memory array. Note: If the USBMPC register's PWRCTL field is set to 0x3 and the power domain to the USB is turned off by writing a 0 to the P0 bit of the PCUSB register, then the SRAM memory goes into retention and the MEMSTAT field of the USBPDS register reads as 0x1 (retention).
Page 314: Register 34: Ethernet Mac Power Domain Status (Emacpds), Offset 0X288
MEMSTAT Memory Array Power Status Displays status of EMAC SRAM memory Value Description Array OFF 0x1-0x2 Reserved Array On PWRSTAT Power Domain Status Value Description 0x1-0x2 Reserved June 18, 2014 Texas Instruments-Production Data...
Page 315: Register 35: Ethernet Mac Memory Power Control (Emacmpc), Offset 0X28C
Tiva TM4C1294NCPDT Microcontroller Register 35: Ethernet MAC Memory Power Control (EMACMPC), offset 0x28C This register provides power control to the peripheral memory array. Note: The EMAC memory array does not support retention and can only be turned ON and OFF.
Page 316: Register 36: Can 0 Power Domain Status (Can0Pds), Offset 0X298
MEMSTAT Memory Array Power Status Displays status of the CAN0 SRAM memory Value Description Array OFF 0x1-0x2 Reserved Array On PWRSTAT Power Domain Status Value Description 0x1-0x2 Reserved June 18, 2014 Texas Instruments-Production Data...
Page 317: Register 37: Can 0 Memory Power Control (Can0Mpc), Offset 0X29C
Tiva TM4C1294NCPDT Microcontroller Register 37: CAN 0 Memory Power Control (CAN0MPC), offset 0x29C This register provides power control to the peripheral memory array. Note: The CAN0 memory array does not support retention and can only be turned ON and OFF.
Page 318: Register 38: Can 1 Power Domain Status (Can1Pds), Offset 0X2A0
MEMSTAT Memory Array Power Status Displays status of CAN1 SRAM memory Value Description Array OFF 0x1-0x2 Reserved Array On PWRSTAT Power Domain Status Value Description 0x1-0x2 Reserved June 18, 2014 Texas Instruments-Production Data...
Page 319: Register 39: Can 1 Memory Power Control (Can1Mpc), Offset 0X2A4
Tiva TM4C1294NCPDT Microcontroller Register 39: CAN 1 Memory Power Control (CAN1MPC), offset 0x2A4 This register provides power control to the peripheral memory array. Note: The CAN1 memory array does not support retention and can only be turned ON and OFF.
Page 320: Register 40: Watchdog Timer Peripheral Present (Ppwd), Offset 0X300
Watchdog Timer 1 Present Value Description Watchdog module 1 is not present. Watchdog module 1 is present. Watchdog Timer 0 Present Value Description Watchdog module 0 is not present. Watchdog module 0 is present. June 18, 2014 Texas Instruments-Production Data...
Page 321: Register 41: 16/32-Bit General-Purpose Timer Peripheral Present (Pptimer), Offset 0X304
Tiva TM4C1294NCPDT Microcontroller Register 41: 16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER), offset 0x304 The PPTIMER register provides software information regarding the 16/32-bit general-purpose timer modules. Important: This register should be used to determine which timers are implemented on this microcontroller.
Page 322: Texas Instruments-Production Data
16/32-bit general-purpose timer module 1 is not present. 16/32-bit general-purpose timer module 1 is present. 16/32-Bit General-Purpose Timer 0 Present Value Description 16/32-bit general-purpose timer module 0 is not present. 16/32-bit general-purpose timer module 0 is present. June 18, 2014 Texas Instruments-Production Data...
Page 323: Register 42: General-Purpose Input/Output Peripheral Present (Ppgpio), Offset 0X308
Tiva TM4C1294NCPDT Microcontroller Register 42: General-Purpose Input/Output Peripheral Present (PPGPIO), offset 0x308 The PPGPIO register provides software information regarding the general-purpose input/output modules. Important: This register should be used to determine which GPIO ports are implemented on this microcontroller. General-Purpose Input/Output Peripheral Present (PPGPIO) Base 0x400F.E000...
Page 324: Texas Instruments-Production Data
GPIO Port F Present Value Description GPIO Port F is not present. GPIO Port F is present. GPIO Port E Present Value Description GPIO Port E is not present. GPIO Port E is present. June 18, 2014 Texas Instruments-Production Data...
Page 325: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description GPIO Port D Present Value Description GPIO Port D is not present. GPIO Port D is present. GPIO Port C Present Value Description GPIO Port C is not present. GPIO Port C is present.
Page 326: Register 43: Micro Direct Memory Access Peripheral Present (Ppdma), Offset 0X30C
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Module Present Value Description μDMA module is not present. μDMA module is present. June 18, 2014 Texas Instruments-Production Data...
Page 327: Register 44: Epi Peripheral Present (Ppepi), Offset 0X310
Tiva TM4C1294NCPDT Microcontroller Register 44: EPI Peripheral Present (PPEPI), offset 0x310 The PPEPI register provides software information regarding the EPI module. Important: This register should be used to determine if the EPI module is implemented on this microcontroller. EPI Peripheral Present (PPEPI) Base 0x400F.E000...
Page 328: Register 45: Hibernation Peripheral Present (Pphib), Offset 0X314
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hibernation Module Present Value Description Hibernation module is not present. Hibernation module is present. June 18, 2014 Texas Instruments-Production Data...
Page 329: Register 46: Universal Asynchronous Receiver/Transmitter Peripheral Present (Ppuart), Offset 0X318
Tiva TM4C1294NCPDT Microcontroller Register 46: Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART), offset 0x318 The PPUART register provides software information regarding the UART modules. Important: This register should be used to determine which UART modules are implemented on this microcontroller. Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART) Base 0x400F.E000...
Page 330: Texas Instruments-Production Data
UART Module 1 Present Value Description UART module 1 is not present. UART module 1 is present. UART Module 0 Present Value Description UART module 0 is not present. UART module 0 is present. June 18, 2014 Texas Instruments-Production Data...
Page 331: Register 47: Synchronous Serial Interface Peripheral Present (Ppssi), Offset 0X31C
Tiva TM4C1294NCPDT Microcontroller Register 47: Synchronous Serial Interface Peripheral Present (PPSSI), offset 0x31C The PPSSI register provides software information regarding the SSI modules. Important: This register should be used to determine which SSI modules are implemented on this microcontroller. However, to support legacy software, the DC2 register is available. A read of the DC2 register correctly identifies if a legacy SSI module is present.
Page 332: Texas Instruments-Production Data
System Control Bit/Field Name Type Reset Description SSI Module 0 Present Value Description SSI module 0 is not present. SSI module 0 is present. June 18, 2014 Texas Instruments-Production Data...
Page 333: Register 48: Inter-Integrated Circuit Peripheral Present (Ppi2C), Offset 0X320
Tiva TM4C1294NCPDT Microcontroller Register 48: Inter-Integrated Circuit Peripheral Present (PPI2C), offset 0x320 The PPI2C register provides software information regarding the I C modules. Important: This register should be used to determine which I C modules are implemented on this microcontroller.
Page 334: Texas Instruments-Production Data
C Module 1 Present Value Description C module 1 is not present. C module 1 is present. C Module 0 Present Value Description C module 0 is not present. C module 0 is present. June 18, 2014 Texas Instruments-Production Data...
Page 335: Register 49: Universal Serial Bus Peripheral Present (Ppusb), Offset 0X328
Tiva TM4C1294NCPDT Microcontroller Register 49: Universal Serial Bus Peripheral Present (PPUSB), offset 0x328 The PPUSB register provides software information regarding the USB module. Important: This register should be used to determine if the USB module is implemented on this microcontroller.
Page 336: Register 50: Ethernet Phy Peripheral Present (Ppephy), Offset 0X330
Ethernet PHY Module Present Value Description Ethernet PHY module is not present. Ethernet PHY module is present. June 18, 2014 Texas Instruments-Production Data...
Page 337: Register 51: Controller Area Network Peripheral Present (Ppcan), Offset 0X334
Tiva TM4C1294NCPDT Microcontroller Register 51: Controller Area Network Peripheral Present (PPCAN), offset 0x334 The PPCAN register provides software information regarding the CAN modules. Important: This register should be used to determine which CAN modules are implemented on this microcontroller. Controller Area Network Peripheral Present (PPCAN) Base 0x400F.E000...
Page 338: Register 52: Analog-To-Digital Converter Peripheral Present (Ppadc), Offset 0X338
ADC Module 1 Present Value Description ADC module 1 is not present. ADC module 1 is present. ADC Module 0 Present Value Description ADC module 0 is not present. ADC module 0 is present. June 18, 2014 Texas Instruments-Production Data...
Page 339: Register 53: Analog Comparator Peripheral Present (Ppacmp), Offset 0X33C
Tiva TM4C1294NCPDT Microcontroller Register 53: Analog Comparator Peripheral Present (PPACMP), offset 0x33C The PPACMP register provides software information regarding the analog comparator module. Important: This register should be used to determine if the analog comparator module is implemented on this microcontroller.
Page 340: Register 54: Pulse Width Modulator Peripheral Present (Pppwm), Offset 0X340
PWM Module 0 Present Value Description PWM module 0 is not present. PWM module 0 is present. June 18, 2014 Texas Instruments-Production Data...
Page 341: Register 55: Quadrature Encoder Interface Peripheral Present (Ppqei), Offset 0X344
Tiva TM4C1294NCPDT Microcontroller Register 55: Quadrature Encoder Interface Peripheral Present (PPQEI), offset 0x344 The PPQEI register provides software information regarding the QEI modules. Important: This register should be used to determine which QEI modules are implemented on this microcontroller. Quadrature Encoder Interface Peripheral Present (PPQEI) Base 0x400F.E000...
Page 342: Register 56: Low Pin Count Interface Peripheral Present (Pplpc), Offset 0X348
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. LPC Module Present Value Description LPC module is not present. LPC module is present. June 18, 2014 Texas Instruments-Production Data...
Page 343: Register 57: Platform Environment Control Interface Peripheral Present (Pppeci), Offset 0X350
Tiva TM4C1294NCPDT Microcontroller Register 57: Platform Environment Control Interface Peripheral Present (PPPECI), offset 0x350 The PPPECI register provides software information regarding the PECI module. Platform Environment Control Interface Peripheral Present (PPPECI) Base 0x400F.E000 Offset 0x350 Type RO, reset 0x0000.0000 reserved...
Page 344: Register 58: Fan Control Peripheral Present (Ppfan), Offset 0X354
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FAN Module 0 Present Value Description FAN module is not present. FAN module is present. June 18, 2014 Texas Instruments-Production Data...
Page 345: Register 59: Eeprom Peripheral Present (Ppeeprom), Offset 0X358
Tiva TM4C1294NCPDT Microcontroller Register 59: EEPROM Peripheral Present (PPEEPROM), offset 0x358 The PPEEPROM register provides software information regarding the EEPROM module. EEPROM Peripheral Present (PPEEPROM) Base 0x400F.E000 Offset 0x358 Type RO, reset 0x0000.0001 reserved Type Reset reserved Type Reset Bit/Field...
Page 346: Register 60: 32/64-Bit Wide General-Purpose Timer Peripheral Present (Ppwtimer), Offset 0X35C
32/64-Bit Wide General-Purpose Timer 0 Present Value Description 32/64-bit wide general-purpose timer module 0 is not present. 32/64-bit wide general-purpose timer module 0 is present. June 18, 2014 Texas Instruments-Production Data...
Page 347: Register 61: Remote Temperature Sensor Peripheral Present (Pprts), Offset 0X370
Tiva TM4C1294NCPDT Microcontroller Register 61: Remote Temperature Sensor Peripheral Present (PPRTS), offset 0x370 The PPRTS register provides software information regarding the Remote Temperature Sensor (RTS) module. Important: This register should be used to determine which RTS modules are implemented on this microcontroller.
Page 348: Register 62: Crc Module Peripheral Present (Ppccm), Offset 0X374
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CRC Modules Present Value Description The CRC module is not present. The CRC module is present. June 18, 2014 Texas Instruments-Production Data...
Page 349: Register 63: Lcd Peripheral Present (Pplcd), Offset 0X390
Tiva TM4C1294NCPDT Microcontroller Register 63: LCD Peripheral Present (PPLCD), offset 0x390 The PPLCD register provides software information regarding the LCD module. Important: This register should be used to determine if an LCD controller is implemented on this microcontroller. LCD Peripheral Present (PPLCD) Base 0x400F.E000...
Page 350: Register 64: 1-Wire Peripheral Present (Ppowire), Offset 0X398
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1-Wire Module Present Value Description 1-Wire module is not present. 1-Wire module is present. June 18, 2014 Texas Instruments-Production Data...
Page 351: Register 65: Ethernet Mac Peripheral Present (Ppemac), Offset 0X39C
Tiva TM4C1294NCPDT Microcontroller Register 65: Ethernet MAC Peripheral Present (PPEMAC), offset 0x39C The PPEMAC register provides software information regarding the Ethernet controller module. Important: This register should be used to determine which Ethernet controller modules are implemented on this microcontroller.
Page 352: Register 66: Power Regulator Bus Peripheral Present (Ppprb), Offset 0X3A0
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PRB Module Present Value Description PRB module is not present. PRB module is present. June 18, 2014 Texas Instruments-Production Data...
Page 353: Register 67: Human Interface Master Peripheral Present (Pphim), Offset 0X3A4
Tiva TM4C1294NCPDT Microcontroller Register 67: Human Interface Master Peripheral Present (PPHIM), offset 0x3A4 The PPHIM register provides software information regarding the Human Interface Master (HIM) module. Important: This register should be used to determine which HIM modules are implemented on this microcontroller.
Page 354: Register 68: Watchdog Timer Software Reset (Srwd), Offset 0X500
Watchdog Timer 1 Software Reset Value Description Watchdog module 1 is not reset. Watchdog module 1 is reset. Watchdog Timer 0 Software Reset Value Description Watchdog module 0 is not reset. Watchdog module 0 is reset. June 18, 2014 Texas Instruments-Production Data...
Page 355: Register 69: 16/32-Bit General-Purpose Timer Software Reset (Srtimer), Offset 0X504
Tiva TM4C1294NCPDT Microcontroller Register 69: 16/32-Bit General-Purpose Timer Software Reset (SRTIMER), offset 0x504 The SRTIMER register provides software the capability to reset the available 16/32-bit timer modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRTIMER register. While the SRTIMER bit is 1, the peripheral is held in reset.
Page 356: Texas Instruments-Production Data
16/32-bit general-purpose timer module 1 is not reset. 16/32-bit general-purpose timer module 1 is reset. 16/32-Bit General-Purpose Timer 0 Software Reset Value Description 16/32-bit general-purpose timer module 0 is not reset. 16/32-bit general-purpose timer module 0 is reset. June 18, 2014 Texas Instruments-Production Data...
Page 357: Register 70: General-Purpose Input/Output Software Reset (Srgpio), Offset 0X508
Tiva TM4C1294NCPDT Microcontroller Register 70: General-Purpose Input/Output Software Reset (SRGPIO), offset 0x508 The SRGPIO register provides software the capability to reset the available GPIO modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRGPIO register. While the SRGPIO bit is 1, the peripheral is held in reset.
Page 358: Texas Instruments-Production Data
GPIO Port H Software Reset Value Description GPIO Port H is not reset. GPIO Port H is reset. GPIO Port G Software Reset Value Description GPIO Port G is not reset. GPIO Port G is reset. June 18, 2014 Texas Instruments-Production Data...
Page 359: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description GPIO Port F Software Reset Value Description GPIO Port F is not reset. GPIO Port F is reset. GPIO Port E Software Reset Value Description GPIO Port E is not reset. GPIO Port E is reset.
Page 360: Register 71: Micro Direct Memory Access Software Reset (Srdma), Offset 0X50C
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Module Software Reset Value Description μDMA module is not reset. μDMA module is reset. June 18, 2014 Texas Instruments-Production Data...
Page 361: Register 72: Epi Software Reset (Srepi), Offset 0X510
Tiva TM4C1294NCPDT Microcontroller Register 72: EPI Software Reset (SREPI), offset 0x510 The SREPI register provides software the capability to reset the available EPI module. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SREPI register. While the SREPI bit is 1, the peripheral is held in reset.
Page 362: Register 73: Hibernation Software Reset (Srhib), Offset 0X514
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hibernation Module Software Reset Value Description Hibernation module is not reset. Hibernation module is reset. June 18, 2014 Texas Instruments-Production Data...
Page 363: Register 74: Universal Asynchronous Receiver/Transmitter Software Reset (Sruart), Offset 0X518
Tiva TM4C1294NCPDT Microcontroller Register 74: Universal Asynchronous Receiver/Transmitter Software Reset (SRUART), offset 0x518 The SRUART register provides software the capability to reset the available UART modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRUART register. While the SRUART bit is 1, the peripheral is held in reset.
Page 364: Texas Instruments-Production Data
UART Module 1 Software Reset Value Description UART module 1 is not reset. UART module 1 is reset. UART Module 0 Software Reset Value Description UART module 0 is not reset. UART module 0 is reset. June 18, 2014 Texas Instruments-Production Data...
Page 365: Register 75: Synchronous Serial Interface Software Reset (Srssi), Offset 0X51C
Tiva TM4C1294NCPDT Microcontroller Register 75: Synchronous Serial Interface Software Reset (SRSSI), offset 0x51C The SRSSI register provides software the capability to reset the available SSI modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRSSI register. While the SRSSI bit is 1, the peripheral is held in reset.
Page 366: Texas Instruments-Production Data
SSI Module 1 Software Reset Value Description SSI module 1 is not reset. SSI module 1 is reset. SSI Module 0 Software Reset Value Description SSI module 0 is not reset. SSI module 0 is reset. June 18, 2014 Texas Instruments-Production Data...
Page 367: Register 76: Inter-Integrated Circuit Software Reset (Sri2C), Offset 0X520
Tiva TM4C1294NCPDT Microcontroller Register 76: Inter-Integrated Circuit Software Reset (SRI2C), offset 0x520 The SRI2C register provides software the capability to reset the available I C modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRI2C register. While the SRI2C bit is 1, the peripheral is held in reset.
Page 368: Texas Instruments-Production Data
C Module 1 Software Reset Value Description C module 1 is not reset. C module 1 is reset. C Module 0 Software Reset Value Description C module 0 is not reset. C module 0 is reset. June 18, 2014 Texas Instruments-Production Data...
Page 369: Register 77: Universal Serial Bus Software Reset (Srusb), Offset 0X528
Tiva TM4C1294NCPDT Microcontroller Register 77: Universal Serial Bus Software Reset (SRUSB), offset 0x528 The SRUSB register provides software the capability to reset the available USB module. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRUSB register. While the SRUSB bit is 1, the peripheral is held in reset.
Page 370: Register 78: Ethernet Phy Software Reset (Srephy), Offset 0X530
Ethernet PHY Module Software Reset Value Description Ethernet PHY module is not reset. Ethernet PHY module is reset. June 18, 2014 Texas Instruments-Production Data...
Page 371: Register 79: Controller Area Network Software Reset (Srcan), Offset 0X534
Tiva TM4C1294NCPDT Microcontroller Register 79: Controller Area Network Software Reset (SRCAN), offset 0x534 The SRCAN register provides software the capability to reset the available CAN modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRCAN register. While the SRCAN bit is 1, the peripheral is held in reset.
Page 372: Register 80: Analog-To-Digital Converter Software Reset (Sradc), Offset 0X538
ADC Module 1 Software Reset Value Description ADC module 1 is not reset. ADC module 1 is reset. ADC Module 0 Software Reset Value Description ADC module 0 is not reset. ADC module 0 is reset. June 18, 2014 Texas Instruments-Production Data...
Page 373: Register 81: Analog Comparator Software Reset (Sracmp), Offset 0X53C
Tiva TM4C1294NCPDT Microcontroller Register 81: Analog Comparator Software Reset (SRACMP), offset 0x53C The SRACMP register provides software the capability to reset the available analog comparator module. A block is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRACMP register. While the SRACMP bit is 1, the module is held in reset.
Page 374: Register 82: Pulse Width Modulator Software Reset (Srpwm), Offset 0X540
PWM Module 0 Software Reset Value Description PWM module 0 is not reset. PWM module 0 is reset. June 18, 2014 Texas Instruments-Production Data...
Page 375: Register 83: Quadrature Encoder Interface Software Reset (Srqei), Offset 0X544
Tiva TM4C1294NCPDT Microcontroller Register 83: Quadrature Encoder Interface Software Reset (SRQEI), offset 0x544 The SRQEI register provides software the capability to reset the available QEI modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRQEI register. While the SRQEI bit is 1, the peripheral is held in reset.
Page 376: Register 84: Eeprom Software Reset (Sreeprom), Offset 0X558
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. EEPROM Module 0 Software Reset Value Description EEPROM module is not reset. EEPROM module is reset. June 18, 2014 Texas Instruments-Production Data...
Page 377: Register 85: Crc Module Software Reset (Srccm), Offset 0X574
Tiva TM4C1294NCPDT Microcontroller Register 85: CRC Module Software Reset (SRCCM), offset 0x574 The SRCCM register provides software the capability to reset the CRC . A module is reset by software using a simple two-step process: 1. Software sets the bit in the SRCCM register. While the SRCCM bit is 1, the peripheral is held in reset.
Page 378: Register 86: Ethernet Mac Software Reset (Sremac), Offset 0X59C
Ethernet Controller MAC Module 0 Software Reset Value Description Ethernet Controller MAC module 0 is not reset. Ethernet Controller MAC module 0 is reset. June 18, 2014 Texas Instruments-Production Data...
Page 379: Register 87: Watchdog Timer Run Mode Clock Gating Control (Rcgcwd), Offset 0X600
Tiva TM4C1294NCPDT Microcontroller Register 87: Watchdog Timer Run Mode Clock Gating Control (RCGCWD), offset 0x600 The RCGCWD register provides software the capability to enable and disable watchdog modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed.
Page 380: Register 88: 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (Rcgctimer), Offset 0X604
6 in Run mode. 16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control Value Description 16/32-bit general-purpose timer module 5 is disabled. Enable and provide a clock to 16/32-bit general-purpose timer module 5 in Run mode. June 18, 2014 Texas Instruments-Production Data...
Page 381: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control Value Description 16/32-bit general-purpose timer module 4 is disabled. Enable and provide a clock to 16/32-bit general-purpose timer module 4 in Run mode.
Page 382: Register 89: General-Purpose Input/Output Run Mode Clock Gating Control (Rcgcgpio), Offset 0X608
Enable and provide a clock to GPIO Port N in Run mode. GPIO Port M Run Mode Clock Gating Control Value Description GPIO Port M is disabled. Enable and provide a clock to GPIO Port M in Run mode. June 18, 2014 Texas Instruments-Production Data...
Page 383: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description GPIO Port L Run Mode Clock Gating Control Value Description GPIO Port L is disabled. Enable and provide a clock to GPIO Port L in Run mode. GPIO Port K Run Mode Clock Gating Control...
Page 384: Texas Instruments-Production Data
Enable and provide a clock to GPIO Port B in Run mode. GPIO Port A Run Mode Clock Gating Control Value Description GPIO Port A is disabled. Enable and provide a clock to GPIO Port A in Run mode. June 18, 2014 Texas Instruments-Production Data...
Page 385: Register 90: Micro Direct Memory Access Run Mode Clock Gating Control (Rcgcdma), Offset 0X60C
Tiva TM4C1294NCPDT Microcontroller Register 90: Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA), offset 0x60C The RCGCDMA register provides software the capability to enable and disable the μDMA module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed.
Page 386: Register 91: Epi Run Mode Clock Gating Control (Rcgcepi), Offset 0X610
EPI Module Run Mode Clock Gating Control Value Description EPI module is disabled. Enable and provide a clock to the EPI module in Run mode. June 18, 2014 Texas Instruments-Production Data...
Page 387: Register 92: Hibernation Run Mode Clock Gating Control (Rcgchib), Offset 0X614
Tiva TM4C1294NCPDT Microcontroller Register 92: Hibernation Run Mode Clock Gating Control (RCGCHIB), offset 0x614 The RCGCHIB register provides software the capability to enable and disable the Hibernation module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed.
Page 388: Register 93: Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (Rcgcuart), Offset 0X618
Enable and provide a clock to UART module 5 in Run mode. UART Module 4 Run Mode Clock Gating Control Value Description UART module 4 is disabled. Enable and provide a clock to UART module 4 in Run mode. June 18, 2014 Texas Instruments-Production Data...
Page 389: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description UART Module 3 Run Mode Clock Gating Control Value Description UART module 3 is disabled. Enable and provide a clock to UART module 3 in Run mode. UART Module 2 Run Mode Clock Gating Control...
Page 390: Register 94: Synchronous Serial Interface Run Mode Clock Gating Control (Rcgcssi), Offset 0X61C
Enable and provide a clock to SSI module 1 in Run mode. SSI Module 0 Run Mode Clock Gating Control Value Description SSI module 0 is disabled. Enable and provide a clock to SSI module 0 in Run mode. June 18, 2014 Texas Instruments-Production Data...
Page 391: Register 95: Inter-Integrated Circuit Run Mode Clock Gating Control (Rcgci2C), Offset 0X620
Tiva TM4C1294NCPDT Microcontroller Register 95: Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C), offset 0x620 The RCGCI2C register provides software the capability to enable and disable the I C modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed.
Page 392: Texas Instruments-Production Data
C module 1 in Run mode. C Module 0 Run Mode Clock Gating Control Value Description C module 0 is disabled. Enable and provide a clock to I C module 0 in Run mode. June 18, 2014 Texas Instruments-Production Data...
Page 393: Register 96: Universal Serial Bus Run Mode Clock Gating Control (Rcgcusb), Offset 0X628
Tiva TM4C1294NCPDT Microcontroller Register 96: Universal Serial Bus Run Mode Clock Gating Control (RCGCUSB), offset 0x628 The RCGCUSB register provides software the capability to enable and disable the USB module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed.
Page 394: Register 97: Ethernet Phy Run Mode Clock Gating Control (Rcgcephy), Offset 0X630
Ethernet PHY Module Run Mode Clock Gating Control Value Description PHY module is disabled. Enable and provide a clock to the PHY module in Run mode. June 18, 2014 Texas Instruments-Production Data...
Page 395: Register 98: Controller Area Network Run Mode Clock Gating Control (Rcgccan), Offset 0X634
Tiva TM4C1294NCPDT Microcontroller Register 98: Controller Area Network Run Mode Clock Gating Control (RCGCCAN), offset 0x634 The RCGCCAN register provides software the capability to enable and disable the CAN modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed.
Page 396: Register 99: Analog-To-Digital Converter Run Mode Clock Gating Control (Rcgcadc), Offset 0X638
Enable and provide a clock to ADC module 1 in Run mode. ADC Module 0 Run Mode Clock Gating Control Value Description ADC module 0 is disabled. Enable and provide a clock to ADC module 0 in Run mode. June 18, 2014 Texas Instruments-Production Data...
Page 397: Register 100: Analog Comparator Run Mode Clock Gating Control (Rcgcacmp), Offset 0X63C
Tiva TM4C1294NCPDT Microcontroller Register 100: Analog Comparator Run Mode Clock Gating Control (RCGCACMP), offset 0x63C The RCGCACMP register provides software the capability to enable and disable the analog comparator module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed.
Page 398: Register 101: Pulse Width Modulator Run Mode Clock Gating Control (Rcgcpwm), Offset 0X640
PWM Module 0 Run Mode Clock Gating Control Value Description PWM module 0 is disabled. Enable and provide a clock to PWM module 0 in Run mode. June 18, 2014 Texas Instruments-Production Data...
Page 399: 0X644
Tiva TM4C1294NCPDT Microcontroller Register 102: Quadrature Encoder Interface Run Mode Clock Gating Control (RCGCQEI), offset 0x644 The RCGCQEI register provides software the capability to enable and disable the QEI modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed.
Page 400: Register 103: Eeprom Run Mode Clock Gating Control (Rcgceeprom), Offset 0X658
EEPROM Module 0 Run Mode Clock Gating Control Value Description EEPROM module is disabled. Enable and provide a clock to the EEPROM module in Run mode. June 18, 2014 Texas Instruments-Production Data...
Page 401: Register 104: Crc Module Run Mode Clock Gating Control (Rcgcccm), Offset 0X674
Tiva TM4C1294NCPDT Microcontroller Register 104: CRC Module Run Mode Clock Gating Control (RCGCCCM), offset 0x674 The RCGCCCM register provides software the capability to enable and disable the CRC in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed.
Page 402: Register 105: Ethernet Mac Run Mode Clock Gating Control (Rcgcemac), Offset 0X69C
Ethernet MAC Module 0 Run Mode Clock Gating Control Value Description Ethernet MAC module 0 is disabled. Enable and provide a clock to Ethernet MAC module 0 in Run mode. June 18, 2014 Texas Instruments-Production Data...
Page 403: Register 106: Watchdog Timer Sleep Mode Clock Gating Control (Scgcwd), Offset 0X700
Tiva TM4C1294NCPDT Microcontroller Register 106: Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD), offset 0x700 The SCGCWD register provides software the capability to enable and disable watchdog modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 404: Register 107: 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (Scgctimer), Offset 0X704
16/32-Bit General-Purpose Timer 5 Sleep Mode Clock Gating Control Value Description 16/32-bit general-purpose timer module 5 is disabled in sleep mode. Enable and provide a clock to 16/32-bit general-purpose timer module 5 in sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 405: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 16/32-Bit General-Purpose Timer 4 Sleep Mode Clock Gating Control Value Description 16/32-bit general-purpose timer module 4 is disabled in sleep mode. Enable and provide a clock to 16/32-bit general-purpose timer module 4 in sleep mode.
Page 406: 0X708
Enable and provide a clock to GPIO Port N in sleep mode. GPIO Port M Sleep Mode Clock Gating Control Value Description GPIO Port M is disabled in sleep mode. Enable and provide a clock to GPIO Port M in sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 407: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description GPIO Port L Sleep Mode Clock Gating Control Value Description GPIO Port L is disabled in sleep mode. Enable and provide a clock to GPIO Port L in sleep mode. GPIO Port K Sleep Mode Clock Gating Control...
Page 408: Texas Instruments-Production Data
Enable and provide a clock to GPIO Port B in sleep mode. GPIO Port A Sleep Mode Clock Gating Control Value Description GPIO Port A is disabled in sleep mode. Enable and provide a clock to GPIO Port A in sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 409: 0X70C
Tiva TM4C1294NCPDT Microcontroller Register 109: Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA), offset 0x70C The SCGCDMA register provides software the capability to enable and disable the μDMA module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 410: Register 110: Epi Sleep Mode Clock Gating Control (Scgcepi), Offset 0X710
EPI Module Sleep Mode Clock Gating Control Value Description EPI module is disabled in sleep mode. Enable and provide a clock to the EPI module in sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 411: Register 111: Hibernation Sleep Mode Clock Gating Control (Scgchib), Offset 0X714
Tiva TM4C1294NCPDT Microcontroller Register 111: Hibernation Sleep Mode Clock Gating Control (SCGCHIB), offset 0x714 The SCGCHIB register provides software the capability to enable and disable the Hibernation module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 412: (Scgcuart), Offset 0X718
Enable and provide a clock to UART module 5 in sleep mode. UART Module 4 Sleep Mode Clock Gating Control Value Description UART module 4 is disabled. Enable and provide a clock to UART module 4 in sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 413: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description UART Module 3 Sleep Mode Clock Gating Control Value Description UART module 3 is disabled in sleep mode. Enable and provide a clock to UART module 3 in sleep mode. UART Module 2 Sleep Mode Clock Gating Control...
Page 414: 0X71C
Enable and provide a clock to SSI module 1 in sleep mode. SSI Module 0 Sleep Mode Clock Gating Control Value Description SSI module 0 is disabled in sleep mode. Enable and provide a clock to SSI module 0 in sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 415: Register 114: Inter-Integrated Circuit Sleep Mode Clock Gating Control (Scgci2C), Offset 0X720
Tiva TM4C1294NCPDT Microcontroller Register 114: Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C), offset 0x720 The SCGCI2C register provides software the capability to enable and disable the I C modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 416: Texas Instruments-Production Data
C module 1 in sleep mode. C Module 0 Sleep Mode Clock Gating Control Value Description C module 0 is disabled. Enable and provide a clock to I C module 0 in sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 417: Register 115: Universal Serial Bus Sleep Mode Clock Gating Control (Scgcusb), Offset 0X728
Tiva TM4C1294NCPDT Microcontroller Register 115: Universal Serial Bus Sleep Mode Clock Gating Control (SCGCUSB), offset 0x728 The SCGCUSB register provides software the capability to enable and disable the USB module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 418: Register 116: Ethernet Phy Sleep Mode Clock Gating Control (Scgcephy), Offset 0X730
PHY Module Sleep Mode Clock Gating Control Value Description PHY module is disabled in sleep mode. Enable and provide a clock to the PHY module in sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 419: Register 117: Controller Area Network Sleep Mode Clock Gating Control (Scgccan), Offset 0X734
Tiva TM4C1294NCPDT Microcontroller Register 117: Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN), offset 0x734 The SCGCCAN register provides software the capability to enable and disable the CAN modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 420: 0X738
Enable and provide a clock to ADC module 1 in sleep mode. ADC Module 0 Sleep Mode Clock Gating Control Value Description ADC module 0 is disabled in sleep mode. Enable and provide a clock to ADC module 0 in sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 421: Register 119: Analog Comparator Sleep Mode Clock Gating Control (Scgcacmp), Offset 0X73C
Tiva TM4C1294NCPDT Microcontroller Register 119: Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP), offset 0x73C The SCGCACMP register provides software the capability to enable and disable the analog comparator module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 422: Register 120: Pulse Width Modulator Sleep Mode Clock Gating Control (Scgcpwm), Offset 0X740
PWM Module 0 Sleep Mode Clock Gating Control Value Description PWM module 0 is disabled in sleep mode. Enable and provide a clock to PWM module 0 in sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 423: 0X744
Tiva TM4C1294NCPDT Microcontroller Register 121: Quadrature Encoder Interface Sleep Mode Clock Gating Control (SCGCQEI), offset 0x744 The SCGCQEI register provides software the capability to enable and disable the QEI modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 424: Register 122: Eeprom Sleep Mode Clock Gating Control (Scgceeprom), Offset 0X758
EEPROM Module 0 Sleep Mode Clock Gating Control Value Description EEPROM module is disabled. Enable and provide a clock to the EEPROM module in sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 425: Register 123: Crc Module Sleep Mode Clock Gating Control (Scgcccm), Offset 0X774
Tiva TM4C1294NCPDT Microcontroller Register 123: CRC Module Sleep Mode Clock Gating Control (SCGCCCM), offset 0x774 The SCGCCCM register provides software the capability to enable and disable the CRC module in sleep mode. When enabled, the module is provided a clock . When disabled, the clock is disabled to save power.
Page 426: Register 124: Ethernet Mac Sleep Mode Clock Gating Control (Scgcemac), Offset 0X79C
Ethernet MAC Module 0 Sleep Mode Clock Gating Control Value Description Ethernet MAC module 0 is disabled in sleep mode. Enable and provide a clock to Ethernet MAC module 0 in sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 427: Register 125: Watchdog Timer Deep-Sleep Mode Clock Gating Control (Dcgcwd), Offset 0X800
Tiva TM4C1294NCPDT Microcontroller Register 125: Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD), offset 0x800 The DCGCWD register provides software the capability to enable and disable watchdog modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 428: Offset 0X804
16/32-Bit General-Purpose Timer 5 Deep-Sleep Mode Clock Gating Control Value Description 16/32-bit general-purpose timer module 5 is disabled in deep-sleep mode. Enable and provide a clock to 16/32-bit general-purpose timer module 5 in deep-sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 429: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 16/32-Bit General-Purpose Timer 4 Deep-Sleep Mode Clock Gating Control Value Description 16/32-bit general-purpose timer module 4 is disabled in deep-sleep mode. Enable and provide a clock to 16/32-bit general-purpose timer module 4 in deep-sleep mode.
Page 430: Register 127: General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (Dcgcgpio), Offset 0X808
Enable and provide a clock to GPIO Port N in deep-sleep mode. GPIO Port M Deep-Sleep Mode Clock Gating Control Value Description GPIO Port M is disabled in deep-sleep mode. Enable and provide a clock to GPIO Port M in deep-sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 431: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description GPIO Port L Deep-Sleep Mode Clock Gating Control Value Description GPIO Port L is disabled in deep-sleep mode. Enable and provide a clock to GPIO Port L in deep-sleep mode. GPIO Port K Deep-Sleep Mode Clock Gating Control...
Page 432: Texas Instruments-Production Data
Enable and provide a clock to GPIO Port B in deep-sleep mode. GPIO Port A Deep-Sleep Mode Clock Gating Control Value Description GPIO Port A is disabled in deep-sleep mode. Enable and provide a clock to GPIO Port A in deep-sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 433: 0X80C
Tiva TM4C1294NCPDT Microcontroller Register 128: Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA), offset 0x80C The DCGCDMA register provides software the capability to enable and disable the μDMA module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 434: Register 129: Epi Deep-Sleep Mode Clock Gating Control (Dcgcepi), Offset 0X810
EPI Module Deep-Sleep Mode Clock Gating Control Value Description EPI module is disabled in deep-sleep mode. Enable and provide a clock to the EPI module in deep-sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 435: Register 130: Hibernation Deep-Sleep Mode Clock Gating Control (Dcgchib), Offset 0X814
Tiva TM4C1294NCPDT Microcontroller Register 130: Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB), offset 0x814 The DCGCHIB register provides software the capability to enable and disable the Hibernation module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 436: (Dcgcuart), Offset 0X818
Enable and provide a clock to UART module 6 in deep-sleep mode. UART Module 5 Deep-Sleep Mode Clock Gating Control Value Description UART module 5 is disabled in deep-sleep mode. Enable and provide a clock to UART module 5 in deep-sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 437: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description UART Module 4 Deep-Sleep Mode Clock Gating Control Value Description UART module 4 is disabled in deep-sleep mode. Enable and provide a clock to UART module 4 in deep-sleep mode. UART Module 3 Deep-Sleep Mode Clock Gating Control...
Page 438: 0X81C
Enable and provide a clock to SSI module 1 in deep-sleep mode. SSI Module 0 Deep-Sleep Mode Clock Gating Control Value Description SSI module 0 is disabled in deep-sleep mode. Enable and provide a clock to SSI module 0 in deep-sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 439: 0X820
Tiva TM4C1294NCPDT Microcontroller Register 133: Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C), offset 0x820 The DCGCI2C register provides software the capability to enable and disable the I C modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 440: Texas Instruments-Production Data
C module 1 in deep-sleep mode. C Module 0 Deep-Sleep Mode Clock Gating Control Value Description C module 0 is disabled in deep-sleep mode. Enable and provide a clock to I C module 0 in deep-sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 441: 0X828
Tiva TM4C1294NCPDT Microcontroller Register 134: Universal Serial Bus Deep-Sleep Mode Clock Gating Control (DCGCUSB), offset 0x828 The DCGCUSB register provides software the capability to enable and disable the USB module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 442: Register 135: Ethernet Phy Deep-Sleep Mode Clock Gating Control (Dcgcephy), Offset 0X830
PHY Module Deep-Sleep Mode Clock Gating Control Value Description PHY module is disabled in deep-sleep mode. Enable and provide a clock to the PHY module in deep-sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 443: 0X834
Tiva TM4C1294NCPDT Microcontroller Register 136: Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN), offset 0x834 The DCGCCAN register provides software the capability to enable and disable the CAN modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 444: 0X838
Enable and provide a clock to ADC module 1 in deep-sleep mode. ADC Module 0 Deep-Sleep Mode Clock Gating Control Value Description ADC module 0 is disabled in deep-sleep mode. Enable and provide a clock to ADC module 0 in deep-sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 445: 0X83C
Tiva TM4C1294NCPDT Microcontroller Register 138: Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP), offset 0x83C The DCGCACMP register provides software the capability to enable and disable the analog comparator module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 446: 0X840
PWM Module 0 Deep-Sleep Mode Clock Gating Control Value Description PWM module 0 is disabled in deep-sleep mode. Enable and provide a clock to PWM module 0 in deep-sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 447: Register 140: Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (Dcgcqei), Offset 0X844
Tiva TM4C1294NCPDT Microcontroller Register 140: Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI), offset 0x844 The DCGCQEI register provides software the capability to enable and disable the QEI modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
Page 448: Register 141: Eeprom Deep-Sleep Mode Clock Gating Control (Dcgceeprom), Offset 0X858
EEPROM Module 0 Deep-Sleep Mode Clock Gating Control Value Description EEPROM module is disabled in deep-sleep mode. Enable and provide a clock to the EEPROM module in deep-sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 449: Register 142: Crc Module Deep-Sleep Mode Clock Gating Control (Dcgcccm), Offset 0X874
Tiva TM4C1294NCPDT Microcontroller Register 142: CRC Module Deep-Sleep Mode Clock Gating Control (DCGCCCM), offset 0x874 The DCGCCCM register provides software the capability to enable and disable the CRC module in deep-sleep mode. When enabled, the module is provided a clock. When disabled, the clock is disabled to save power.
Page 450: Register 143: Ethernet Mac Deep-Sleep Mode Clock Gating Control (Dcgcemac), Offset 0X89C
Ethernet MAC Module 0 Deep-Sleep Mode Clock Gating Control Value Description Ethernet MAC module 0 is disabled in deep-sleep mode. Enable and provide a clock to Ethernet MAC module 0 in deep-sleep mode. June 18, 2014 Texas Instruments-Production Data...
Page 451: Register 144: Watchdog Timer Power Control (Pcwd), Offset 0X900
Tiva TM4C1294NCPDT Microcontroller Register 144: Watchdog Timer Power Control (PCWD), offset 0x900 Important: The Watchdog Timer modules do not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption.
Page 452: Texas Instruments-Production Data
In this case, the module's state is not retained. This configuration provides the lowest power consumption state. Watchdog Timer 0 module is powered, but does not receive a clock. In this case, the module is inactive. June 18, 2014 Texas Instruments-Production Data...
Page 453: Register 145: 16/32-Bit General-Purpose Timer Power Control (Pctimer), Offset 0X904
Tiva TM4C1294NCPDT Microcontroller Register 145: 16/32-Bit General-Purpose Timer Power Control (PCTIMER), offset 0x904 Important: The Timer module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility.
Page 454: Texas Instruments-Production Data
In this case, the module's state is not retained. This configuration provides the lowest power consumption state. Timer 4 module is powered, but does not receive a clock. In this case, the module is inactive. June 18, 2014 Texas Instruments-Production Data...
Page 455: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description General-Purpose Timer 3 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCTIMER, SCGCTIMER or DCGCTIMER register is clear. Value Description Timer 3 module is not powered and does not receive a clock.
Page 456: Register 146: General-Purpose Input/Output Power Control (Pcgpio), Offset 0X908
Module is powered and receives a clock. General-Purpose Input/Output Power Control (PCGPIO) Base 0x400F.E000 Offset 0x908 Type RW, reset 0x0000.7FFF reserved Type Reset reserved Type Reset June 18, 2014 Texas Instruments-Production Data...
Page 457: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 31:15 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 458: Texas Instruments-Production Data
This configuration provides the lowest power consumption state. GPIO Port H is powered, but does not receive a clock. In this case, the module is inactive. June 18, 2014 Texas Instruments-Production Data...
Page 459: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description GPIO Port G Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear. Value Description GPIO Port G is not powered and does not receive a clock. In this case, the module's state is not retained.
Page 460: Texas Instruments-Production Data
This configuration provides the lowest power consumption state. GPIO Port A is powered, but does not receive a clock. In this case, the module is inactive. June 18, 2014 Texas Instruments-Production Data...
Page 461: Register 147: Micro Direct Memory Access Power Control (Pcdma), Offset 0X90C
Tiva TM4C1294NCPDT Microcontroller Register 147: Micro Direct Memory Access Power Control (PCDMA), offset 0x90C Important: The µDMA module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility.
Page 462: Texas Instruments-Production Data
In this case, the module's state is not retained. This configuration provides the lowest power consumption state. The µDMA module is powered, but does not receive a clock. In this case, the module is inactive. June 18, 2014 Texas Instruments-Production Data...
Page 463: Register 148: External Peripheral Interface Power Control (Pcepi), Offset 0X910
Tiva TM4C1294NCPDT Microcontroller Register 148: External Peripheral Interface Power Control (PCEPI), offset 0x910 Important: The EPI module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility.
Page 464: Texas Instruments-Production Data
In this case, the module's state is not retained. This configuration provides the lowest power consumption state. The EPI module is powered, but does not receive a clock. In this case, the module is inactive. June 18, 2014 Texas Instruments-Production Data...
Page 465: Register 149: Hibernation Power Control (Pchib), Offset 0X914
Tiva TM4C1294NCPDT Microcontroller Register 149: Hibernation Power Control (PCHIB), offset 0x914 Important: The Hibernation module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility.
Page 466: Texas Instruments-Production Data
In this case, the module's state is not retained. This configuration provides the lowest power consumption state. The HIB module is powered, but does not receive a clock. In this case, the module is inactive. June 18, 2014 Texas Instruments-Production Data...
Page 467: Register 150: Universal Asynchronous Receiver/Transmitter Power Control (Pcuart), Offset 0X918
Tiva TM4C1294NCPDT Microcontroller Register 150: Universal Asynchronous Receiver/Transmitter Power Control (PCUART), offset 0x918 Important: The UART module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility.
Page 468: Texas Instruments-Production Data
In this case, the module's state is not retained. This configuration provides the lowest power consumption state. The UART module 4 is powered, but does not receive a clock. In this case, the module is inactive. June 18, 2014 Texas Instruments-Production Data...
Page 469: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description UART Module 3 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCUART, SCGCUART or DCGCUART register is clear. Value Description The UART module 3 is not powered and does not receive a clock.
Page 470: Register 151: Synchronous Serial Interface Power Control (Pcssi), Offset 0X91C
Module is powered and receives a clock. Synchronous Serial Interface Power Control (PCSSI) Base 0x400F.E000 Offset 0x91C Type RW, reset 0x0000.000F reserved Type Reset reserved Type Reset June 18, 2014 Texas Instruments-Production Data...
Page 471: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 31:4 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 472: Register 152: Inter-Integrated Circuit Power Control (Pci2C), Offset 0X920
Reset Description 31:10 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 473: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description C Module 9 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCI2C, SCGCI2C or DCGCI2C register is clear. Value Description The I C module 9 is not powered and does not receive a clock.
Page 474: Texas Instruments-Production Data
In this case, the module's state is not retained. This configuration provides the lowest power consumption state. The I C module 2 is powered, but does not receive a clock. In this case, the module is inactive. June 18, 2014 Texas Instruments-Production Data...
Page 475: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description C Module 1 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCI2C, SCGCI2C or DCGCI2C register is clear. Value Description The I C module 1 is not powered and does not receive a clock.
Page 476: Register 153: Universal Serial Bus Power Control (Pcusb), Offset 0X928
Reset Description 31:1 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 477: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description USB Module Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCUSB, SCGCUSB or DCGCUSB register is clear. Value Description The USB module is not powered and does not receive a clock.
Page 478: Register 154: Ethernet Phy Power Control (Pcephy), Offset 0X930
Note: If the MOSC is chosen as the clock to the Ethernet PHY then software has to enable the MOSC before enabling the Ethernet PHY by setting the P0 bit in the PCEPHY. Ethernet PHY Power Control (PCEPHY) Base 0x400F.E000 Offset 0x930 Type RW, reset 0x0000.0000 reserved Type Reset reserved Type Reset June 18, 2014 Texas Instruments-Production Data...
Page 479: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 31:1 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 480: Register 155: Controller Area Network Power Control (Pccan), Offset 0X934
Reset Description 31:2 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 481: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description CAN Module 1 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCCAN, SCGCCAN or DCGCCAN register is clear. Value Description The CAN module 1 is not powered and does not receive a clock.
Page 482: Register 156: Analog-To-Digital Converter Power Control (Pcadc), Offset 0X938
Module is powered and receives a clock. Analog-to-Digital Converter Power Control (PCADC) Base 0x400F.E000 Offset 0x938 Type RW, reset 0x0000.0003 reserved Type Reset reserved Type Reset June 18, 2014 Texas Instruments-Production Data...
Page 483: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 31:2 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 484: Register 157: Analog Comparator Power Control (Pcacmp), Offset 0X93C
Reset Description 31:1 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 485: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description Analog Comparator Module 0 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCACMP, SCGCACMP or DCGCACMP register is clear. Value Description The Analog Comparator module is not powered and does not receive a clock.
Page 486: Register 158: Pulse Width Modulator Power Control (Pcpwm), Offset 0X940
Reset Description 31:1 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 487: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description PWM Module 0 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCPWM, SCGCPWM or DCGCPWM register is clear. Value Description The PWM module 0 is not powered and does not receive a clock.
Page 488: Register 159: Quadrature Encoder Interface Power Control (Pcqei), Offset 0X944
Module is powered and receives a clock. Quadrature Encoder Interface Power Control (PCQEI) Base 0x400F.E000 Offset 0x944 Type RW, reset 0x0000.0001 reserved Type Reset reserved Type Reset June 18, 2014 Texas Instruments-Production Data...
Page 489: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 31:1 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 490: Register 160: Eeprom Power Control (Pceeprom), Offset 0X958
Reset Description 31:1 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 491: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description EEPROM Module 0 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCEEPROM, SCGCEEPROM or DCGCEEPROM register is clear. Value Description The EEPROM module is not powered and does not receive a clock.
Page 492: Register 161: Crc Module Power Control (Pcccm), Offset 0X974
Reset Description 31:1 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 493: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description CRC Module Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCCCM, SCGCCCM or DCGCCCM register is clear. Value Description The CRC module is not powered and does not receive a clock.
Page 494: Register 162: Ethernet Mac Power Control (Pcemac), Offset 0X99C
Reset Description 31:1 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 495: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description Ethernet MAC Module 0 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCEMAC, SCGCEMAC or DCGCEMAC register is clear. Value Description Ethernet MAC Module 0 is not powered and does not receive a clock.
Page 496: Register 163: Watchdog Timer Peripheral Ready (Prwd), Offset 0Xa00
Watchdog Timer 0 Peripheral Ready Value Description Watchdog module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. Watchdog module 0 is ready for access. June 18, 2014 Texas Instruments-Production Data...
Page 497: Register 164: 16/32-Bit General-Purpose Timer Peripheral Ready (Prtimer), Offset 0Xa04
Tiva TM4C1294NCPDT Microcontroller Register 164: 16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER), offset 0xA04 The PRGPT32 register indicates whether the timer modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCGPT32 bit is changed from 0 to 1.
Page 498: Texas Instruments-Production Data
16/32-Bit General-Purpose Timer 0 Peripheral Ready Value Description 16/32-bit timer module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 16/32-bit timer module 0 is ready for access. June 18, 2014 Texas Instruments-Production Data...
Page 499: Register 165: General-Purpose Input/Output Peripheral Ready (Prgpio), Offset 0Xa08
Tiva TM4C1294NCPDT Microcontroller Register 165: General-Purpose Input/Output Peripheral Ready (PRGPIO), offset 0xA08 The PRGPIO register indicates whether the GPIO modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCGPIO bit is changed from 0 to 1.
Page 500: Texas Instruments-Production Data
GPIO Port F Peripheral Ready Value Description GPIO Port F is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. GPIO Port F is ready for access. June 18, 2014 Texas Instruments-Production Data...
Page 501: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description GPIO Port E Peripheral Ready Value Description GPIO Port E is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. GPIO Port E is ready for access.
Page 502: Register 166: Micro Direct Memory Access Peripheral Ready (Prdma), Offset 0Xa0C
μDMA Module Peripheral Ready Value Description The μDMA module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. The μDMA module is ready for access. June 18, 2014 Texas Instruments-Production Data...
Page 503: Register 167: Epi Peripheral Ready (Prepi), Offset 0Xa10
Tiva TM4C1294NCPDT Microcontroller Register 167: EPI Peripheral Ready (PREPI), offset 0xA10 The PREPI register indicates whether the EPI module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCEPI bit is changed from 0 to 1.
Page 504: Register 168: Hibernation Peripheral Ready (Prhib), Offset 0Xa14
Hibernation Module Peripheral Ready Value Description The Hibernation module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. The Hibernation module is ready for access. June 18, 2014 Texas Instruments-Production Data...
Page 505: Register 169: Universal Asynchronous Receiver/Transmitter Peripheral Ready (Pruart), Offset
Tiva TM4C1294NCPDT Microcontroller Register 169: Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART), offset 0xA18 The PRUART register indicates whether the UART modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCUART bit is changed from 0 to 1.
Page 506: Texas Instruments-Production Data
UART Module 0 Peripheral Ready Value Description UART module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. UART module 0 is ready for access. June 18, 2014 Texas Instruments-Production Data...
Page 507: Register 170: Synchronous Serial Interface Peripheral Ready (Prssi), Offset 0Xa1C
Tiva TM4C1294NCPDT Microcontroller Register 170: Synchronous Serial Interface Peripheral Ready (PRSSI), offset 0xA1C The PRSSI register indicates whether the SSI modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCSSI bit is changed from 0 to 1.
Page 508: Texas Instruments-Production Data
SSI Module 0 Peripheral Ready Value Description SSI module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. SSI module 0 is ready for access. June 18, 2014 Texas Instruments-Production Data...
Page 509: Register 171: Inter-Integrated Circuit Peripheral Ready (Pri2C), Offset 0Xa20
Tiva TM4C1294NCPDT Microcontroller Register 171: Inter-Integrated Circuit Peripheral Ready (PRI2C), offset 0xA20 The PRI2C register indicates whether the I C modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCI2C bit is changed from 0 to 1.
Page 510: Texas Instruments-Production Data
C Module 1 Peripheral Ready Value Description C module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. C module 1 is ready for access. June 18, 2014 Texas Instruments-Production Data...
Page 511: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description C Module 0 Peripheral Ready Value Description C module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. C module 0 is ready for access.
Page 512: Register 172: Universal Serial Bus Peripheral Ready (Prusb), Offset 0Xa28
USB Module Peripheral Ready Value Description The USB module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. The USB module is ready for access. June 18, 2014 Texas Instruments-Production Data...
Page 513: Register 173: Ethernet Phy Peripheral Ready (Prephy), Offset 0Xa30
Tiva TM4C1294NCPDT Microcontroller Register 173: Ethernet PHY Peripheral Ready (PREPHY), offset 0xA30 The PREPHY register indicates whether the Ethernet PHY module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCEPHY bit is changed from 0 to 1.
Page 514: Register 174: Controller Area Network Peripheral Ready (Prcan), Offset 0Xa34
CAN Module 0 Peripheral Ready Value Description CAN module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. CAN module 0 is ready for access. June 18, 2014 Texas Instruments-Production Data...
Page 515: Register 175: Analog-To-Digital Converter Peripheral Ready (Pradc), Offset 0Xa38
Tiva TM4C1294NCPDT Microcontroller Register 175: Analog-to-Digital Converter Peripheral Ready (PRADC), offset 0xA38 The PRADC register indicates whether the ADC modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCADC bit is changed from 0 to 1.
Page 516: Register 176: Analog Comparator Peripheral Ready (Pracmp), Offset 0Xa3C
Analog Comparator Module 0 Peripheral Ready Value Description The analog comparator module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. The analog comparator module is ready for access. June 18, 2014 Texas Instruments-Production Data...
Page 517: Register 177: Pulse Width Modulator Peripheral Ready (Prpwm), Offset 0Xa40
Tiva TM4C1294NCPDT Microcontroller Register 177: Pulse Width Modulator Peripheral Ready (PRPWM), offset 0xA40 The PRPWM register indicates whether the PWM modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCPWM bit is changed from 0 to 1.
Page 518: Register 178: Quadrature Encoder Interface Peripheral Ready (Prqei), Offset 0Xa44
QEI Module 0 Peripheral Ready Value Description QEI module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. QEI module 0 is ready for access. June 18, 2014 Texas Instruments-Production Data...
Page 519: Register 179: Eeprom Peripheral Ready (Preeprom), Offset 0Xa58
Tiva TM4C1294NCPDT Microcontroller Register 179: EEPROM Peripheral Ready (PREEPROM), offset 0xA58 The PREEPROM register indicates whether the EEPROM module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCEEPROM bit is changed from 0 to 1.
Page 520: Register 180: Crc Module Peripheral Ready (Prccm), Offset 0Xa74
CRC Peripheral Ready Value Description The CRC module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. The CRC module is ready for access. June 18, 2014 Texas Instruments-Production Data...
Page 521: Register 181: Ethernet Mac Peripheral Ready (Premac), Offset 0Xa9C
Tiva TM4C1294NCPDT Microcontroller Register 181: Ethernet MAC Peripheral Ready (PREMAC), offset 0xA9C The PREMAC register indicates whether the Ethernet module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCEMAC bit is changed from 0 to 1.
Page 522: Register 182: Unique Id 0 (Uniqueid0), Offset 0Xf20
Unique ID n (UNIQUEIDn) Base 0x400F.E000 Offset 0xF20 Type RO, reset - Type Reset Type Reset Bit/Field Name Type Reset Description 31:0 Unique ID The result of registers 0-3 concatenated defines the unique 128-bit device identifier. June 18, 2014 Texas Instruments-Production Data...
Page 523: Processor Support And Exception Module
Tiva TM4C1294NCPDT Microcontroller Processor Support and Exception Module This module is an AHB peripheral that handles system-level Cortex-M4 FPU exceptions. For functions with registers mapped into this aperture, if the function is not available on a device, then all writes to the associated registers are ignored and reads return zeros.
Page 524: Register 1: System Exception Raw Interrupt Status (Sysexcris), Offset 0X000
FPUFCRIS Floating-Point Underflow Exception Raw Interrupt Status Value Description No interrupt A floating-point underflow exception has occurred. This bit is cleared by writing a 1 to the UFCIC bit in the SYSEXCIC register. June 18, 2014 Texas Instruments-Production Data...
Page 525: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description FPIOCRIS Floating-Point Invalid Operation Raw Interrupt Status Value Description No interrupt A floating-point invalid operation exception has occurred. This bit is cleared by writing a 1 to the IOCIC bit in the SYSEXCIC register.
Page 526: Register 2: System Exception Interrupt Mask (Sysexcim), Offset 0X004
Floating-Point Underflow Exception Interrupt Mask Value Description The FPUFCRIS interrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when the FPUFCRIS bit in the SYSEXCRIS register is set. June 18, 2014 Texas Instruments-Production Data...
Page 527: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description FPIOCIM Floating-Point Invalid Operation Interrupt Mask Value Description The FPIOCRIS interrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when the FPIOCRIS bit in the SYSEXCRIS register is set.
Page 528: Register 3: System Exception Masked Interrupt Status (Sysexcmis), Offset 0X008
An interrupt has not occurred or is masked. An unmasked interrupt was signaled due to an underflow exception. This bit is cleared by writing a 1 to the FPUFCIC bit in the SYSEXCIC register. June 18, 2014 Texas Instruments-Production Data...
Page 529: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description FPIOCMIS Floating-Point Invalid Operation Masked Interrupt Status Value Description An interrupt has not occurred or is masked. An unmasked interrupt was signaled due to an invalid operation. This bit is cleared by writing a 1 to the FPIOCIC bit in the SYSEXCIC register.
Page 530: Register 4: System Exception Interrupt Clear (Sysexcic), Offset 0X00C
FPDZCMIS bit in the SYSEXCMIS register. FPIDCIC Floating-Point Input Denormal Exception Interrupt Clear Writing a 1 to this bit clears the FPIDCRIS bit in the SYSEXCRIS register and the FPIDCMIS bit in the SYSEXCMIS register. June 18, 2014 Texas Instruments-Production Data...
Page 531: Hibernation Module
Tiva TM4C1294NCPDT Microcontroller Hibernation Module The Hibernation Module manages removal and restoration of power to provide a means for reducing system power consumption. When the processor and peripherals are idle, power can be completely removed with only the Hibernation module remaining powered. Power can be restored based on an external signal or at a certain time using the built-in Real-Time Clock (RTC).
Page 532: Texas Instruments-Production Data
■ Clock source from an internal low frequency oscillator (HIB LFIOSC) or a 32.768-kHz external crystal or oscillator ■ Sixteen 32-bit words of battery-backed memory to save state during hibernation ■ Programmable interrupts for: – RTC match – External wake – Low battery June 18, 2014 Texas Instruments-Production Data...
Page 533: Block Diagram
Tiva TM4C1294NCPDT Microcontroller Block Diagram Figure 7-1. Hibernation Module Block Diagram Alternate Clock Clock Source for To GPIO Module for LPC System Clock HIBCTL.CLK32EN & HIBCTL.OSCSEL I/O Config. HIBCC. HIBCC. ALTCLK1EN SYSCLKEN HIBIO Frequency Oscillator XOSC0 32.786 kHz Oscillator Interrupts...
Page 534: Functional Description
>V . The Hibernation module also has an independent clock source to maintain a real-time clock (RTC) when the system clock is powered down. Hibernate mode can be entered through one of two ways: June 18, 2014 Texas Instruments-Production Data...
Page 535: Register Access Timing
Tiva TM4C1294NCPDT Microcontroller ■ The user initiates hibernation by setting the HIBREQ bit in the Hibernation Control (HIBCTL) register ■ Power is arbitrarily removed from V while a valid V is applied Once in hibernation, the module signals an external voltage regulator to turn the power back on when an external pin (WAKE, RST or a wake-enabled GPIO pin) is asserted or when the internal RTC reaches a certain value.
Page 536: Texas Instruments-Production Data
Figure 7-2 on page 537. When using an external clock source, the GNDX pin should be connected to digital ground. Note: In the figures below the parameters R and C have recommended values of 51Ω ±5% and 0.1µF ±5%, respectively. See “Hibernation Module” on page 1845 for more information. June 18, 2014 Texas Instruments-Production Data...
Page 537: Figure 7-2. Using A Crystal As The Hibernation Clock Source With A Single Battery Source
Tiva TM4C1294NCPDT Microcontroller Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source Tiva™ Microcontroller Regulator or Switch Input Voltage XOSC0 XOSC1 GNDX WAKE VBAT Open drain Battery external wake up circuit Note: Some devices may not supply the GNDX signal. If GNDX is absent, the crystal load capacitors can be tied to GND externally.
Page 538: System Implementation
Unused Signals” on page 1816. In this situation, the HIB bit in the Hibernation Run Mode Clock Gating Control (RCGCHIB) register must be cleared, disabling the system clock to the Hibernation module and Hibernation module registers are not accessible. June 18, 2014 Texas Instruments-Production Data...
Page 539: Battery Management
Tiva TM4C1294NCPDT Microcontroller 7.3.4 Battery Management Important: System-level factors may affect the accuracy of the low-battery detect circuit. The designer should consider battery type, discharge characteristics, and a test load during battery voltage measurements. The Hibernation module can be independently powered by a battery or an auxiliary power source using the VBAT pin.
Page 540: Texas Instruments-Production Data
0s in this mode. In addition, writes have no effect on these registers when the calendar function is enabled. The Hibernation Calendar n (HIBCALn), Hibernation Calendar Match (HIBCALMn) and Hibernation Calendar Load (HIBCALLDn) register fields are written or stored in hexadecimal. June 18, 2014 Texas Instruments-Production Data...
Page 541: Texas Instruments-Production Data
Tiva TM4C1294NCPDT Microcontroller When reading the Hibernation Calendar n (HIBCALn) registers, the status of the VALID bit in the HIBCAL0/1 register must be checked to ensure the registers are in sync before reading. The calendar function will keep track of the following: ■...
Page 542: Tamper
Figure 7-7 on page 542 shows the Tamper block diagram. Figure 7-7. Tamper Block Diagram Tamper Detect Control Tamper Event NMI and Filter HIBTPCTL BBRAM Clear TMPR[3:0] HIBTPIO HIBTPSTAT HIB Wake HIBTPCTL.TPEN Tamper Log XOSC Fail XOSC0 Detector HIBTPLOG HIBTPCTL.TPEN June 18, 2014 Texas Instruments-Production Data...
Page 543: Figure 7-8. Tamper Pad With Glitch Filtering
Tiva TM4C1294NCPDT Microcontroller 7.3.6.2 Functional Description The Tamper module provides mechanisms to detect, respond, and log system tamper events. A tamper event is detected by state transitions on up to four GPIOs. The module may respond to a tamper event by clearing all or part of the hibernate module memory, generating a tamper event signal to the System Control module.
Page 544: Texas Instruments-Production Data
LFIOSC. The NMI interrupt handler may access the module immediately, but should read the HIBTPLOGn registers before issuing a tamper clear in the HIBTPCTL register. Note: The HIBTPLOG7 register is sticky and is only cleared by a Hibernate module reset. June 18, 2014 Texas Instruments-Production Data...
Page 545: Battery-Backed Memory
Tiva TM4C1294NCPDT Microcontroller Tamper I/O Control Up to four tamper I/Os are available. These signals are individually enabled and the detection level can be configured per pin. Enabling the tamper IO will override all settings made in the GPIO module.
Page 546: Power Control Using Vdd3On Mode
Mask (HIBIM) register. Note: If an external WAKE signal is asserted, the application is responsible for clearing the signal source once the EXTWEN bit has been registered in the Hibernation Raw Interrupt Status (HIBRIS) register. June 18, 2014 Texas Instruments-Production Data...
Page 547: Arbitrary Power Removal
Tiva TM4C1294NCPDT Microcontroller To use the RST pin as a wake source, the WURSTEN bit must be set in the Hibernate I/O Configuration (HIBIO) register and the WUUNLK bit must be set in the same register. To enable any of the assigned GPIO pins as a wake source, the WUUNLK bit must be set in the HIBIO register and the wake configuration must be programmed through the GPIOWAKEPEN and GPIOWAKELVL registers in the GPIO module.
Page 548: Initialization And Configuration
2. Write 0x40 to the HIBCTL register at offset 0x10 to enable the oscillator input. 3. Wait until the WC interrupt in the HIBMIS register has been triggered before performing any other operations with the Hibernation module. June 18, 2014 Texas Instruments-Production Data...
Page 549: Rtc Match Functionality (No Hibernation)
Tiva TM4C1294NCPDT Microcontroller If a 32.768-kHz single-ended oscillator is used as the Hibernation module clock source, then perform the following steps: 1. Write 0x0000.0010 to the HIBIM register to enable the WC interrupt. 2. Write 0x0001.0040 to the HIBCTL register at offset 0x10 to enable the oscillator input and bypass the on-chip oscillator.
Page 550: External Wake-Up From Hibernation
GPIOWAKEPEN and GPIOWAKELVL register will be ignored. 5. Clear any pending interrupts by writing a 1 to the PADIOWK bit in the HIBIC register. June 18, 2014 Texas Instruments-Production Data...
Page 551: Rtc Or External Wake-Up From Hibernation
Tiva TM4C1294NCPDT Microcontroller 6. The hibernation sequence may be initiated by writing 0x4000.0152 to the HIBCTL register. Note for Port M external wake, the user must enable VDD3ON mode and set the RETCLR bit in the HIBCTL register. 7.4.5 RTC or External Wake-Up from Hibernation 1.
Page 552: Table 7-3. Hibernation Module Register Map
0x018 HIBRIS 0x0000.0000 Hibernation Raw Interrupt Status 0x01C HIBMIS 0x0000.0000 Hibernation Masked Interrupt Status 0x020 HIBIC RW1C 0x0000.0000 Hibernation Interrupt Clear 0x024 HIBRTCT 0x0000.7FFF Hibernation RTC Trim 0x028 HIBRTCSS 0x0000.0000 Hibernation RTC Sub Seconds June 18, 2014 Texas Instruments-Production Data...
Page 553: Register Descriptions
Tiva TM4C1294NCPDT Microcontroller Table 7-3. Hibernation Module Register Map (continued) Offset Name Type Reset Description page 0x02C HIBIO 0x8000.0000 Hibernation IO Configuration 0x030- HIBDATA Hibernation Data 0x06F 0x300 HIBCALCTL 0x0000.0000 Hibernation Calendar Control 0x310 HIBCAL0 0x0000.0000 Hibernation Calendar 0 0x314 HIBCAL1 0x0000.0000...
Page 554: Register 1: Hibernation Rtc Counter (Hibrtcc), Offset 0X000
31:0 RTCC 0x0000.0000 RTC Counter A read returns the 32-bit counter value, which represents the seconds elapsed since the RTC was enabled. This register is read-only. To change the value, use the HIBRTCLD register. June 18, 2014 Texas Instruments-Production Data...
Page 555: Register 2: Hibernation Rtc Match 0 (Hibrtcm0), Offset 0X004
Tiva TM4C1294NCPDT Microcontroller Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 This register is the 32-bit seconds match register for the RTC counter. The 15-bit sub second match value is stored in the reading the RTCSSC field in the HIBRTCSS register and can be used in conjunction with this register for a more precise time match.
Page 556: Register 3: Hibernation Rtc Load (Hibrtcld), Offset 0X00C
RTCLD Type Reset RTCLD Type Reset Bit/Field Name Type Reset Description 31:0 RTCLD 0x0000.0000 RTC Load A write loads the current value into the RTC counter (RTCC). A read returns the 32-bit load value. June 18, 2014 Texas Instruments-Production Data...
Page 557: Register 4: Hibernation Control (Hibctl), Offset 0X010
Tiva TM4C1294NCPDT Microcontroller Register 4: Hibernation Control (HIBCTL), offset 0x010 This register is the control register for the Hibernation module. This register must be written last before a hibernate event is issued. Writes to other registers after the HIBREQ bit is set are not guaranteed to complete before hibernation is entered.
Page 558 The internal 32.768-kHz Hibernation oscillator is enabled. This bit should be cleared when using an external 32.768-kHz crystal. The internal 32.768-kHz Hibernation oscillator is disabled and powered down. This bit should be set when using a single-ended oscillator attached to XOSC0. June 18, 2014 Texas Instruments-Production Data...
Page 559 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14:13...
Page 560 Run, Sleep, or Deep Sleep mode regardless of whether the PINWEN bit is 0x0 or 0x1. The interrupt may be forwarded to the processor by setting the EXTW bit in the HIBIM register. June 18, 2014 Texas Instruments-Production Data...
Page 561 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description RTCWEN RTC Wake-up Enable Value Description An RTC match event has no effect on hibernation. An RTC match event (the value the HIBRTCC register matches the value of the HIBRTCM0 register and the value...
Page 562: Register 5: Hibernation Interrupt Mask (Hibim), Offset 0X014
Reset Pad I/O Wake-Up Interrupt Mask Value Description The RSTWK interrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when the RSTWK bit in the HIBRIS register is set. June 18, 2014 Texas Instruments-Production Data...
Page 563 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description PADIOWK Pad I/O Wake-Up Interrupt Mask Value Description The PADIOWK interrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when the PADIOWK bit in the HIBRIS register is set.
Page 564: Register 6: Hibernation Raw Interrupt Status (Hibris), Offset 0X018
An interrupt is sent to the interrupt controller because one of the wake-enabled GPIO pins or the external RESET pin has been asserted. June 18, 2014 Texas Instruments-Production Data...
Page 565 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description Write Complete/Capable Raw Interrupt Status Value Description The WRC bit in the HIBCTL has not been set. The WRC bit in the HIBCTL has been set. This bit is cleared by writing a 1 to the WC bit in the HIBIC register.
Page 566: Register 7: Hibernation Masked Interrupt Status (Hibmis), Offset 0X01C
PADIOWK Pad I/O Wake-Up Interrupt Mask Value Description An external GPIO or reset interrupt has not occurred or is masked. An unmasked interrupt was signaled due to a wake-enabled GPIO or RESET pin assertion. June 18, 2014 Texas Instruments-Production Data...
Page 567 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description Write Complete/Capable Masked Interrupt Status Value Description The WRC bit has not been set or the interrupt is masked. An unmasked interrupt was signaled due to the WRC bit being set. This bit is cleared by writing a 1 to the WC bit in the HIBIC register.
Page 568: Register 8: Hibernation Interrupt Clear (Hibic), Offset 0X020
Reads return the raw interrupt status. EXTW RW1C External Wake-Up Interrupt Clear Writing a 1 to this bit clears the EXTW bit in the HIBRIS and HIBMIS registers. Reads return the raw interrupt status. June 18, 2014 Texas Instruments-Production Data...
Page 569 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description LOWBAT RW1C Low Battery Voltage Interrupt Clear Writing a 1 to this bit clears the LOWBAT bit in the HIBRIS and HIBMIS registers. Reads return the raw interrupt status. reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 570: Register 9: Hibernation Rtc Trim (Hibrtct), Offset 0X024
Compensation can be adjusted by software by moving the default value of 0x7FFF up or down. Moving the value up slows down the RTC and moving the value down speeds up the RTC. June 18, 2014 Texas Instruments-Production Data...
Page 571: Register 10: Hibernation Rtc Sub Seconds (Hibrtcss), Offset 0X028
Tiva TM4C1294NCPDT Microcontroller Register 10: Hibernation RTC Sub Seconds (HIBRTCSS), offset 0x028 This register contains the RTC sub seconds counter and match values. The RTC value can be read by first reading the HIBRTCC register, reading the RTCSSC field in the HIBRTCSS register, and then rereading the HIBRTCC register.
Page 572: Register 11: Hibernation Io Configuration (Hibio), Offset 0X02C
The RST signal is enabled as a wake source. reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 573 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description WUUNLK I/O Wake Pad Configuration Enable Value Description The I/O WAKE configuration set by the WURSTEN bit or in the GPIO module registers GPIOWAKEPEN and GPIOWAKELVL is ignored. Implement the I/O WAKE configuration, level and enables for the external RST pin and/or GPIO wake-enabled pins.
Page 574: Register 12: Hibernation Data (Hibdata), Offset 0X030-0X06F
V is reapplied. Hibernation Data (HIBDATA) Base 0x400F.C000 Offset 0x030-0x06F Type RW, reset - Type Reset Type Reset Bit/Field Name Type Reset Description 31:0 Hibernation Module NV Data June 18, 2014 Texas Instruments-Production Data...
Page 575: Register 13: Hibernation Calendar Control (Hibcalctl), Offset 0X300
Tiva TM4C1294NCPDT Microcontroller Register 13: Hibernation Calendar Control (HIBCALCTL), offset 0x300 The Hibernate calendar is enabled by setting the CALEN bit in the HIBCALCTL register. If the BCD bit is set, the fields are reported in BCD format. Hibernation Calendar Control (HIBCALCTL) Base 0x400F.C000...
Page 576: Register 14: Hibernation Calendar 0 (Hibcal0), Offset 0X310
0x0 representing 12AM or 12 PM. 15:14 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 577 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 13:8 Minutes This field holds the minute information in hexadecimal. Bits 13:8 correspond to hex values from 0x0 to 0x3b (0 to 59 minutes). reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 578: Register 15: Hibernation Calendar 1 (Hibcal1), Offset 0X314
Bits 11:8 correspond to hex values from 0x1 to 0xC (1 to 12 months). reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 579 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description Day of Month This field holds the day of the month value in hexadecimal. Bits 4:0 correspond to hex values from 0x1 to 1F (1 to 31 days). The value 0 is used to show an ignore match.
Page 580: Register 16: Hibernation Calendar Load 0 (Hibcalld0), Offset 0X320
Bits 13:8 correspond to hex values from 0x0 to 0x3B (0 to 59 minutes). reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 581 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description Seconds This field holds the seconds value in hexadecimal. Bits 5:0 correspond to hex values from 0x0 to 0x3B (0 to 59 seconds). June 18, 2014 Texas Instruments-Production Data...
Page 582: Register 17: Hibernation Calendar Load (Hibcalld1), Offset 0X324
The day of the month value is written in this field in hexadecimal. Bits 4:0 correspond to hex values from 0x1 to 1F (1 to 31 days). The encoding 0x0 is reserved for the ignore match function. June 18, 2014 Texas Instruments-Production Data...
Page 583: Register 18: Hibernation Calendar Match 0 (Hibcalm0), Offset 0X330
Tiva TM4C1294NCPDT Microcontroller Register 18: Hibernation Calendar Match 0 (HIBCALM0), offset 0x330 The Hibernation Calendar Match 0 (HIBCALM0) register is used when the CALEN bit is set in the HIBCALCTL register. This register is loaded with desired match values for calendar mode. Once the HIBCAL0/1 register values equal the HIBCALM0/1 register values, the RTCALT0 bit is set in the HIBRIS register.
Page 584 This field holds the match value for seconds. The value is represented in hexadecimal. Bits 5:0 correspond to hex values from 0x0 to 0x3b (0 to 59 seconds). To ignore the hours match, write this field to all 1s. June 18, 2014 Texas Instruments-Production Data...
Page 585: Register 19: Hibernation Calendar Match 1 (Hibcalm1), Offset 0X334
Tiva TM4C1294NCPDT Microcontroller Register 19: Hibernation Calendar Match 1 (HIBCALM1), offset 0x334 The Hibernation Calendar Match 1 (HIBCALM1) register is used when the CALEN bit is set in the HIBCALCTL register. This register is loaded with desired match values for calendar mode. Once the HIBCAL0/1 register values equal the HIBCALM0/1 register values, the RTCALT0 bit is set in the HIBRIS register.
Page 586: Register 20: Hibernation Lock (Hiblock), Offset 0X360
Base 0x400F.C000 Offset 0x360 Type RW, reset 0x0000.0000 HIBLOCK Type Reset HIBLOCK Type Reset Bit/Field Name Type Reset Description 31:0 HIBLOCK 0x0000 HIbernate Lock A write of 0xA335.9554 unlocks the HIBRCTL and Tamper registers. June 18, 2014 Texas Instruments-Production Data...
Page 587: Register 21: Hib Tamper Control (Hibtpctl), Offset 0X400
Tiva TM4C1294NCPDT Microcontroller Register 21: HIB Tamper Control (HIBTPCTL), offset 0x400 The Tamper Control (HIBTPCTL) register provides control of the module. Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module registers are on the Hibernation module clock domain and have special timing requirements.
Page 588 Tamper module disabled. Tamper module Enabled. Note: Once tamper is enabled, the following HIBCTL register bits are locked and cannot be modified: ■ OSCSEL ■ OSCDRV ■ OSCBYP ■ VDD3ON ■ CLK32EN ■ RTCEN June 18, 2014 Texas Instruments-Production Data...
Page 589: Register 22: Hib Tamper Status (Hibtpstat), Offset 0X404
Tiva TM4C1294NCPDT Microcontroller Register 22: HIB Tamper Status (HIBTPSTAT), offset 0x404 The HIB Tamper Status (HIBTPCTL) register provides status of the module. Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module registers are on the Hibernation module clock domain and have special timing requirements.
Page 590 Hibernation Module Bit/Field Name Type Reset Description XOSCFAIL RW1C External Oscillator Failure Write a 1 to this bit to clear it. Value Description External oscillator is valid. External oscillator has failed June 18, 2014 Texas Instruments-Production Data...
Page 591: Register 23: Hib Tamper I/O Control (Hibtpio), Offset 0X410
Tiva TM4C1294NCPDT Microcontroller Register 23: HIB Tamper I/O Control (HIBTPIO), offset 0x410 The HIB Tamper I/O Control (HIBTPIO) register provides control of the Tamper I/O. Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module registers are on the Hibernation module clock domain and have special timing requirements.
Page 592 Detect enabled 15:12 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 593 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description GFLTR1 TMPR1 Glitch Filtering Value Description A trigger match level is ignored until the TMPR1 signal is stable for two hibernate clocks. A trigger match level is ignored until the TMPR1 signal is stable for 3,071 Hibernate Clocks (93.7ms using 32.768 kHz).
Page 594 Hibernation Module Bit/Field Name Type Reset Description LEV0 TMPR0 Trigger Level Value Description Trigger on level low Trigger on level high TMPR0 Enable Value Description Detect disabled Detect enabled June 18, 2014 Texas Instruments-Production Data...
Page 595: Register 24: Hib Tamper Log 0 (Hibtplog0), Offset 0X4E0
Tiva TM4C1294NCPDT Microcontroller Register 24: HIB Tamper Log 0 (HIBTPLOG0), offset 0x4E0 Register 25: HIB Tamper Log 2 (HIBTPLOG2), offset 0x4E8 Register 26: HIB Tamper Log 4 (HIBTPLOG4), offset 0x4F0 Register 27: HIB Tamper Log 6 (HIBTPLOG6), offset 0x4F8 The HIB Tamper Log (HIBTPLOG) even registers capture the time information during a tamper event.
Page 596: Register 28: Hib Tamper Log 1 (Hibtplog1), Offset 0X4E4
TRIG3 Status of TMPR[3] Trigger Value Description Default A tamper event has been detected on TMPR[3] TRIG2 Status of TMPR[2] Trigger Value Description Default A tamper event has been detected on TMPR[2] June 18, 2014 Texas Instruments-Production Data...
Page 597 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description TRIG1 Status of TMPR[1] Trigger Value Description Default A tamper event has been detected on TMPR[1] TRIG0 Status of TMPR[0] Trigger Value Description Default A tamper event has been detected on TMPR[0]...
Page 598: Register 32: Hibernation Peripheral Properties (Hibpp) , Offset 0Xfc0
TAMPER Tamper Pin Presence Value Description Tamper module is not present. Tamper module is present. WAKENC Wake Pin Presence Value Description WAKE pin is present. WAKE pin is not part of the package pinout. June 18, 2014 Texas Instruments-Production Data...
Page 599: Register 33: Hibernation Clock Control (Hibcc), Offset 0Xfc8
Tiva TM4C1294NCPDT Microcontroller Register 33: Hibernation Clock Control (HIBCC), offset 0xFC8 This register enables alternate clock sources. Note: This register is in the system clock domain. Writes to this register do not require waiting for the WRC bit of the HIBCTL register to be set.
Page 600: Internal Memory
Internal Memory Internal Memory The TM4C1294NCPDT microcontroller comes with 256 KB of bit-banded SRAM, internal ROM, 1024 KB of Flash memory, and 6KB of EEPROM. The TM4C1294NCPDT microcontroller provides 1024 KB of on-chip Flash memory. The Flash memory is configured as four banks of 16K x 128 bits (4 * 256 KB total) which are two-way interleaved.
Page 601: Figure 8-1. Internal Memory Block Diagram
Tiva TM4C1294NCPDT Microcontroller Figure 8-1. Internal Memory Block Diagram EEPROM Control EESIZE EEBLOCK EEOFFSET EERDWR EEPROM Array EEDWRINC EEDONE EESUPP EEUNLOCK EEPROT EEPASSn EEINT EEHIDE EEDBGME EEPROMPP ROMSWMAP Flash Control FCRIS ICODE FCIM CORTEX M4 FCMISC DCODE FSIZE FLASHPP FLASHCONF...
Page 602: Functional Description
■ Cyclic Redundancy Check (CRC) error detection functionality The boot loader is used as an initial program loader (when the Flash location 0x0000.0004, the reset vector location is all 1s (that is, erased state of Flash)) as well as an application-initiated June 18, 2014 Texas Instruments-Production Data...
Page 603 Tiva TM4C1294NCPDT Microcontroller firmware upgrade mechanism (by calling back to the boot loader). The Peripheral Driver Library APIs in ROM can be called by applications, reducing Flash memory requirements and freeing the Flash memory to be used for other purposes (such as additional features in the application). Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the U.S.
Page 604: Flash Memory
SPMU363) for more information on CRC. 8.2.3 Flash Memory The Flash memory is configured in groups of four banks four banks of 16K x 128 bits (4 * 256 KB total) which are two-way interleaved as shown below. June 18, 2014 Texas Instruments-Production Data...
Page 605: Figure 8-2. Flash Memory Configuration
Tiva TM4C1294NCPDT Microcontroller Figure 8-2. Flash Memory Configuration 0x0F.FFFC 0x0F.FFF8 0x0F.FFF4 0x0F.FFF0 0x0F.FFEC 0x0F.FFE8 0x0F.FFE4 0x0F.FFE0 8 KB Sector31-1 Bank 3 8 KB Sector31-1 Bank 2 512 KB High Region 0x08.401C 0x08.4018 0x08.4014 0x08.4010 0x08.400C 0x08.4008 0x08.4004 0x08.4000 0x08.3FFC 0x08.3FF8 0x08.3FF4...
Page 606: Figure 8-3. Single 256-Bit Prefetch Buffer Set
If there is a hit, the target word is immediately sent to the CPU with no wait states. If there is a miss, then the prefetch buffer is invalidated and the miss is processed as a 256-bit read from the flash June 18, 2014 Texas Instruments-Production Data...
Page 607: Figure 8-5. Single Cycle Access, 0 Wait States
Tiva TM4C1294NCPDT Microcontroller subsystem to fill the next, least-recently used prefetch buffer. Two memory banks are read in parallel to retrieve 256-bits worth of data. If an auto-fill has been started and a miss occurs, the auto-fill completes before the miss is processed.
Page 608: Figure 8-6. Prefetch Fills From Flash
In addition to the data, the boot loader in both the lower and upper banks must be mirrored June 18, 2014 Texas Instruments-Production Data...
Page 609: Figure 8-7. Mirror Mode Function
Tiva TM4C1294NCPDT Microcontroller while programming the flash contents. If data needs to be recovered, a hot swap can be done by setting the FMME bit in the FLASHCONF register to ensure the flash banks are idle during the swap. The prefetch buffers must be invalidated during the execution of a hot swap. Next, the address translation logic decodes up to 512 KB from the upper banks to the lower banks.
Page 610: Table 8-2. Flash Memory Protection Policy Combinations
PC-relative memory address. The execution of the LDR instruction generates a read transaction across the Cortex-M3's DCode bus, which is subject to the execute-only protection mechanism. If the accessed block is marked as execute only, the transaction June 18, 2014 Texas Instruments-Production Data...
Page 611 Tiva TM4C1294NCPDT Microcontroller is blocked, and the processor is prevented from loading the constant data and, therefore, inhibiting correct execution. Therefore, using execute-only protection requires that literal data be handled differently. There are three ways to address this: 1. Use a compiler that allows literal data to be collected into a separate section that is put into one or more read-enabled flash blocks.
Page 612 ■ All Flash operations are completed before entering sleep or deep sleep. To program a 32-bit word 1. Write source data to the FMD register. 2. Write the target address to the FMA register. June 18, 2014 Texas Instruments-Production Data...
Page 613 Tiva TM4C1294NCPDT Microcontroller 3. Write the Flash memory write key and the WRITE bit (a value of 0xA442.0001) to the FMC register. The write key may be 0xA442 or the value programmed into the FLPEKEY register depending on the KEY value in the BOOTCFG register. See page 674 and page 640 for more information.
Page 614: Table 8-3. User-Programmable Flash Memory Resident Registers
Data Source FMPRE0 0x0000.0000 FMPRE0 FMPRE1 0x0000.0002 FMPRE1 FMPRE2 0x0000.0004 FMPRE2 FMPRE3 0x0000.0006 FMPRE3 FMPRE4 0x0000.0008 FMPRE4 FMPRE5 0x0000.000A FMPRE5 FMPRE6 0x0000.000C FMPRE6 FMPRE7 0x0000.000E FMPRE7 FMPRE8 0x0000.0010 FMPRE8 FMPRE9 0x0000.0012 FMPRE9 FMPRE10 0x0000.0014 FMPRE10 June 18, 2014 Texas Instruments-Production Data...
Page 615: Eeprom
BOOTCFG 0x7510.0000 8.2.4 EEPROM The TM4C1294NCPDT microcontroller includes an EEPROM with the following features: ■ 6Kbytes of memory accessible as 1536 32-bit words ■ 96 blocks of 16 words (64 bytes) each ■ Built-in wear leveling ■ Access protection per block ■...
Page 616 Depending on the CPU frequency, the application must program the EEPROM Clock High Time (EBCHT), EEPROM Bank Clock Edge (EBCE) and the EEPROM Wait States (EWS) in the Memory Timing Parameter Register 0 for Main Flash and EEPROM (MEMTIM0) register at System Control Module offset 0x0C0. June 18, 2014 Texas Instruments-Production Data...
Page 617: Table 8-4. Memtim0 Register Configuration Versus Frequency
Tiva TM4C1294NCPDT Microcontroller Table 8-4. MEMTIM0 Register Configuration versus Frequency CPU Frequency range (f) Time Period Range (t) in ns EEPROM Bank Clock EEPROM Bank EEPROM Wait in MHz High Time (EBCHT) Clock Edge States (EWS) (EBCE) 62.5 16 < f ≤ 40 62.5 >...
Page 618 The original block is then erased. Finally, the copy buffer contents are copied back to the block. The EEPROM module includes functionality to prevent data corruption due to power-loss or a brown-out event during programming or erase operations. These conditions prevent corruption of June 18, 2014 Texas Instruments-Production Data...
Page 619 Tiva TM4C1294NCPDT Microcontroller non-targeted memory areas but cannot guarantee that the operation is completed successfully. Refer to “EEPROM” on page 1848 for important timing information on EEPROM protection. The EEPROM mechanism properly tracks all state information to provide complete safety and protection.
Page 620 1. Insert delay (6 cycles plus function call overhead). 2. Poll the WORKING bit in the EEPROM Done Status (EEDONE) register until it is clear, indicating that the EEPROM has completed its power-on initialization. When WORKING=0, continue. June 18, 2014 Texas Instruments-Production Data...
Page 621: Bus Matrix Memory Accesses
Tiva TM4C1294NCPDT Microcontroller 3. Read the PRETRY and ERETRY bits in the EEPROM Support Control and Status (EESUPP) register. If either of the bits are set, return an error, else continue. 4. Reset the EEPROM module using the EEPROM Software Reset (SREEPROM) register at offset 0x558 in the System Control register space.
Page 622: Table 8-6. Flash Register Map
EEPROM Done Status 0x01C EESUPP EEPROM Support Control and Status 0x020 EEUNLOCK EEPROM Unlock 0x030 EEPROT 0x0000.0000 EEPROM Protection 0x034 EEPASS0 EEPROM Password 0x038 EEPASS1 EEPROM Password 0x03C EEPASS2 EEPROM Password 0x040 EEINT 0x0000.0000 EEPROM Interrupt June 18, 2014 Texas Instruments-Production Data...
Page 623 Tiva TM4C1294NCPDT Microcontroller Table 8-6. Flash Register Map (continued) Offset Name Type Reset Description page 0x050 EEHIDE0 0x0000.0000 EEPROM Block Hide 0 0x054 EEHIDE1 0x0000.0000 EEPROM Block Hide 1 0x058 EEHIDE2 0x0000.0000 EEPROM Block Hide 2 0x080 EEDBGME 0x0000.0000 EEPROM Debug Mass Erase...
Page 624: Internal Memory Register Descriptions (Internal Memory Control Offset)
Internal Memory Register Descriptions (Internal Memory Control Offset) This section lists and describes the memory control registers, in numerical order by address offset. Registers in this section are relative to the memory control base address of 0x400F.D000. June 18, 2014 Texas Instruments-Production Data...
Page 625: Register 1: Flash Memory Address (Fma), Offset 0X000
Tiva TM4C1294NCPDT Microcontroller Register 1: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations for flash space that is not user configurable (that is, FMPREn, FMPPEn, USER_REGn, BOOTCFG), this register contains a 16 KB-aligned CPU byte address and specifies which block is erased.
Page 626: Register 2: Flash Memory Data (Fmd), Offset 0X004
Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type RW, reset 0x0000.0000 DATA Type Reset DATA Type Reset Bit/Field Name Type Reset Description 31:0 DATA 0x0000.0000 Data Value Data value for write operation. June 18, 2014 Texas Instruments-Production Data...
Page 627: Register 3: Flash Memory Control (Fmc), Offset 0X008
Tiva TM4C1294NCPDT Microcontroller Register 3: Flash Memory Control (FMC), offset 0x008 When this register is written, the Flash memory controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 625). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 626) is written to the specified address.
Page 628 Set this bit to erase the Flash memory page specified by the contents of the FMA register. When read, a 1 indicates that the previous page erase access is not complete. For information on erase time, see “Flash Memory” on page 1847. June 18, 2014 Texas Instruments-Production Data...
Page 629 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description WRITE Write a Word into Flash Memory This bit is used to write a word into Flash memory and to monitor the progress of that process. Value Description A write of 0 has no effect on the state of this bit.
Page 630: Register 4: Flash Controller Raw Interrupt Status (Fcris), Offset 0X00C
If this error occurs when using the Flash write buffer, software must inspect the affected words to determine where the error occurred. This bit is cleared by writing a 1 to the ERMISC bit in the FCMISC register. June 18, 2014 Texas Instruments-Production Data...
Page 631 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description INVDRIS Invalid Data Raw Interrupt Status Value Description An interrupt has not occurred. An interrupt is pending because a bit that was previously programmed as a 0 is now being requested to be programmed as a 1.
Page 632 This status is sent to the interrupt controller when the AMASK bit in the FCIM register is set. This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register. June 18, 2014 Texas Instruments-Production Data...
Page 633: Register 5: Flash Controller Interrupt Mask (Fcim), Offset 0X010
Tiva TM4C1294NCPDT Microcontroller Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the Flash memory controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type RW, reset 0x0000.0000 reserved Type...
Page 634 This bit controls the reporting of the access raw interrupt status to the interrupt controller. Value Description The ARIS interrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when the ARIS bit is set. June 18, 2014 Texas Instruments-Production Data...
Page 635: Register 6: Flash Controller Masked Interrupt Status And Clear (Fcmisc), Offset 0X014
Tiva TM4C1294NCPDT Microcontroller Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting.
Page 636 When read, a 1 indicates that an unmasked interrupt was signaled because a programming cycle completed. Writing a 1 to this bit clears PMISC and also the PRIS bit in the FCRIS register (see page 630). June 18, 2014 Texas Instruments-Production Data...
Page 637 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description AMISC RW1C Access Masked Interrupt Status and Clear Value Description When read, a 0 indicates that no improper accesses have occurred. A write of 0 has no effect on the state of this bit.
Page 638: Register 7: Flash Memory Control 2 (Fmc2), Offset 0X020
FMA register. When read, a 1 indicates that the previous buffered Flash memory write access is not complete. For information on programming time, see “Flash Memory” on page 1847. June 18, 2014 Texas Instruments-Production Data...
Page 639: Register 8: Flash Write Buffer Valid (Fwbval), Offset 0X030
Tiva TM4C1294NCPDT Microcontroller Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 This register provides a bitwise status of which FWBn registers have been written by the processor since the last write of the Flash memory write buffer. The entries with a 1 are written on the next write of the Flash memory write buffer.
Page 640: Register 9: Flash Program/Erase Key (Flpekey), Offset 0X03C
15:0 PEKEY 0xFFFF Key Value When a value other than all 1s or all 0s, this 16-bit value is used as the "match" for the upper 16-bits of the register FMC and FMC2 keys. June 18, 2014 Texas Instruments-Production Data...
Page 641: Register 10: Flash Write Buffer N (Fwbn), Offset 0X100 - 0X17C
Tiva TM4C1294NCPDT Microcontroller Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C These 32 registers hold the contents of the data to be written into the Flash memory on a buffered Flash memory write operation. The offset selects one of the 32-bit registers. Only FWBn registers...
Page 642: Register 11: Flash Peripheral Properties (Flashpp), Offset 0Xfc0
FLASHDMAST and FLASHDMASZ registers 27:23 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 643 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 22:19 EESS EEPROM Sector Size of the physical bank Value Description 1 KB 2 KB 4 KB 8 KB 0x4-0x7 reserved 18:16 MAINSS Flash Sector Size of the physical bank Value Description...
Page 644: Register 12: Sram Size (Ssize), Offset 0Xfc4
15:0 SIZE 0x3FF SRAM Size Indicates the size of the on-chip SRAM. Value Description 0x03FF 256 KB of SRAM June 18, 2014 Texas Instruments-Production Data...
Page 645: Register 13: Flash Configuration Register (Flashconf), Offset 0Xfc8
Tiva TM4C1294NCPDT Microcontroller Register 13: Flash Configuration Register (FLASHCONF), offset 0xFC8 The FLASHCONF register allows the user to enable or disable various properties of the Flash. The force bits, FBFON and FBFOFF, can be used to test code performance and execution by turning the prefetch buffers on and subsequently forcing them off.
Page 646 Force prefetch buffers to be disabled. 15:0 reserved 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 647: Register 14: Rom Third-Party Software (Romswmap), Offset 0Xfcc
Tiva TM4C1294NCPDT Microcontroller Register 14: ROM Third-Party Software (ROMSWMAP), offset 0xFCC This register indicates the presence of third-party software in the on-chip ROM. ROMSWMAP enables the ROM apertures that are available. ROM Third-Party Software (ROMSWMAP) Base 0x400F.D000 Offset 0xFCC Type RO, reset 0x0000.0000...
Page 648 Software region not available to the core. Region available to core 0x2-0x3 reserved SW0EN ROM SW Region 0 Availability Value Description Software region not available to the core. Region available to core 0x2-0x3 reserved June 18, 2014 Texas Instruments-Production Data...
Page 649: Register 15: Flash Dma Address Size (Flashdmasz), Offset 0Xfd0
Tiva TM4C1294NCPDT Microcontroller Register 15: Flash DMA Address Size (FLASHDMASZ), offset 0xFD0 The FLASHDMASZ register contains the area of Flash that the µDMA can access. Note: The µDMA can access Flash in Run Mode only (not available in low power modes).
Page 650: Register 16: Flash Dma Starting Address (Flashdmast), Offset 0Xfd4
EEPROM module registers are accessed. In addition, after enabling or resetting the EEPROM module, software must wait until the WORKING bit in the EEDONE register is clear before accessing any EEPROM registers. June 18, 2014 Texas Instruments-Production Data...
Page 651: Register 17: Eeprom Size Information (Eesize), Offset 0X000
Tiva TM4C1294NCPDT Microcontroller Register 17: EEPROM Size Information (EESIZE), offset 0x000 The EESIZE register indicates the number of 16-word blocks and 32-bit words in the EEPROM. EEPROM Size Information (EESIZE) Base 0x400A.F000 Offset 0x000 Type RO, reset 0x0060.0600 reserved BLKCNT...
Page 652: Register 18: Eeprom Current Block (Eeblock), Offset 0X004
EESIZE register. Attempts to write this field larger than the maximum number of blocks or to a locked block causes this field to be configured to 0. June 18, 2014 Texas Instruments-Production Data...
Page 653: Register 19: Eeprom Current Offset (Eeoffset), Offset 0X008
Tiva TM4C1294NCPDT Microcontroller Register 19: EEPROM Current Offset (EEOFFSET), offset 0x008 The EEOFFSET register is used to select the EEPROM word to read or write within the block selected by the EEBLOCK register. The value is a word offset into the block. Because accesses to the EERDWRINC register change the offset, software can read the contents of this register to determine the current offset.
Page 654: Register 20: Eeprom Read-Write (Eerdwr), Offset 0X010
If protection and access rules do not permit reads, all 1s are returned. If protection and access rules do not permit writes, the write fails and the EEDONE register indicates failure. June 18, 2014 Texas Instruments-Production Data...
Page 655: Register 21: Eeprom Read-Write With Increment (Eerdwrinc), Offset 0X014
Tiva TM4C1294NCPDT Microcontroller Register 21: EEPROM Read-Write with Increment (EERDWRINC), offset 0x014 The EERDWRINC register is used to read or write the EEPROM word at the address pointed to by the EEBLOCK and EEOFFSET registers, and then increment the OFFSET field in the EEOFFSET register.
Page 656: Register 22: Eeprom Done Status (Eedone), Offset 0X018
WRBUSY Write Busy Value Description No error An attempt to access the EEPROM was made while a write was in progress. June 18, 2014 Texas Instruments-Production Data...
Page 657 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description NOPERM Write Without Permission Value Description No error An attempt was made to write without permission. This error can result because the block is locked, the write violates the programmed access protection, or when an attempt is made to write a password when the password has already been written.
Page 658: Register 23: Eeprom Support Control And Status (Eesupp), Offset 0X01C
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 659: Register 24: Eeprom Unlock (Eeunlock), Offset 0X020
Tiva TM4C1294NCPDT Microcontroller Register 24: EEPROM Unlock (EEUNLOCK), offset 0x020 The EEUNLOCK register can be used to unlock the whole EEPROM or a single block using a password. Unlocking is only required if a password is registered using the EEPASSn registers for the block that is selected by the EEBLOCK register.
Page 660: Register 25: Eeprom Protection (Eeprot), Offset 0X030
Only supervisor code may access this block of the EEPROM. μDMA and Debug are also prevented from accessing the EEPROM. If this bit is set for block 0, then the whole EEPROM may only be accessed by supervisor code. June 18, 2014 Texas Instruments-Production Data...
Page 661 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description PROT Protection Control The Protection bits control what context is needed for reading and writing the block selected by the EEBLOCK register, or if block 0 is selected, all blocks. The following values are allowed:...
Page 662: Register 26: Eeprom Password (Eepass0), Offset 0X034
0x0 if no password is registered. A write to this register if it reads as 0x0 sets the password. If an attempt is made to write to this register when it reads as 0x1, the write is ignored and the NOPERM bit in the EEDONE register is set. June 18, 2014 Texas Instruments-Production Data...
Page 663: Register 29: Eeprom Interrupt (Eeint), Offset 0X040
Tiva TM4C1294NCPDT Microcontroller Register 29: EEPROM Interrupt (EEINT), offset 0x040 The EEINT register is used to control whether an interrupt should be generated when a write to EEPROM completes as indicated by the EEDONE register value changing from 0x1 to any other value.
Page 664: Register 30: Eeprom Block Hide 0 (Eehide0), Offset 0X050
Any attempt to clear a bit in this register that is set is ignored. reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 665: Register 31: Eeprom Block Hide 1 (Eehide1), Offset 0X054
Tiva TM4C1294NCPDT Microcontroller Register 31: EEPROM Block Hide 1 (EEHIDE1), offset 0x054 Register 32: EEPROM Block Hide 2 (EEHIDE2), offset 0x058 The EEHIDE register is used to hide one or more blocks. Bits 0 through 31 of the EEHIDE1 register correspond to EEPROM blocks 32 through 63.
Page 666 Mass Erase Value Description No action. When written as a 1, the EEPROM is mass erased. This bit continues to read as 1 until the EEPROM is fully erased. June 18, 2014 Texas Instruments-Production Data...
Page 667: Memory Register Descriptions (System Control Offset)
Tiva TM4C1294NCPDT Microcontroller Register 34: EEPROM Peripheral Properties (EEPROMPP), offset 0xFC0 The EEPROMPP register indicates the size of the EEPROM for this part. EEPROM Peripheral Properties (EEPROMPP) Base 0x400A.F000 Offset 0xFC0 Type RO, reset 0x0000.01FF reserved Type Reset SIZE Type...
Page 668: Register 35: Reset Vector Pointer (Rvp), Offset 0X0D4
The RVP register is initialized by a power-on reset. Reset Vector Pointer (RVP) Base 0x400F.E000 Offset 0x0D4 Type RO, reset 0x0101.FFF0 Type Reset Type Reset Bit/Field Name Type Reset Description 31:0 0x0101.FFF0 Reset Vector Pointer Address June 18, 2014 Texas Instruments-Production Data...
Page 669: Register 36: Flash Memory Protection Read Enable 0 (Fmpre0), Offset 0X200
Tiva TM4C1294NCPDT Microcontroller Register 36: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x200 Register 37: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 Register 38: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 Register 39: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C...
Page 670 Each bit configures a 2-KB flash block to be read only. Note that for read-protection of sectors, eight bits need to be cleared to create a 16-KB read-protected sector. The policies may be combined as shown in the table "Flash Protection Policy Combinations". June 18, 2014 Texas Instruments-Production Data...
Page 671: Register 52: Flash Memory Protection Program Enable 0 (Fmppe0), Offset 0X400
Tiva TM4C1294NCPDT Microcontroller Register 52: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x400 Register 53: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 Register 54: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 Register 55: Flash Memory Protection Program Enable 3 (FMPPE3), offset...
Page 672 ■ FMPPE13: 833 to 896 KB ■ FMPPE14: 897 to 960 KB ■ FMPPE15: 961 to 1024 KB Flash Memory Protection Program Enable n (FMPPEn) Base 0x400F.E000 Offset 0x400 Type RW, reset 0xFFFF.FFFF PROG_ENABLE Type Reset PROG_ENABLE Type Reset June 18, 2014 Texas Instruments-Production Data...
Page 673 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 31:0 PROG_ENABLE 0xFFFF.FFFF Flash Programming Enable Every eighth bit programs an 16-KB flash sector to be execute only. The policies may be combined as shown in Table 8-2 on page 610. June 18, 2014...
Page 674: Register 68: Boot Configuration (Bootcfg), Offset 0X1D0
“Recovering a "Locked" Microcontroller” on page 213. Boot Configuration (BOOTCFG) Base 0x400F.E000 Offset 0x1D0 Type RO, reset 0xFFFF.FFFE reserved Type Reset PORT reserved reserved DBG1 DBG0 Type Reset June 18, 2014 Texas Instruments-Production Data...
Page 675 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description Not Written When set, this bit indicates that the values in this register can be changed from 1 to 0. When clear, this bit specifies that the contents of this register cannot be changed.
Page 676 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. DBG0 Debug Control 0 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. June 18, 2014 Texas Instruments-Production Data...
Page 677: Register 71: User Register 2 (User_Reg2), Offset 0X1E8
Tiva TM4C1294NCPDT Microcontroller Register 69: User Register 0 (USER_REG0), offset 0x1E0 Register 70: User Register 1 (USER_REG1), offset 0x1E4 Register 71: User Register 2 (USER_REG2), offset 0x1E8 Register 72: User Register 3 (USER_REG3), offset 0x1EC Note: Offset is relative to System Control base address of 0x400F.E000.
Page 678: Micro Direct Memory Access (Μdma)
Micro Direct Memory Access (μDMA) Micro Direct Memory Access (μDMA) The TM4C1294NCPDT microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex -M4F processor, allowing for more efficient use of the processor and the available bus bandwidth.
Page 679: Block Diagram
Tiva TM4C1294NCPDT Microcontroller ■ Maskable peripheral requests ■ Interrupt on transfer completion, with a separate interrupt per channel Block Diagram Figure 9-1. μDMA Block Diagram System Memory uDMA DMA error Controller CH Control Table DMASTAT DMASRCENDP DMACFG dma_req DMADSTENDP General...
Page 680: Channel Assignments
Reserved Reserved Reserved UART0 UART1 Reserved GPTimer I2C1RX Reserved Reserved Reserved Reserved UART0 UART1 Reserved GPTimer I2C1 TX Reserved Reserved Reserved Reserved SSI0 RX SSI1 RX UART6 Reserved I2C2 RX Reserved Reserved GPTimer Reserved June 18, 2014 Texas Instruments-Production Data...
Page 681: Priority
Tiva TM4C1294NCPDT Microcontroller Table 9-1. μDMA Channel Assignments (continued) Encoding Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral SSI0 TX SSI1 TX UART6 Reserved I2C2 TX Reserved Reserved GPTimer Reserved Reserved UART2 SSI2 RX Reserved GPIO K Software Reserved...
Page 682: Arbitration Size
Trigger event C TX TX Buffer Not Full TX FIFO Level (configurable) C RX RX Buffer Not Empty RX FIFO Level (configurable) SSI TX TX FIFO Not Full TX FIFO Level (fixed at 4) June 18, 2014 Texas Instruments-Production Data...
Page 683: Channel Configuration
Tiva TM4C1294NCPDT Microcontroller Table 9-2. Request Type Support (continued) Peripheral Event that generates Single Request Event that generates Burst Request SSI RX RX FIFO Not Empty RX FIFO Level (fixed at 4) UART TX TX FIFO Not Full TX FIFO Level (configurable)
Page 684: Table 9-3. Control Structure Memory Map
DMA Channel Enable Set (DMAENASET) register. A channel can be disabled by setting the channel bit in the DMA Channel Enable Clear (DMAENACLR) register. At the end of a complete μDMA transfer, the controller automatically disables the channel. June 18, 2014 Texas Instruments-Production Data...
Page 685: Transfer Modes
Tiva TM4C1294NCPDT Microcontroller 9.2.6 Transfer Modes The μDMA controller supports several transfer modes. Two of the modes support simple one-time transfers. Several complex modes support a continuous flow of data. 9.2.6.1 Stop Mode While Stop is not actually a transfer mode, it is a valid value for the mode field of the control word.
Page 686: Figure 9-2. Example Of Ping-Pong Μdma Transaction
For example, a gather μDMA operation could be used to selectively read the payload of several stored packets of a communication protocol and store them together in sequence in a memory buffer. June 18, 2014 Texas Instruments-Production Data...
Page 687 Tiva TM4C1294NCPDT Microcontroller In Memory Scatter-Gather mode, the primary control structure is used to program the alternate control structure from a table in memory. The table is set up by the processor software and contains a list of control structures, each containing the source and destination end pointers, and the control word for a specific transfer.
Page 688: Figure 9-3. Memory Scatter-Gather, Setup And Configuration
3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the alternate control structure, where it is executed by the µDMA controller. 4. The SRC and DST pointers in the task list must point to the last location in the corresponding buffer. June 18, 2014 Texas Instruments-Production Data...
Page 689: Figure 9-4. Memory Scatter-Gather, Μdma Copy Sequence
Tiva TM4C1294NCPDT Microcontroller Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence Task List µDMA Control Table Buffers in Memory in Memory in Memory SRC A SRC B COPIED SRC C TASK A TASK B COPIED TASK C DEST A DEST B DEST C Then, using the channel’s alternate control structure, the...
Page 690 A to the peripheral data register. Next, the µDMA controller again uses the primary control structure to load task B into the alternate control structure, and then performs the B operation with the alternate control structure. The process is repeated for task C. June 18, 2014 Texas Instruments-Production Data...
Page 691: Figure 9-5. Peripheral Scatter-Gather, Setup And Configuration
Tiva TM4C1294NCPDT Microcontroller Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration Source Buffer Channel Control Task List in Memory in Memory Table in Memory 4 WORDS (SRC A) “TASK” A ITEMS=4 Channel Primary Unused Control Structure ITEMS=12 “TASK” B 16 WORDS (SRC B)
Page 692: Figure 9-6. Peripheral Scatter-Gather, Μdma Copy Sequence
Using the channel’s primary control structure, the µDMA Then, using the channel’s alternate control structure, the controller copies task C configuration to the channel’s µDMA controller copies data from the source buffer C to alternate control structure. the peripheral data register. June 18, 2014 Texas Instruments-Production Data...
Page 693: Transfer Size And Increment
Tiva TM4C1294NCPDT Microcontroller 9.2.7 Transfer Size and Increment The μDMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination data size must be the same for any given transfer. The source and destination address can be auto-incremented by bytes, half-words, or words, or can be set to no increment.
Page 694: Software Request
The location of the channel control structure must also be programmed. The following steps should be performed one time during system initialization: 1. Enable the μDMA clock using the RCGCDMA register (see page 385). June 18, 2014 Texas Instruments-Production Data...
Page 695: Configuring A Memory-To-Memory Transfer
Tiva TM4C1294NCPDT Microcontroller 2. Enable the μDMA controller by setting the MASTEREN bit of the DMA Configuration (DMACFG) register. 3. Program the location of the channel control table by writing the base address of the table to the DMA Channel Control Base Pointer (DMACTLBASE) register. The base address must be aligned on a 1024-byte boundary.
Page 696: Configuring A Peripheral For Simple Transmit
Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority. 2. Set bit 7 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the primary channel control structure for this transfer. June 18, 2014 Texas Instruments-Production Data...
Page 697: Table 9-9. Channel Control Structure Offsets For Channel 7
Tiva TM4C1294NCPDT Microcontroller 3. Set bit 7 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the μDMA controller to respond to single and burst requests. 4. Set bit 7 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow the μDMA controller to recognize requests for this channel.
Page 698: Configuring A Peripheral For Ping-Pong Receive
The primary control structure for channel 8 is at offset 0x080 of the channel control table, and the alternate channel control structure is at offset 0x280. The channel control structures for channel 8 are located at the offsets shown in Table 9-11. June 18, 2014 Texas Instruments-Production Data...
Page 699: Table 9-11. Primary And Alternate Channel Control Structure Offsets For Channel 8
Tiva TM4C1294NCPDT Microcontroller Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 Offset Description Control Table Base + 0x080 Channel 8 Primary Source End Pointer Control Table Base + 0x084 Channel 8 Primary Destination End Pointer Control Table Base + 0x088...
Page 700 Process the newly received data in buffer B or signal the buffer processing code that buffer B has data available. b. Reprogram the alternate channel control word at offset 0x288 according to Table 9-12 on page 699. June 18, 2014 Texas Instruments-Production Data...
Page 701: Configuring Channel Assignments
Tiva TM4C1294NCPDT Microcontroller 9.3.5 Configuring Channel Assignments Channel assignments for each μDMA channel can be changed using the DMACHMAPn registers. Each 4-bit field represents a μDMA channel. Refer to Table 9-1 on page 680 for channel assignments. For example, to use UART1 RX on channel 8, configure the CH8SEL bit in the DMACHMAP1 register to be 0x1.
Page 702: Μdma Channel Control Structure
The channel control structure is one entry in the channel control table. Each channel has a primary and alternate structure. The primary control structures are located at offsets 0x0, 0x10, 0x20 and so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on. June 18, 2014 Texas Instruments-Production Data...
Page 703: Register 1: Dma Channel Source Address End Pointer (Dmasrcendp), Offset 0X000
Tiva TM4C1294NCPDT Microcontroller Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 DMA Channel Source Address End Pointer (DMASRCENDP) is part of the Channel Control Structure and is used to specify the source address for a μDMA transfer.
Page 704: Register 2: Dma Channel Destination Address End Pointer (Dmadstendp), Offset 0X004
This field points to the last address of the μDMA transfer destination (inclusive). If the destination address is not incrementing (the DSTINC field in the DMACHCTL register is 0x3), then this field points at the destination location itself (such as a peripheral data register). June 18, 2014 Texas Instruments-Production Data...
Page 705: Register 3: Dma Channel Control Word (Dmachctl), Offset 0X008
Tiva TM4C1294NCPDT Microcontroller Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 DMA Channel Control Word (DMACHCTL) is part of the Channel Control Structure and is used to specify parameters of a μDMA transfer. Note: The offset specified is from the base address of the control structure in system memory, not the μDMA module base address.
Page 706 32-bit data size. Reserved 23:22 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 707 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description DSTPROT0 Destination Privilege Access This bit controls the privilege access protection for destination data writes. Value Description The access is non-privileged. The access is privileged. 20:19 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 708 For each trigger (whether from a peripheral or a software request), the μDMA controller performs the number of transfers specified by the ARBSIZE field. Auto-Request The initial request (software- or peripheral-initiated) is sufficient to complete the entire transfer of XFERSIZE items without any further requests. June 18, 2014 Texas Instruments-Production Data...
Page 709: Μdma Register Descriptions
Tiva TM4C1294NCPDT Microcontroller Ping-Pong This mode uses both the primary and alternate control structures for this channel. When the number of transfers specified by the XFERSIZE field have completed for the current control structure (primary or alternate), the µDMA controller switches to the other one. These switches continue until one of the control structures is not set to ping-pong mode.
Page 710: Register 4: Dma Status (Dmastat), Offset 0X000
Done 0xA-0xF Undefined reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 711 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description MASTEN Master Enable Status Value Description The μDMA controller is disabled. The μDMA controller is enabled. June 18, 2014 Texas Instruments-Production Data...
Page 712: Register 5: Dma Configuration (Dmacfg), Offset 0X004
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MASTEN Controller Master Enable Value Description Disables the μDMA controller. Enables μDMA controller. June 18, 2014 Texas Instruments-Production Data...
Page 713: Register 6: Dma Channel Control Base Pointer (Dmactlbase), Offset 0X008
Tiva TM4C1294NCPDT Microcontroller Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 The DMACTLBASE register must be configured so that the base pointer points to a location in system memory. The amount of system memory that must be assigned to the μDMA controller depends on the number of μDMA channels used and whether the alternate channel control data structure is used.
Page 714: Register 7: Dma Alternate Channel Control Base Pointer (Dmaaltbase), Offset 0X00C
Type RO, reset 0x0000.0200 ADDR Type Reset ADDR Type Reset Bit/Field Name Type Reset Description 31:0 ADDR 0x0000.0200 Alternate Channel Address Pointer This field provides the base address of the alternate channel control structures. June 18, 2014 Texas Instruments-Production Data...
Page 715: Register 8: Dma Channel Wait-On-Request Status (Dmawaitstat), Offset 0X010
Tiva TM4C1294NCPDT Microcontroller Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 This read-only register indicates that the μDMA channel is waiting on a request. A peripheral can hold off the μDMA from performing a single request until the peripheral is ready for a burst request to enhance the μDMA performance.
Page 716: Register 9: Dma Channel Software Request (Dmaswreq), Offset 0X014
These bits generate software requests. Bit 0 corresponds to channel 0. Value Description No request generated. Generate a software request for the corresponding channel. These bits are automatically cleared when the software request has been completed. June 18, 2014 Texas Instruments-Production Data...
Page 717: Register 10: Dma Channel Useburst Set (Dmauseburstset), Offset 0X018
Tiva TM4C1294NCPDT Microcontroller Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 Each bit of the DMAUSEBURSTSET register represents the corresponding μDMA channel. Setting a bit disables the channel's single request input from generating requests, configuring the channel to only accept burst requests. Reading the register returns the status of USEBURST.
Page 718: Register 11: Dma Channel Useburst Clear (Dmauseburstclr), Offset 0X01C
Description 31:0 CLR[n] Channel [n] Useburst Clear Value Description No effect. Setting a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register meaning that µDMA channel [n] responds to single and burst requests. June 18, 2014 Texas Instruments-Production Data...
Page 719: Register 12: Dma Channel Request Mask Set (Dmareqmaskset), Offset 0X020
Tiva TM4C1294NCPDT Microcontroller Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 Each bit of the DMAREQMASKSET register represents the corresponding μDMA channel. Setting a bit disables μDMA requests for the channel. Reading the register returns the request mask status.
Page 720: Register 13: Dma Channel Request Mask Clear (Dmareqmaskclr), Offset 0X024
Channel [n] Request Mask Clear Value Description No effect. Setting a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register meaning that the peripheral associated with channel [n] is enabled to request μDMA transfers. June 18, 2014 Texas Instruments-Production Data...
Page 721: Register 14: Dma Channel Enable Set (Dmaenaset), Offset 0X028
Tiva TM4C1294NCPDT Microcontroller Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 Each bit of the DMAENASET register represents the corresponding µDMA channel. Setting a bit enables the corresponding µDMA channel. Reading the register returns the enable status of the channels.
Page 722: Register 15: Dma Channel Enable Clear (Dmaenaclr), Offset 0X02C
No effect. Setting a bit clears the corresponding SET[n] bit in the DMAENASET register meaning that channel [n] is disabled for μDMA transfers. Note: The controller disables a channel when it completes the μDMA cycle. June 18, 2014 Texas Instruments-Production Data...
Page 723: Register 16: Dma Channel Primary Alternate Set (Dmaaltset), Offset 0X030
Tiva TM4C1294NCPDT Microcontroller Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 Each bit of the DMAALTSET register represents the corresponding µDMA channel. Setting a bit configures the µDMA channel to use the alternate control data structure. Reading the register returns the status of which control data structure is in use for the corresponding µDMA channel.
Page 724: Register 17: Dma Channel Primary Alternate Clear (Dmaaltclr), Offset 0X034
DMAALTSET register meaning that channel [n] is using the primary control structure. Note: For Ping-Pong and Scatter-Gather cycle types, the µDMA controller automatically sets these bits to select the alternate channel control data structure. June 18, 2014 Texas Instruments-Production Data...
Page 725: Register 18: Dma Channel Priority Set (Dmaprioset), Offset 0X038
Tiva TM4C1294NCPDT Microcontroller Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 Each bit of the DMAPRIOSET register represents the corresponding µDMA channel. Setting a bit configures the µDMA channel to have a high priority level. Reading the register returns the status of the channel priority mask.
Page 726: Register 19: Dma Channel Priority Clear (Dmaprioclr), Offset 0X03C
Reset Description 31:0 CLR[n] Channel [n] Priority Clear Value Description No effect. Setting a bit clears the corresponding SET[n] bit in the DMAPRIOSET register meaning that channel [n] is using the default priority level. June 18, 2014 Texas Instruments-Production Data...
Page 727: Register 20: Dma Bus Error Clear (Dmaerrclr), Offset 0X04C
Tiva TM4C1294NCPDT Microcontroller Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C The DMAERRCLR register is used to read and clear the µDMA bus error status. The error status is set if the μDMA controller encountered a bus error while performing a transfer. If a bus error occurs on a channel, that channel is automatically disabled by the μDMA controller.
Page 728: Register 21: Dma Channel Assignment (Dmachasgn), Offset 0X500
Offset 0x500 Type RW, reset 0x0000.0000 CHASGN[n] Type Reset CHASGN[n] Type Reset Bit/Field Name Type Reset Description 31:0 CHASGN[n] Channel [n] Assignment Select Value Description Use the primary channel assignment. Use the secondary channel assignment. June 18, 2014 Texas Instruments-Production Data...
Page 729: Register 22: Dma Channel Map Select 0 (Dmachmap0), Offset 0X510
Tiva TM4C1294NCPDT Microcontroller Register 22: DMA Channel Map Select 0 (DMACHMAP0), offset 0x510 Each 4-bit field of the DMACHMAP0 register configures the μDMA channel assignment as specified in Table 9-1 on page 680. Note: To support legacy software which uses the DMA Channel Assignment (DMACHASGN) register, a value of 0x0 is equivalent to a DMACHASGN bit being clear, and a value of 0x1 is equivalent to a DMACHASGN bit being set.
Page 730: Register 23: Dma Channel Map Select 1 (Dmachmap1), Offset 0X514
See Table 9-1 on page 680 for channel assignments. CH9SEL 0x00 μDMA Channel 9 Source Select See Table 9-1 on page 680 for channel assignments. CH8SEL 0x00 μDMA Channel 8 Source Select See Table 9-1 on page 680 for channel assignments. June 18, 2014 Texas Instruments-Production Data...
Page 731: Register 24: Dma Channel Map Select 2 (Dmachmap2), Offset 0X518
Tiva TM4C1294NCPDT Microcontroller Register 24: DMA Channel Map Select 2 (DMACHMAP2), offset 0x518 Each 4-bit field of the DMACHMAP2 register configures the μDMA channel assignment as specified in Table 9-1 on page 680. Note: To support legacy software which uses the DMA Channel Assignment (DMACHASGN) register, a value of 0x0 is equivalent to a DMACHASGN bit being clear, and a value of 0x1 is equivalent to a DMACHASGN bit being set.
Page 732: Register 25: Dma Channel Map Select 3 (Dmachmap3), Offset 0X51C
See Table 9-1 on page 680 for channel assignments. CH25SEL 0x00 μDMA Channel 25 Source Select See Table 9-1 on page 680 for channel assignments. CH24SEL 0x00 μDMA Channel 24 Source Select See Table 9-1 on page 680 for channel assignments. June 18, 2014 Texas Instruments-Production Data...
Page 733: Register 26: Dma Peripheral Identification 0 (Dmaperiphid0), Offset 0Xfe0
Tiva TM4C1294NCPDT Microcontroller Register 26: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 0 (DMAPeriphID0) Base 0x400F.F000 Offset 0xFE0 Type RO, reset 0x0000.0030...
Page 734: Register 27: Dma Peripheral Identification 1 (Dmaperiphid1), Offset 0Xfe4
PID1 0xB2 μDMA Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. June 18, 2014 Texas Instruments-Production Data...
Page 735: Register 28: Dma Peripheral Identification 2 (Dmaperiphid2), Offset 0Xfe8
Tiva TM4C1294NCPDT Microcontroller Register 28: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 2 (DMAPeriphID2) Base 0x400F.F000 Offset 0xFE8 Type RO, reset 0x0000.000B...
Page 736: Register 29: Dma Peripheral Identification 3 (Dmaperiphid3), Offset 0Xfec
PID3 0x00 μDMA Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. June 18, 2014 Texas Instruments-Production Data...
Page 737: Register 30: Dma Peripheral Identification 4 (Dmaperiphid4), Offset 0Xfd0
Tiva TM4C1294NCPDT Microcontroller Register 30: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 4 (DMAPeriphID4) Base 0x400F.F000 Offset 0xFD0 Type RO, reset 0x0000.0004...
Page 738: Register 31: Dma Primecell Identification 0 (Dmapcellid0), Offset 0Xff0
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CID0 0x0D μDMA PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. June 18, 2014 Texas Instruments-Production Data...
Page 739: Register 32: Dma Primecell Identification 1 (Dmapcellid1), Offset 0Xff4
Tiva TM4C1294NCPDT Microcontroller Register 32: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 1 (DMAPCellID1) Base 0x400F.F000 Offset 0xFF4 Type RO, reset 0x0000.00F0...
Page 740: Register 33: Dma Primecell Identification 2 (Dmapcellid2), Offset 0Xff8
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CID2 0x05 μDMA PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. June 18, 2014 Texas Instruments-Production Data...
Page 741: Register 34: Dma Primecell Identification 3 (Dmapcellid3), Offset 0Xffc
Tiva TM4C1294NCPDT Microcontroller Register 34: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 3 (DMAPCellID3) Base 0x400F.F000 Offset 0xFFC Type RO, reset 0x0000.00B1...
Page 742: General-Purpose Input/Outputs (Gpios)
– 2-mA, 4-mA, 6-mA, 8-mA, 10-mA and 12-mA pad drive for digital communication; up to four pads can sink 18-mA for high-current applications – Slew rate control for 8-mA, 10-mA and 12-mA pad drive – Open drain enables – Digital input enables June 18, 2014 Texas Instruments-Production Data...
Page 743: Signal Description
Tiva TM4C1294NCPDT Microcontroller 10.1 Signal Description GPIO signals have alternate hardware functions. The following table lists the GPIO pins and their analog and digital alternate functions. The digital alternate hardware functions are enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL) register to the numeric encoding shown in the table below.
Page 744 U2Tx T3CCP1 SSI1XDAT3 AIN5 U2RTS T4CCP0 USB0EPEN SSI2XDAT3 AIN4 U2CTS T4CCP1 USB0PFLT SSI2XDAT2 AIN3 U1RTS AIN2 U1DSR AIN1 U1DCD AIN0 U1DTR AIN9 U1RI SSI1XDAT0 AIN8 SSI1XDAT1 EN0LED0 M0PWM0 SSI3XDAT1 TRD2 EN0LED2 M0PWM1 SSI3XDAT0 TRD1 June 18, 2014 Texas Instruments-Production Data...
Page 745 Tiva TM4C1294NCPDT Microcontroller Table 10-2. GPIO Pins and Alternate Functions (128TQFP) (continued) Analog Digital Function (GPIOPCTL PMCx Bit Field Encoding) Special Function M0PWM2 SSI3Fss TRD0 M0PWM3 SSI3Clk TRCLK EN0LED1 M0FAULT0 SSI3XDAT2 TRD3 I2C1SCL EN0PPS M0PWM4 EPI0S11 I2C1SDA M0PWM5 EPI0S10 U0RTS...
Page 746: Pad Capabilities
Note: Port pins PL6 and PL7 operate as Fast GPIO pads, but have 4-mA drive capability only. GPIO register controls for drive strength, slew rate and open drain have no effect on these pins. The registers which have no effect are as follows: GPIODR2R, GPIODR4R, GPIODR8R, GPIODR12R, GPIOSLR, and GPIOODR. June 18, 2014 Texas Instruments-Production Data...
Page 747: Functional Description
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 10-1 on page 747 and Figure 10-2 on page 748). The TM4C1294NCPDT microcontroller contains 15 ports and thus 15 of these physical GPIO blocks. Note that not all pins are implemented on every block.
Page 748: Data Control
In the case that the software routine is not implemented and the device is locked out of the part, this issue can be solved by using the TM4C1294NCPDT Flash Programmer "Unlock" feature. Please refer to...
Page 749: Figure 10-3. Gpiodata Write Example
Tiva TM4C1294NCPDT Microcontroller 10.3.1.1 Data Direction Operation The GPIO Direction (GPIODIR) register (see page 760) is used to configure each individual pin as an input or output. When the data direction bit is cleared, the GPIO is configured as an input, and the corresponding data register bit captures and stores the value on the GPIO port.
Page 750: Interrupt Control
GPIOIM is set), and an interrupt for that port is generated, a trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, June 18, 2014 Texas Instruments-Production Data...
Page 751: Mode Control
Tiva TM4C1294NCPDT Microcontroller an ADC conversion is initiated. See page 1091. Note that whether the GPIO is configured to trigger on edge events or level events, a single-clock ADC trigger pulse is created in either event. Thus, when a level event is selected, the ADC sample sequence will run only one time and multiple sample sequences will not be executed if the level remains the same.
Page 752: Commit Control
2-mA driver. The table below shows the drive capability options. If EDMn is 0x00, then the GPIODR2R, GPIODR4R, and GPIODR8R function as stated in their default register description. Note: A GPIOPC register write must precede the configuration of the GPIODRnR registers in order for extended drive mode to take effect. June 18, 2014 Texas Instruments-Production Data...
Page 753: Identification
Tiva TM4C1294NCPDT Microcontroller Table 10-3. GPIO Drive Strength Options EDMn GPIODR12R GPIODR8R GPIODR4R GPIODR2R (2mA) Drive (mA) (GPIOPP) (GPIOPC) (+4mA) (+4mA) (+2mA) 10.3.6 Identification The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers.
Page 754: Table 10-4. Gpio Pad Configuration Examples
DR4R DR8R DR12R Digital Input (GPIO) Digital Output (GPIO) Open Drain Output (GPIO) Open Drain Input/Output (I2CSDA) Digital Input/Output (I2CSCL) Digital Input (Timer CCP) Digital Input (QEI) Digital Output (PWM) Digital Output (Timer PWM) June 18, 2014 Texas Instruments-Production Data...
Page 755: Register Map
Tiva TM4C1294NCPDT Microcontroller Table 10-4. GPIO Pad Configuration Examples (continued) GPIO Register Bit Value Configuration AFSEL DR2R DR4R DR8R DR12R Digital Input/Output (SSI) Digital Input/Output (UART) Analog Input (Comparator) Digital Output (Comparator) a. X=Ignored (don’t care bit) ?=Can be either 0 or 1, depending on the configuration Table 10-5.
Page 756: Table 10-6. Gpio Pins With Special Considerations
NMI and JTAG/SWD pins (see “Signal Tables” on page 1772 for pin numbers). To ensure that the JTAG and NMI pins are not accidentally programmed as GPIO pins, these pins default to non-committable. Because of this, the default reset value of GPIOCR changes for the corresponding ports. June 18, 2014 Texas Instruments-Production Data...
Page 757: Table 10-7. Gpio Register Map
Tiva TM4C1294NCPDT Microcontroller Table 10-7. GPIO Register Map Offset Name Type Reset Description page 0x000 GPIODATA 0x0000.0000 GPIO Data 0x400 GPIODIR 0x0000.0000 GPIO Direction 0x404 GPIOIS 0x0000.0000 GPIO Interrupt Sense 0x408 GPIOIBE 0x0000.0000 GPIO Interrupt Both Edges 0x40C GPIOIEV 0x0000.0000...
Page 758: Register Descriptions
0xFF8 GPIOPCellID2 0x0000.0005 GPIO PrimeCell Identification 2 0xFFC GPIOPCellID3 0x0000.00B1 GPIO PrimeCell Identification 3 10.6 Register Descriptions The remainder of this section lists and describes the GPIO registers, in numerical order by address offset. June 18, 2014 Texas Instruments-Production Data...
Page 759: Register 1: Gpio Data (Gpiodata), Offset 0X000
Tiva TM4C1294NCPDT Microcontroller Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 760).
Page 760: Register 2: Gpio Direction (Gpiodir), Offset 0X400
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 GPIO Data Direction Value Description Corresponding pin is an input. Corresponding pins is an output. June 18, 2014 Texas Instruments-Production Data...
Page 761: Register 3: Gpio Interrupt Sense (Gpiois), Offset 0X404
Tiva TM4C1294NCPDT Microcontroller Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Setting a bit in the GPIOIS register configures the corresponding pin to detect levels, while clearing a bit configures the corresponding pin to detect edges.
Page 762: Register 4: Gpio Interrupt Both Edges (Gpioibe), Offset 0X408
0x00 GPIO Interrupt Both Edges Value Description Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register (see page 763). Both edges on the corresponding pin trigger an interrupt. June 18, 2014 Texas Instruments-Production Data...
Page 763: Register 5: Gpio Interrupt Event (Gpioiev), Offset 0X40C
Tiva TM4C1294NCPDT Microcontroller Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Setting a bit in the GPIOIEV register configures the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 761).
Page 764: Register 6: Gpio Interrupt Mask (Gpioim), Offset 0X410
The µDMA done interrupt is not masked and can generate an interrupt to the interrupt controller. 0x00 GPIO Interrupt Mask Enable Value Description The interrupt from the corresponding pin is masked. The interrupt from the corresponding pin is sent to the interrupt controller. June 18, 2014 Texas Instruments-Production Data...
Page 765: Register 7: Gpio Raw Interrupt Status (Gpioris), Offset 0X414
Tiva TM4C1294NCPDT Microcontroller Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. A bit in this register is set when an interrupt condition occurs on the corresponding GPIO pin or if a µDMA done interrupt occurs. If the corresponding bit in the GPIO Interrupt Mask (GPIOIM) register (see page 764) is set, the interrupt is sent to the interrupt controller.
Page 766 An interrupt condition has occurred on the corresponding pin. For edge-detect interrupts, this bit is cleared by writing a 1 to the corresponding bit in the GPIOICR register. For a GPIO level-detect interrupt, the bit is cleared when the level is deasserted. June 18, 2014 Texas Instruments-Production Data...
Page 767: Register 8: Gpio Masked Interrupt Status (Gpiomis), Offset 0X418
Tiva TM4C1294NCPDT Microcontroller Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. If a bit is set in this register, the corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear, either no interrupt has been generated, or the interrupt is masked.
Page 768 For edge-detect interrupts, this bit is cleared by writing a 1 to the corresponding bit in the GPIOICR register. For a GPIO level-detect interrupt, the bit is cleared when the level is deasserted. June 18, 2014 Texas Instruments-Production Data...
Page 769: Register 9: Gpio Interrupt Clear (Gpioicr), Offset 0X41C
Tiva TM4C1294NCPDT Microcontroller Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to the DMAIC bit in this register clears the corresponding interrupt bit in the GPIORIS and GPIOMIS registers. For edge-detect interrupts, writing a 1 to the IC bit in the GPIOICR register clears the corresponding bit in the GPIORIS and GPIOMIS registers.
Page 770: Register 10: Gpio Alternate Function Select (Gpioafsel), Offset 0X420
In the case that the software routine is not implemented and the device is locked out of the part, this issue can be solved by using the TM4C1294NCPDT Flash Programmer "Unlock" feature. Please refer to...
Page 771 Tiva TM4C1294NCPDT Microcontroller Pull Up Select (GPIOPUR) register (see page 776), GPIO Pull-Down Select (GPIOPDR) register (see page 778), and GPIO Digital Enable (GPIODEN) register (see page 781) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 783) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 784) have been set.
Page 772: Register 11: Gpio 2-Ma Drive Select (Gpiodr2R), Offset 0X500
The corresponding GPIO pin has 2-mA drive. Setting a bit in either the GPIODR4 register or the GPIODR8 register clears the corresponding 2-mA enable bit. The change is effective on the next clock cycle. June 18, 2014 Texas Instruments-Production Data...
Page 773: Register 12: Gpio 4-Ma Drive Select (Gpiodr4R), Offset 0X504
Tiva TM4C1294NCPDT Microcontroller Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware.
Page 774: Register 13: Gpio 8-Ma Drive Select (Gpiodr8R), Offset 0X508
The corresponding GPIO pin has 8-mA drive. Setting a bit in either the GPIODR2 register or the GPIODR4 register clears the corresponding 8-mA enable bit. The change is effective on the next clock cycle. June 18, 2014 Texas Instruments-Production Data...
Page 775: Register 14: Gpio Open Drain Select (Gpioodr), Offset 0X50C
Tiva TM4C1294NCPDT Microcontroller Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open-drain configuration of the corresponding GPIO pad. When open-drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Enable (GPIODEN) register (see page 781).
Page 776: Register 15: Gpio Pull-Up Select (Gpiopur), Offset 0X510
Enable (GPIODEN) register (see page 781) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 783) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 784) have been set. June 18, 2014 Texas Instruments-Production Data...
Page 777 Tiva TM4C1294NCPDT Microcontroller GPIO Pull-Up Select (GPIOPUR) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (AHB) base: 0x4005.E000...
Page 778: Register 16: Gpio Pull-Down Select (Gpiopdr), Offset 0X514
Enable (GPIODEN) register (see page 781) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 783) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 784) have been set. June 18, 2014 Texas Instruments-Production Data...
Page 779 Tiva TM4C1294NCPDT Microcontroller GPIO Pull-Down Select (GPIOPDR) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (AHB) base: 0x4005.E000...
Page 780: Register 17: Gpio Slew Rate Control Select (Gpioslr), Offset 0X518
0x00 Slew Rate Limit Enable (8-mA, 10-mA and 12-mA drive only) Value Description Slew rate control is disabled for the corresponding pin. Slew rate control is enabled for the corresponding pin. June 18, 2014 Texas Instruments-Production Data...
Page 781: Register 18: Gpio Digital Enable (Gpioden), Offset 0X51C
Tiva TM4C1294NCPDT Microcontroller Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C Note: Pins configured as digital inputs are Schmitt-triggered. The GPIODEN register is the digital enable register. By default, all GPIO signals except those listed below are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver.
Page 782 The digital functions for the corresponding pin are disabled. The digital functions for the corresponding pin are enabled. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in Table 10-1 on page 743. June 18, 2014 Texas Instruments-Production Data...
Page 783: Register 19: Gpio Lock (Gpiolock), Offset 0X520
Tiva TM4C1294NCPDT Microcontroller Register 19: GPIO Lock (GPIOLOCK), offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register (see page 784). Writing 0x4C4F.434B to the GPIOLOCK register unlocks the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written.
Page 784: Register 20: Gpio Commit (Gpiocr), Offset 0X524
Description 31:8 reserved 0x0000.00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 785 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description GPIO Commit Value Description The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN bits cannot be written. The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN bits can be written. Note: The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the NMI pin and the four JTAG/SWD pins (see “Signal Tables”...
Page 786: Register 21: Gpio Analog Mode Select (Gpioamsel), Offset 0X528
Note: This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. The reset state of this register is 0 for all signals. June 18, 2014 Texas Instruments-Production Data...
Page 787: Register 22: Gpio Port Control (Gpiopctl), Offset 0X52C
Tiva TM4C1294NCPDT Microcontroller Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C The GPIOPCTL register is used in conjunction with the GPIOAFSEL register and selects the specific peripheral signal for each GPIO pin when using the alternate function mode. Most bits in the GPIOAFSEL register are cleared on reset, therefore most GPIO pins are configured as GPIOs by default.
Page 788 This field controls the configuration for GPIO pin 2. PMC1 Port Mux Control 1 This field controls the configuration for GPIO pin 1. PMC0 Port Mux Control 0 This field controls the configuration for GPIO pin 0. June 18, 2014 Texas Instruments-Production Data...
Page 789: Register 23: Gpio Adc Control (Gpioadcctl), Offset 0X530
Tiva TM4C1294NCPDT Microcontroller Register 23: GPIO ADC Control (GPIOADCCTL), offset 0x530 This register is used to configure a GPIO pin as a source for the ADC trigger. Note that if the Port B GPIOADCCTL register is cleared, PB4 can still be used as an external trigger for the ADC.
Page 790: Register 24: Gpio Dma Control (Gpiodmactl), Offset 0X534
DMAEN 0x00 μDMA Trigger Enable Value Description The corresponding pin is not used to trigger the μDMA. The corresponding pin is used to trigger the μDMA. June 18, 2014 Texas Instruments-Production Data...
Page 791: Register 25: Gpio Select Interrupt (Gpiosi), Offset 0X538
Tiva TM4C1294NCPDT Microcontroller Register 25: GPIO Select Interrupt (GPIOSI), offset 0x538 This register is used to enable individual interrupts for each pin. Note: This register is only available on Port P and Port Q. GPIO Select Interrupt (GPIOSI) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000...
Page 792: Register 26: Gpio 12-Ma Drive Select (Gpiodr12R), Offset 0X53C
Please refer to Table 10-3 on page 753 for information on how to configure the drive strength. Changes in the GPIODR2R, the GPIODR4R register and/or the GPIODR8R registers to configure 12 mA are effective on the next clock cycle. June 18, 2014 Texas Instruments-Production Data...
Page 793: Register 27: Gpio Wake Pin Enable (Gpiowakepen), Offset 0X540
Tiva TM4C1294NCPDT Microcontroller Register 27: GPIO Wake Pin Enable (GPIOWAKEPEN), offset 0x540 This register is used to configure K[7:4] as a wake enable source for the hibernation module. The wake level must be programmed in the GPIOWAKELVL register at offset 0x544. In order for this register configuration to become implemented, the WUUNLK bit needs to be set in the HIBIO register at offset 0x02C in the hibernation module.
Page 794 Wake-on level is enabled. reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 795: Register 28: Gpio Wake Level (Gpiowakelvl), Offset 0X544
Tiva TM4C1294NCPDT Microcontroller Register 28: GPIO Wake Level (GPIOWAKELVL), offset 0x544 This register is used to configure the wake level for K[7:4] in the hibernation module. The wake source must be enabled in the GPIOWAKEPEN register at offset 0x540. In order for this register configuration to become implemented, the WUUNLK bit needs to be set in the HIBIO register at offset 0x02C in the hibernation module.
Page 796 Wake level high reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 797: Register 29: Gpio Wake Status (Gpiowakestat), Offset 0X548
Tiva TM4C1294NCPDT Microcontroller Register 29: GPIO Wake Status (GPIOWAKESTAT), offset 0x548 This register indicates the GPIO wake event status. If a register bit has been set for K[7:4] , a wake event signal has been sent to the Hibernate module.
Page 798 Pin wake event asserted to hibernate module reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 799: Register 30: Gpio Peripheral Property (Gpiopp), Offset 0Xfc0
Tiva TM4C1294NCPDT Microcontroller Register 30: GPIO Peripheral Property (GPIOPP), offset 0xFC0 The GPIOPP register provides information regarding the GPIO properties. GPIO Peripheral Property (GPIOPP) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (AHB) base: 0x4005.B000...
Page 800: Register 31: Gpio Peripheral Configuration (Gpiopc), Offset 0Xfc4
10-3 on page 753 shows the drive capability options. If EDMn is 0x00, then the GPIODR2R, GPIODR4R, and GPIODR8R function as stated in their default register description. Table 10-13. GPIO Drive Strength Options EDMn GPIODR12R GPIODR8R GPIODR4R GPIODR2R (2mA) Drive (mA) (GPIOPP) (GPIOPC) (+4mA) (+4mA) (+2mA) June 18, 2014 Texas Instruments-Production Data...
Page 801 Tiva TM4C1294NCPDT Microcontroller GPIO Peripheral Configuration (GPIOPC) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (AHB) base: 0x4005.E000...
Page 802 The write one, clear other behavior of GPIODDRnR registers is disabled. A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 June 18, 2014 Texas Instruments-Production Data...
Page 803: Register 32: Gpio Peripheral Identification 4 (Gpioperiphid4), Offset 0Xfd0
Tiva TM4C1294NCPDT Microcontroller Register 32: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral.
Page 804: Register 33: Gpio Peripheral Identification 5 (Gpioperiphid5), Offset 0Xfd4
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PID5 0x00 GPIO Peripheral ID Register [15:8] June 18, 2014 Texas Instruments-Production Data...
Page 805: Register 34: Gpio Peripheral Identification 6 (Gpioperiphid6), Offset 0Xfd8
Tiva TM4C1294NCPDT Microcontroller Register 34: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral.
Page 806: Register 35: Gpio Peripheral Identification 7 (Gpioperiphid7), Offset 0Xfdc
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PID7 0x00 GPIO Peripheral ID Register [31:24] June 18, 2014 Texas Instruments-Production Data...
Page 807: Register 36: Gpio Peripheral Identification 0 (Gpioperiphid0), Offset 0Xfe0
Tiva TM4C1294NCPDT Microcontroller Register 36: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral.
Page 808: Register 37: Gpio Peripheral Identification 1 (Gpioperiphid1), Offset 0Xfe4
PID1 0x00 GPIO Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. June 18, 2014 Texas Instruments-Production Data...
Page 809: Register 38: Gpio Peripheral Identification 2 (Gpioperiphid2), Offset 0Xfe8
Tiva TM4C1294NCPDT Microcontroller Register 38: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral.
Page 810: Register 39: Gpio Peripheral Identification 3 (Gpioperiphid3), Offset 0Xfec
PID3 0x01 GPIO Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. June 18, 2014 Texas Instruments-Production Data...
Page 811: Register 40: Gpio Primecell Identification 0 (Gpiopcellid0), Offset 0Xff0
Tiva TM4C1294NCPDT Microcontroller Register 40: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system.
Page 812: Register 41: Gpio Primecell Identification 1 (Gpiopcellid1), Offset 0Xff4
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CID1 0xF0 GPIO PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. June 18, 2014 Texas Instruments-Production Data...
Page 813: Register 42: Gpio Primecell Identification 2 (Gpiopcellid2), Offset 0Xff8
Tiva TM4C1294NCPDT Microcontroller Register 42: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system.
Page 814: Register 43: Gpio Primecell Identification 3 (Gpiopcellid3), Offset 0Xffc
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CID3 0xB1 GPIO PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. June 18, 2014 Texas Instruments-Production Data...
Page 815: External Peripheral Interface (Epi)
Tiva TM4C1294NCPDT Microcontroller External Peripheral Interface (EPI) The External Peripheral Interface is a high-speed parallel bus for external peripherals or memory. It has several modes of operation to interface gluelessly to many types of external devices. The External Peripheral Interface is similar to a standard microprocessor address/data bus, except that it must typically be connected to just one type of external device.
Page 816: Epi Block Diagram
– 1 to 32 bits, FIFOed with speed control – Useful for custom peripherals or for digital data acquisition and actuator controls 11.1 EPI Block Diagram Figure 11-1 on page 817 provides a block diagram of a TM4C1294NCPDT EPI module. June 18, 2014 Texas Instruments-Production Data...
Page 817: Signal Description
Tiva TM4C1294NCPDT Microcontroller Figure 11-1. EPI Block Diagram General Parallel NBRFIFO GPIO 8 x 32 bits WFIFO SDRAM 4 x 32 bits EPI 31:0 Interface With Host Bus Baud Rate Control (Clock) Wide Parallel Interface 11.2 Signal Description The following table lists the external signals of the EPI controller and describes the function of each.
Page 818: Functional Description
GPIO which has more variable timing due to on-chip bus arbitration and delays across bus bridges. Blocking reads stall the CPU until the transaction completes. Non-blocking reads are performed in the background and allow the processor June 18, 2014 Texas Instruments-Production Data...
Page 819: Master Access To Epi
Tiva TM4C1294NCPDT Microcontroller to continue operation. In addition, write data can also be stored in the WFIFO to allow multiple writes with no stalls. Note: Both the WTAV bit field in the EPIWFIFOCNT register and the WBUSY bit in the EPISTAT register must be polled to determine if there is a current write transaction from the WFIFO.
Page 820: Dma Operation
WFIFO is full. Note that when the µDMA controller is stalled, the core continues operation. See “Micro Direct Memory Access (μDMA)” on page 678 for more information on configuring the µDMA. June 18, 2014 Texas Instruments-Production Data...
Page 821: Initialization And Configuration
(see “Register Descriptions” on page 758). Normally, a pull-up or pull-down is needed on the board to at least control the chip-select or chip-enable as the TM4C1294NCPDT GPIOs come out of reset in tri-state. June 18, 2014...
Page 822: Epi Interface Options
PRECHARGE or ACTIVATE) is determined. If a higher frequency is given than is used, then the only downside is that the peripheral is slower (uses more cycles for these delays). If a lower frequency is given, incorrect operation occurs. June 18, 2014 Texas Instruments-Production Data...
Page 823: Table 11-3. Epi Sdram X16 Signal Connections
Tiva TM4C1294NCPDT Microcontroller See “External Peripheral Interface (EPI)” on page 1853 for timing details for the SDRAM mode. 11.4.2.1 External Signal Connections Table 11-3 on page 823 defines how EPI module signals should be connected to SDRAMs. The table applies when using a x16 SDRAM up to 512 megabits. Note that the EPI signals must use 8-mA drive when interfacing to SDRAM, see page 774.
Page 824: Figure 11-2. Sdram Non-Blocking Read Cycle
(EPI0S19) CASn (EPI0S18) DQMH, DQML (EPI0S [17:16]) AD [15:0] Column Data 0 Data 1 Data n (EPI0S [15:0]) Burst Activate Read Term AD [15:0] driven in AD [15:0] driven out AD [15:0] driven out June 18, 2014 Texas Instruments-Production Data...
Page 825: Figure 11-3. Sdram Normal Read Cycle
Tiva TM4C1294NCPDT Microcontroller 11.4.2.5 Normal Read Cycle Figure 11-3 on page 825 shows a normal read cycle of n halfwords; n can be 1 or 2. The cycle begins with the Activate command and the row address on the EPI0S[15:0] signals. With the programmed CAS latency of 2, the Read command with the column address on the EPI0S[15:0] signals follows after 2 clock cycles.
Page 826: Host Bus Mode
4 external devices to the EPI signals, as well as control whether byte select signals are provided in HB16 mode. These capabilities depend on the configuration of the MODE field in the EPIHBnCFG June 18, 2014 Texas Instruments-Production Data...
Page 827: Table 11-4. Cscfgext + Cscfg Encodings
Tiva TM4C1294NCPDT Microcontroller register, the CSCFG field and the CSCFGEXT bit in the EPIHBnCFGn register, and the BSEL bit in the EPIHB16CFG register. The CSCFGEXT bit extends the chip select configuration possibilities by providing the most significant bit of the CSCFG field. Refer to Table 11-4 on page 827 for the possible ALE and chip select options that can be programmed by the combination of the CSCFGEXT and CSCFG bits.
Page 828: Table 11-5. Dual- And Quad- Chip Select Address Mappings
If the CSBAUD bit is clear, all chip selects use the clock frequency, wait states, and strobe polarity defined for CS0n. If the CSBAUD bit is set, the four chip selects can use different interface modes. June 18, 2014 Texas Instruments-Production Data...
Page 829: Table 11-6. Chip Select Configuration Register Assignment
Tiva TM4C1294NCPDT Microcontroller Table 11-6. Chip Select Configuration Register Assignment Configuration Register Corresponding Chip Select EPIHBnCFG CS0n EPIHBnCFG2 CS1n EPIHBnCFG3 CS2n EPIHBnCFG4 CS3n a. If the CSBAUD bit in the EPIHBnCFG2 register is clear and multiple chip selects are enabled, then all chip selects are configured by the MODE bit field in the EPIHBnCFG register.
Page 830 Two EPI signals are used for byte selects, reducing the available address space by two bits. Table 11-8 on page 831 shows how the EPI[31:0] signals function while in Host-Bus 8 mode. Notice that the signal configuration changes based on the address/data mode selected by the MODE June 18, 2014 Texas Instruments-Production Data...
Page 831: Table 11-8. Epi Host-Bus 8 Signal Connections
Tiva TM4C1294NCPDT Microcontroller field in the EPIHB8CFGn register and on the chip select configuration selected by the CSCFG and CSCFGEXT field in the EPIHB8CFG2 register. Although the EPI0S31 signal can be configured for the EPI clock signal in Host-Bus mode, it is not required and should be configured as a GPIO to reduce EMI in the system.
Page 832 CS0n CS0n CS1n CS1n EPI0S27 FFULL CS0n CS0n CS1n CS1n EPI0S28 RDn/OEn RDn/OEn EPI0S29 CS0n CS0n CS0n EPI0S30 CS0n CS0n EPI0S31 Clock Clock Clock EPI0S32 iRDY iRDY iRDY EPI0S33 CS3n CS3n EPI0S34 CS2n CS2n June 18, 2014 Texas Instruments-Production Data...
Page 833: Table 11-9. Epi Host-Bus 16 Signal Connections
Tiva TM4C1294NCPDT Microcontroller Table 11-8. EPI Host-Bus 8 Signal Connections (continued) EPI Signal HB8 Signal (MODE HB8 Signal (MODE HB8 Signal (MODE CSCFG =ADMUX) =ADNOMUX (Cont. =XFIFO) Read)) EPI0S35 a. "X" indicates the state of this field is a don't care.
Page 834 HB16 Signal (MODE HB16 Signal CSCFG BSEL =ADMUX) =ADNOMUX (Cont. (MODE Read)) =XFIFO) EPI0S18 EPI0S19 EPI0S20 EPI0S21 EPI0S22 EPI0S23 EPI0S24 BSEL0n BSEL0n BSEL0n BSEL0n CS1n BSEL0n BSEL0n BSEL1n BSEL1n EPI0S25 BSEL0n BSEL0n BSEL0n BSEL0n BSEL1n BSEL1n June 18, 2014 Texas Instruments-Production Data...
Page 835 Tiva TM4C1294NCPDT Microcontroller Table 11-9. EPI Host-Bus 16 Signal Connections (continued) EPI Signal HB16 Signal (MODE HB16 Signal (MODE HB16 Signal CSCFG BSEL =ADMUX) =ADNOMUX (Cont. (MODE Read)) =XFIFO) BSEL0n BSEL0n BSEL0n BSEL0n FEMPTY BSEL1n BSEL1n EPI0S26 CS0n CS0n BSEL1n...
Page 836: Figure 11-5. Irdy Access Stalls, Irdydly==01, 10, 11
RDCRE bit in EPIHB16CFG2 register activates CS1n during a PSRAM configuration register write or read. The WRCRE and RDCRE bit in EBIHB16CFG3 corresponds to CS2n and EPIHB16CFG4, to CS3n. The WRCRE bit clears when the transfer is done. There must not be any system access or June 18, 2014 Texas Instruments-Production Data...
Page 837 Tiva TM4C1294NCPDT Microcontroller non-blocking read activity during the CRE read or write-enable transfer. During a write to the PSRAM's CR, the configuration data is written out on data pins [20:0] of the EPI bus. For a PSRAM configuration read access, the RDCRE bit in the EPIHB16CFG register is set to signal that the next access is a read of the PSRAM configuration register (CR).
Page 838: Table 11-10. Psram Fixed Latency Wait State Configuration
Burst mode the RDWS and WRWS bit fields define the latency for only the first access of the write or read cycle. Every access after that is a single access. Figure 11-7 on page 839 and Figure 11-8 on page 839 depict a PSRAM burst read and write. June 18, 2014 Texas Instruments-Production Data...
Page 839: Figure 11-7. Psram Burst Read
Tiva TM4C1294NCPDT Microcontroller Figure 11-7. PSRAM Burst Read EPICLK EPI0S31 EPI0S[19:0] ADDRESS Latency (3 clocks) EPI0S29 iRDY EPI0S32 EPI0S[15:0] DATA0 DATA1 DATA2 DATA3 BSELn Figure 11-8. PSRAM Burst Write EPICLK EPI0S31 EPI0S[19:0] ADDRESS Latency (3 clocks) EPI0S28 EPI0S29 iRDY EPI0S32...
Page 840: Figure 11-9. Read Delay During Refresh Event
Figure 11-10 on page 841 depict the delay in data transfer during a refresh collision. Figure 11-9. Read Delay During Refresh Event EPICLK EPI0S31 EPI0S[19:0] ADDRESS EPI0S28 EPI0S29 BSELn iRDY EPI0S32 EPI0S[15:0] DATA3 DATA0 DATA1 DATA2 One wait state June 18, 2014 Texas Instruments-Production Data...
Page 841: Figure 11-10. Write Delay During Refresh Event
Tiva TM4C1294NCPDT Microcontroller Figure 11-10. Write Delay During Refresh Event EPICLK EPI0S31 EPI0S[19:0] ADDRESS EPI0S28 EPI0S29 BSELn iRDY EPI0S32 EPI0S[15:0] DATA0 DATA1 DATA2 DATA3 One wait state 11.4.3.3 Host Bus 16-bit Muxed Interface Figure 11-11 on page 842 shows how to connect the EPI signals to a 16-bit SRAM and a 16-bit Flash memory with muxed address and memory using byte selects and dual chip selects with ALE.
Page 842: Figure 11-11. Example Schematic For Muxed Host-Bus 16 Mode
CSBAUD bit in the EPIHBnCFG2 register. In this case, the COUNT0 field controls the CS0n transactions, and the COUNT1 field controls the CS1n transactions. When using quad chip select mode, the COUNT0 bit field of the EPIBAUD2 register June 18, 2014 Texas Instruments-Production Data...
Page 843: Table 11-11. Data Phase Wait State Programming
Tiva TM4C1294NCPDT Microcontroller controls the baud rate of CS2n and the COUNT1 bit field is programmed to control the baud rate of CS3n. Additionally, the Host-Bus mode provides read and write wait states for the data portion to support different classes of device. These wait states stretch the data period (hold the rising edge of data strobe) and may be used in all four sub-modes.
Page 844 Figure 11-12 on page 845 shows a basic Host-Bus read cycle. Figure 11-13 on page 845 shows a basic Host-Bus write cycle. Both of these figures show address and data signals in the non-multiplexed mode (MODE field ix 0x1 in the EPIHBnCFG register). June 18, 2014 Texas Instruments-Production Data...
Page 845: Figure 11-12. Host-Bus Read Cycle, Mode = 0X1, Wrhigh = 0, Rdhigh = 0
Tiva TM4C1294NCPDT Microcontroller Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 (EPI0S30) (EPI0S30) (EPI0S29) RDn/OEn (EPI0S28) BSEL0n/ BSEL1n Address Data Data BSEL0n and BSEL1n are available in Host-Bus 16 mode only. Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0...
Page 846: Figure 11-14. Host-Bus Write Cycle With Multiplexed Address And Data, Mode = 0X0, Wrhigh 0, Rdhigh = 0
(output enable is asserted) and then changing the address pins. The data pins are changed by the SRAM after the address pins change. Figure 11-16. Continuous Read Mode Accesses Address Addr1 Addr2 Addr3 Data Data1 Data2 Data3 June 18, 2014 Texas Instruments-Production Data...
Page 847: General-Purpose Mode
Tiva TM4C1294NCPDT Microcontroller FIFO mode accesses are the same as normal read and write accesses, except that the ALE signal and address pins are not present. Two input signals can be used to indicate when the XFIFO is full or empty to gate transactions and avoid overruns and underruns. The FFULL and FEMPTY signals are synchronized and must be recognized as asserted by the microcontroller for 2 system clocks before they affect transaction status.
Page 848 20-bit address uses EPI0S[27:8]. The address signals may be used by the external peripheral as an address, code (command), or for other unrelated uses (such as a chip enable). If the chosen address/data combination does not use all of the EPI signals, the unused pins can be June 18, 2014 Texas Instruments-Production Data...
Page 849: Table 11-12. Epi General-Purpose Signal Connections
Tiva TM4C1294NCPDT Microcontroller used as GPIOs or for other functions. For example, when using a 4-bit address with an 8-bit data, the pins assigned to EPIS0[23:8] can be assigned to other functions. ■ Data may be 8 bits, 16 bits, 24 bits, or 32 bits (controlled by the DSIZE field in the EPIGPCFG register).
Page 850: Figure 11-19. Single-Cycle Single Write Access, Frm50=0, Frmcnt=0, Wr2Cyc=0
WR2CYC bit in the EPIGPCFG register. Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0 Clock (EPI0S31) Frame (EPI0S30) (EPI0S29) (EPI0S28) Address Data Data June 18, 2014 Texas Instruments-Production Data...
Page 851: Figure 11-20. Two-Cycle Read, Write Accesses, Frm50=0, Frmcnt=0, Wr2Cyc=1
Tiva TM4C1294NCPDT Microcontroller Figure 11-20. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, WR2CYC=1 CLOCK (EPI0S31) FRAME (EPI0S30) (EPI0S29) (EPI0S28) Address Data Data Data Read Write Figure 11-21. Read Accesses, FRM50=0, FRMCNT=0 CLOCK (EPI0S31) FRAME (EPI0S30) (EPI0S29) (EPI0S28) Address Addr1 Addr2 Addr3...
Page 852: Figure 11-22. Frame Signal Operation, Frm50=0 And Frmcnt=0
Clock (EPI0S31) WR (EPI0S28) RD (EPI0S29) Frame (EPI0S30) When FRMCNT=1, the FRAME signal transitions on the rising edge of the WR or RD strobes for every other access, see Figure 11-26 on page 853. June 18, 2014 Texas Instruments-Production Data...
Page 853: Figure 11-26. Frame Signal Operation, Frm50=1 And Frmcnt=1
Tiva TM4C1294NCPDT Microcontroller Figure 11-26. FRAME Signal Operation, FRM50=1 and FRMCNT=1 Clock (EPI0S31) (EPI0S28) (EPI0S29) Frame (EPI0S30) When FRMCNT=2, the FRAME signal transitions the rising edge of the WR or RD strobes for every third access, and so on for every value of FRMCNT, see Figure 11-27 on page 853.
Page 854: Register Map
EPIADDRMAP 0x0000.0000 EPI Address Map 0x020 EPIRSIZE0 0x0000.0003 EPI Read Size 0 0x024 EPIRADDR0 0x0000.0000 EPI Read Address 0 0x028 EPIRPSTD0 0x0000.0000 EPI Non-Blocking Read Data 0 0x030 EPIRSIZE1 0x0000.0003 EPI Read Size 1 June 18, 2014 Texas Instruments-Production Data...
Page 855 Tiva TM4C1294NCPDT Microcontroller Table 11-13. External Peripheral Interface (EPI) Register Map (continued) Offset Name Type Reset Description page 0x034 EPIRADDR1 0x0000.0000 EPI Read Address 1 0x038 EPIRPSTD1 0x0000.0000 EPI Non-Blocking Read Data 1 0x060 EPISTAT 0x0000.0000 EPI Status 0x06C EPIRFIFOCNT...
Page 856: Register Descriptions
External Peripheral Interface (EPI) 11.6 Register Descriptions This section lists and describes the EPI registers, in numerical order by address offset. June 18, 2014 Texas Instruments-Production Data...
Page 857: Register 1: Epi Configuration (Epicfg), Offset 0X000
Tiva TM4C1294NCPDT Microcontroller Register 1: EPI Configuration (EPICFG), offset 0x000 Important: The MODE field determines which configuration register is accessed for offsets 0x010 and 0x014. Any write to the EPICFG register resets the register contents at offsets 0x010 and 0x014.
Page 858 Control, address, and data pins are configured using the EPIHB8CFG and EPIHB8CFG2 registers. 16-Bit Host-Bus (HB16) Host-bus 16-bit interface (standard SRAM). Control, address, and data pins are configured using the EPIHB16CFG and EPIHB16CFG2 registers. 0x3-0xF Reserved June 18, 2014 Texas Instruments-Production Data...
Page 859: Register 2: Epi Main Baud Rate (Epibaud), Offset 0X004
Tiva TM4C1294NCPDT Microcontroller Register 2: EPI Main Baud Rate (EPIBAUD), offset 0x004 The system clock is used internally to the EPI Controller. The baud rate counter can be used to divide the system clock down to control the speed on the external interface. If the mode selected emits an external EPI clock, this register defines the EPI clock emitted.
Page 860 15:0 COUNT0 0x0000 Baud Rate Counter 0 This bit field contains a counter used to divide the system clock by the count. A count of 0 means the system clock is used as is. June 18, 2014 Texas Instruments-Production Data...
Page 861: Register 3: Epi Main Baud Rate (Epibaud2), Offset 0X008
Tiva TM4C1294NCPDT Microcontroller Register 3: EPI Main Baud Rate (EPIBAUD2), offset 0x008 The system clock is used internally to the EPI Controller. The baud rate counter can be used to divide the system clock down to control the speed on the external interface. If the mode selected emits an external EPI clock, this register defines the EPI clock emitted.
Page 862 This bit field is only valid when quad chip selects are enabled by setting the CSCFGEXT to 1 and the CSCFG field to 0x1 or 0x2. In addition, the CSBAUD bit must be set in the EPIHBnCFG2 register. June 18, 2014 Texas Instruments-Production Data...
Page 863: Register 4: Epi Sdram Configuration (Episdramcfg), Offset 0X010
Tiva TM4C1294NCPDT Microcontroller Register 4: EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPISDRAMCFG, the MODE field must be 0x1. The SDRAM Configuration register is used to specify several parameters for the SDRAM controller.
Page 864 SIZE Size of SDRAM The value of this field affects address pins and behavior. Value Description 64 megabits (8MB) 128 megabits (16MB) 256 megabits (32MB) 512 megabits (64MB) June 18, 2014 Texas Instruments-Production Data...
Page 865: Register 5: Epi Host-Bus 8 Configuration (Epihb8Cfg), Offset 0X010
Tiva TM4C1294NCPDT Microcontroller Register 5: EPI Host-Bus 8 Configuration (EPIHB8CFG), offset 0x010 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPIHB8CFG, the MODE field must be 0x2.
Page 866 26:24 reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 867 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description XFFEN External FIFO FULL Enable Value Description No effect. An external FIFO full signal can be used to control write cycles. If this bit is set and the FFULL full signal is high, XFIFO writes are stalled.
Page 868 This field is used in conjunction with the EPIBAUD register reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 869 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description MODE Host Bus Sub-Mode This field determines which of four Host Bus 8 sub-modes to use. Sub-mode use is determined by the connected external peripheral. See Table 11-8 on page 831 for information on how this bit field affects the operation of the EPI signals.
Page 870: Register 6: Epi Host-Bus 16 Configuration (Epihb16Cfg), Offset 0X010
EPI Host-Bus 16 Configuration (EPIHB16CFG) Base 0x400D.0000 Offset 0x010 Type RW, reset 0x0008.FF00 CLKGATE CLKINV RDYEN IRDYINV reserved XFFEN XFEEN WRHIGH RDHIGH ALEHIGH WRCRE RDCRE BURST CLKGATEI Type Reset MAXWAIT WRWS RDWS reserved BSEL MODE Type Reset June 18, 2014 Texas Instruments-Production Data...
Page 871 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description CLKGATE Clock Gated Value Description The EPI clock is free running. The EPI clock is held low. Note: A software application should only set the CLKGATE bit when there are no pending transfers or no EPI register access has been issued.
Page 872 EPIHBPSRAM register to the configuration register (CR) of the PSRAM. The WRCRE bit will self clear once the write-enabled CRE access is complete. Value Description No Action. Start CRE write transaction for CS0n. June 18, 2014 Texas Instruments-Production Data...
Page 873 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description RDCRE PSRAM Configuration Register Read Enables read of PSRAM configuration registers. With the RDCRE set, the next access is a read of the PSRAM's Configuration Register (CR). This bit self clears once the read-enabled CRE access is complete.
Page 874 Two EPI signals function as byte select signals to allow 8-bit transfers. See Table 11-9 on page 833 for details on which EPI signals are used. Note: If BSEL = 0, byte accesses cannot be executed. June 18, 2014 Texas Instruments-Production Data...
Page 875 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description MODE Host Bus Sub-Mode This field determines which of three Host Bus 16 sub-modes to use. Sub-mode use is determined by the connected external peripheral. See Table 11-9 on page 833 for information on how this bit field affects the operation of the EPI signals.
Page 876: Register 7: Epi General-Purpose Configuration (Epigpcfg), Offset 0X010
No clock output. EPI0S31 functions as the EPI clock output. The EPI clock is generated from the COUNT0 field in the EPIBAUD register (as is the system clock which is divided down from it). June 18, 2014 Texas Instruments-Production Data...
Page 877 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description CLKGATE Clock Gated Value Description The EPI clock is free running. The EPI clock is output only when there is data to write or read (current transaction); otherwise the EPI clock is held low.
Page 878 32 Bits Wide (EPI0S0 to EPI0S31) This size may not be used with an EPI clock. This value is normally used for acquisition input and actuator control as well as other general-purpose uses that require 32 bits per direction. June 18, 2014 Texas Instruments-Production Data...
Page 879: Register 8: Epi Host-Bus 8 Configuration 2 (Epihb8Cfg2), Offset 0X014
Tiva TM4C1294NCPDT Microcontroller Register 8: EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2), offset 0x014 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPIHB8CFG2, the MODE field of the EPICFG register must be 0x2.
Page 880: Table 11-14. Cscfgext + Cscfg Encodings
EPI0S34 is used as CS2n and EPI0S33 is used as CS3n. ALE with Quad CSn Configuration EPI0S30 is used as ALE, EPI0S26 is CS0n, and EPI0S27 is used as CS1n. EPI0S34 is used as CS2n and EPI0S33 is used as CS3n. Reserved June 18, 2014 Texas Instruments-Production Data...
Page 881 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description CSBAUD Chip Select Baud Rate and Multiple Sub-Mode Configuration enable This bit is only valid when the CSCFGEXT + CSCFG field is programmed to 0x2 or 0x3, 0x5 or 0x6. This bit configures the baud rate settings for CS0n, CS1n, CS2n, and CS3n.
Page 882 This field is used if the CSBAUD bit in the EPIHB8CFG2 register is enabled. Value Description The WRITE strobe for CS1n accesses is WRn (active Low). The WRITE strobe for CS1n accesses is WR (active High). June 18, 2014 Texas Instruments-Production Data...
Page 883 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description RDHIGH CS1n READ Strobe Polarity This field is used if the CSBAUD bit in the EPIHB8CFG2 register is enabled. Value Description The READ strobe for CS1n accesses is RDn (active Low). The READ strobe for CS1n accesses is RD (active High).
Page 884 If CSBAUD is clear, all chip-selects use the MODE configuration defined in the EPIHB8CFG register. Value Description ADMUX – AD[7:0] Data and Address are muxed. ADNONMUX – D[7:0] Data and address are separate. 0x2-0x3 reserved June 18, 2014 Texas Instruments-Production Data...
Page 885: Register 9: Epi Host-Bus 16 Configuration 2 (Epihb16Cfg2), Offset 0X014
Tiva TM4C1294NCPDT Microcontroller Register 9: EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2), offset 0x014 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPIHB16CFG2, the MODE field must be 0x3.
Page 886: Table 11-15. Cscfgext + Cscfg Encodings
EPI0S34 is used as CS2n and EPI0S33 is used as CS3n. ALE with Quad CSn Configuration EPI0S30 is used as ALE, EPI0S26 is CS0n, and EPI0S27 is used as CS1n. EPI0S34 is used as CS2n and EPI0S33 is used as CS3n. Reserved June 18, 2014 Texas Instruments-Production Data...
Page 887 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description CSBAUD Chip Select Baud Rate and Multiple Sub-Mode Configuration enable This bit is only valid when the CSCFGEXT + CSCFG field is programmed to 0x2 or 0x3, 0x5 or 0x6. This bit configures the baud rate settings for CS0n, CS1n, CS2n, and CS3n.
Page 888 This field is used if CSBAUD bit of the EPIHB16CFG2 register is enabled. Value Description The READ strobe for CS1n accesses is RDn (active Low). The READ strobe for CS1n accesses is RD (active High). June 18, 2014 Texas Instruments-Production Data...
Page 889 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description ALEHIGH CS1n ALE Strobe Polarity This field is used if CSBAUD bit of the EPIHB16CFG2 register is enabled. Value Description The address latch strobe for CS1n accesses is ALEn (active Low). The address latch strobe for CS1n accesses is ALE (active High).
Page 890 Active RDn is 8 EPI clocks reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 891 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description MODE CS1n Host Bus Sub-Mode This field determines which Host Bus 16 sub-mode to use for CS1n. Sub-mode use is determined by the connected external peripheral. See Table 11-9 on page 833 for information on how this bit field affects the operation of the EPI signals.
Page 892: Register 10: Epi Address Map (Epiaddrmap), Offset 0X01C
EPI Address Map (EPIADDRMAP) Base 0x400D.0000 Offset 0x01C Type RW, reset 0x0000.0000 reserved Type Reset reserved ECSZ ECADR EPSZ EPADR ERSZ ERADR Type Reset June 18, 2014 Texas Instruments-Production Data...
Page 893 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 31:12 reserved 0x0000.0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 894 Selects address mapping for external RAM area: Value Description Not mapped At 0x6000.0000 At 0x8000.0000 Only to be used with Host Bus quad chip select. In quad chip select mode, CS0n maps to 0x6000.0000 and CS1n maps to 0x8000.0000. June 18, 2014 Texas Instruments-Production Data...
Page 895: Register 11: Epi Read Size 0 (Epirsize0), Offset 0X020
Tiva TM4C1294NCPDT Microcontroller Register 11: EPI Read Size 0 (EPIRSIZE0), offset 0x020 Register 12: EPI Read Size 1 (EPIRSIZE1), offset 0x030 This register selects the size of transactions when performing non-blocking reads with the EPIRPSTDn registers. This size affects how the external address is incremented.
Page 896: Register 13: Epi Read Address 0 (Epiraddr0), Offset 0X024
EPI Read Address n (EPIRADDRn) Base 0x400D.0000 Offset 0x024 Type RW, reset 0x0000.0000 ADDR Type Reset ADDR Type Reset Bit/Field Name Type Reset Description 31:0 ADDR 0x0000.0000 Current Address Next address to read. June 18, 2014 Texas Instruments-Production Data...
Page 897: Register 15: Epi Non-Blocking Read Data 0 (Epirpstd0), Offset 0X028
Tiva TM4C1294NCPDT Microcontroller Register 15: EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028 Register 16: EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038 This register sets up a non-blocking read via the external interface. A non-blocking read is started by writing to this register with the count (other than 0). Clearing this register terminates an active non-blocking read as well as cancelling any that are pending.
Page 898 Reading this register provides the current count. A write of 0 cancels a non-blocking read (whether active now or pending). Prior to writing a non-zero value, this register must first be cleared. June 18, 2014 Texas Instruments-Production Data...
Page 899: Register 17: Epi Status (Epistat), Offset 0X060
Tiva TM4C1294NCPDT Microcontroller Register 17: EPI Status (EPISTAT), offset 0x060 This register indicates which non-blocking read register is currently active; it also indicates whether the external interface is busy performing a write or non-blocking read (it cannot be performing a blocking read, as the bus would be blocked and as a result, this register could not be accessed).
Page 900 ACTIVE Register Active Value Description If NBRBUSY is set, the EPIRPSTD0 register is active. If the NBRBUSY bit is clear, then neither EPIRPSTDx register is active. The EPIRPSTD1 register is active. June 18, 2014 Texas Instruments-Production Data...
Page 901: Register 18: Epi Read Fifo Count (Epirfifocnt), Offset 0X06C
Tiva TM4C1294NCPDT Microcontroller Register 18: EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C This register returns the number of values in the NBRFIFO (the data in the NBRFIFO can be read via the EPIREADFIFO register). A race is possible, but that only means that more values may come in after this register has been read.
Page 902: Register 19: Epi Read Fifo (Epireadfifo0), Offset 0X070
Reset DATA Type Reset Bit/Field Name Type Reset Description 31:0 DATA Reads Data This field contains the data that is at the top of the NBRFIFO. After being read, the NBRFIFO entry is removed. June 18, 2014 Texas Instruments-Production Data...
Page 903: Register 27: Epi Fifo Level Selects (Epififolvl), Offset 0X200
μDMA to insert more write data. It should be noted that the FIFO triggers are not identical to other such FIFOs in TM4C1294NCPDT peripherals. In particular, empty and full triggers are provided to avoid wait states when using blocking operations.
Page 904 Trigger when there are 4 or more entries in the NBRFIFO. Trigger when there are 6 or more entries in the NBRFIFO. Trigger when there are 7 or more entries in the NBRFIFO. Trigger when there are 8 entries in the NBRFIFO. reserved June 18, 2014 Texas Instruments-Production Data...
Page 905: Register 28: Epi Write Fifo Count (Epiwfifocnt), Offset 0X204
Tiva TM4C1294NCPDT Microcontroller Register 28: EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 This register contains the number of slots currently available in the WFIFO. This register may be used for polled writes to avoid stalling and for blocking reads to avoid excess stalling (due to undrained writes).
Page 906: Register 29: Epi Dma Transmit Count (Epidmatxcnt), Offset 0X208
15:0 TXCNT 0x0000 DMA Count This field is used to program the total number of transfers (byte, halfword or word) from the µDMA to the EPI WRFIFO. June 18, 2014 Texas Instruments-Production Data...
Page 907: Register 30: Epi Interrupt Mask (Epiim), Offset 0X210
Tiva TM4C1294NCPDT Microcontroller Register 30: EPI Interrupt Mask (EPIIM), offset 0x210 This register is the interrupt mask set or clear register. For each interrupt source (read, write, and error), a mask value of 1 allows the interrupt source to trigger an interrupt to the interrupt controller;...
Page 908 Error Interrupt Mask Value Description ERRIS in the EPIRIS register is masked and does not cause an interrupt. ERRIS in the EPIRIS register is not masked and can trigger an interrupt to the interrupt controller. June 18, 2014 Texas Instruments-Production Data...
Page 909: Register 31: Epi Raw Interrupt Status (Epiris), Offset 0X214
Tiva TM4C1294NCPDT Microcontroller Register 31: EPI Raw Interrupt Status (EPIRIS), offset 0x214 This register is the raw interrupt status register. On a read, it gives the current state of each interrupt source. A write has no effect. Note that raw status for read and write is set or cleared based on FIFO fullness as controlled by EPIFIFOLVL.
Page 910 To determine which error occurred, read the status of the EPI Error Interrupt Status and Clear (EPIEISC) register. This bit is cleared by writing a 1 to the bit in the EPIEISC register that caused the interrupt. June 18, 2014 Texas Instruments-Production Data...
Page 911: Register 32: Epi Masked Interrupt Status (Epimis), Offset 0X218
Tiva TM4C1294NCPDT Microcontroller Register 32: EPI Masked Interrupt Status (EPIMIS), offset 0x218 This register is the masked interrupt status register. On read, it gives the current state of each interrupt source (read, write, and error) after being masked via the EPIIM register. A write has no effect.
Page 912 An error has not occurred or the interrupt is masked. A WFIFO Full, a Read Stalled, or a Timeout error has occurred and the ERIM bit in the EPIIM register is set, triggering an interrupt to the interrupt controller. June 18, 2014 Texas Instruments-Production Data...
Page 913: Register 33: Epi Error And Interrupt Status And Clear (Epieisc), Offset 0X21C
Tiva TM4C1294NCPDT Microcontroller Register 33: EPI Error and Interrupt Status and Clear (EPIEISC), offset 0x21C This register is used to clear a pending error interrupt. Clearing any defined bit in the EPIEISC has no effect; setting a bit clears the error source and the raw error returns to 0. When any of bits[2:0] of this register are read as set, it indicates that the ERRRIS bit in the EPIRIS register is set and an EPI controller error is sent to the interrupt controller if the ERIM bit in the EPIIM register is set.
Page 914 MAXWAIT field (when not 0). Value Description No timeout error has occurred. A timeout error has occurred. Writing a 1 to this bit clears it, as well as the ERRRIS and ERIM bits. June 18, 2014 Texas Instruments-Production Data...
Page 915: Register 34: Epi Host-Bus 8 Configuration 3 (Epihb8Cfg3), Offset 0X308
Tiva TM4C1294NCPDT Microcontroller Register 34: EPI Host-Bus 8 Configuration 3 (EPIHB8CFG3), offset 0x308 Important: The MODE field in the EPICFG register configures whether EPI Host Bus mode is enabled. For EPIHB8CFG3 to be valid, the MODE field must be 0x2.
Page 916 This field is used in conjunction with the EPIBAUD2 register. reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 917 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description MODE CS2n Host Bus Sub-Mode This field determines which Host Bus 8 sub-mode to use for CS2n in multiple chip-select mode. Sub-mode use is determined by the connected external peripheral. See Table 11-8 on page 831 for information on how this bit field affects the operation of the EPI signals.
Page 918: Register 35: Epi Host-Bus 16 Configuration 3 (Epihb16Cfg3), Offset 0X308
This field is used if the CSBAUD bit is enabled in EPIHB16CFG2. Value Description The address latch strobe for CS2n accesses is ADVn (active Low). The address latch strobe for CS2n accesses is ALE (active High). June 18, 2014 Texas Instruments-Production Data...
Page 919 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description WRCRE CS2n PSRAM Configuration Register Write Used for PSRAM configuration registers. With WRCRE set, the next transaction by the EPI is a write of the CR bit field in the EPIHBPSRAM register to the configuration register (CR) of the PSRAM.
Page 920 This field is used in conjunction with the EPIBAUD2 register. reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 921 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description MODE CS2n Host Bus Sub-Mode This field determines which Host Bus 16 sub-mode to use for CS2n in multiple chip select mode. Sub-mode use is determined by the connected external peripheral. See Table 11-9 on page 833 for information on how this bit field affects the operation of the EPI signals.
Page 922: Register 36: Epi Host-Bus 8 Configuration 4 (Epihb8Cfg4), Offset 0X30C
High). 18:8 reserved 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 923 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description WRWS CS3n Write Wait States This field adds wait states to the data phase of CS3n accesses (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR).
Page 924 If CSBAUD is clear, all chip-selects use the MODE configuration defined in the EPIHB8CFG register. Value Description ADMUX – AD[7:0] Data and Address are muxed. ADNONMUX – D[7:0] Data and address are separate. 0x2-0x3 reserved June 18, 2014 Texas Instruments-Production Data...
Page 925: Register 37: Epi Host-Bus 16 Configuration 4 (Epihb16Cfg4), Offset 0X30C
Tiva TM4C1294NCPDT Microcontroller Register 37: EPI Host-Bus 16 Configuration 4 (EPIHB16CFG4), offset 0x30C Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB16CFG4 to be valid, the MODE field must be 0x3. EPI Host-Bus 16 Configuration 4 (EPIHB16CFG4) Base 0x400D.0000...
Page 926 Burst mode is enabled for CS3n. 15:8 reserved 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 927 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description WRWS CS3n Write Wait States This field adds wait states to the data phase of CS2n accesses (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR).
Page 928 Data and Address are muxed. ADNONMUX – D[15:0] Data and address are separate. This mode is not practical in HB16 mode for normal peripherals because there are generally not enough address bits available. 0x2-0x3 reserved June 18, 2014 Texas Instruments-Production Data...
Page 929: Register 38: Epi Host-Bus 8 Timing Extension (Epihb8Time), Offset 0X310
Tiva TM4C1294NCPDT Microcontroller Register 38: EPI Host-Bus 8 Timing Extension (EPIHB8TIME), offset 0x310 Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB8TIME to be valid, the MODE field must be 0x2. EPI Host-Bus 8 Timing Extension (EPIHB8TIME) Base 0x400D.0000...
Page 930 BURST mode. Value Description No change in the number of wait state clock cycles programmed in the RDWS field of EPIHB8CFG. Wait state value is now: RDWS - 1 RDWS field is programmed in EPIHB8CFG. June 18, 2014 Texas Instruments-Production Data...
Page 931: Register 39: Epi Host-Bus 16 Timing Extension (Epihb16Time), Offset 0X310
Tiva TM4C1294NCPDT Microcontroller Register 39: EPI Host-Bus 16 Timing Extension (EPIHB16TIME), offset 0x310 Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB16TIME to be valid, the MODE field must be 0x3. EPI Host-Bus 16 Timing Extension (EPIHB16TIME) Base 0x400D.0000...
Page 932 BURST mode. Value Description No change in the number of wait state clock cycles programmed in the RDWS field of EPIHB16CFG. Wait state value is now: RDWS - 1 RDWS field is programmed in EPIHB16CFG. June 18, 2014 Texas Instruments-Production Data...
Page 933: Register 40: Epi Host-Bus 8 Timing Extension (Epihb8Time2), Offset 0X314
Tiva TM4C1294NCPDT Microcontroller Register 40: EPI Host-Bus 8 Timing Extension (EPIHB8TIME2), offset 0x314 Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB8TIME2 to be valid, the MODE field must be 0x2. EPI Host-Bus 8 Timing Extension (EPIHB8TIME2) Base 0x400D.0000...
Page 934 BURST mode. Value Description No change in the number of wait state clock cycles programmed in the RDWS field of EPIHB8CFG2. Wait state value is now: RDWS - 1 RDWS field is programmed in EPIHB8CFG2. June 18, 2014 Texas Instruments-Production Data...
Page 935: Register 41: Epi Host-Bus 16 Timing Extension (Epihb16Time2), Offset 0X314
Tiva TM4C1294NCPDT Microcontroller Register 41: EPI Host-Bus 16 Timing Extension (EPIHB16TIME2), offset 0x314 Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB16TIME2 to be valid, the MODE field must be 0x3. EPI Host-Bus 16 Timing Extension (EPIHB16TIME2) Base 0x400D.0000...
Page 936 BURST mode. Value Description No change in the number of wait state clock cycles programmed in the RDWS field of EPIHB16CFG2. Wait state value is now: RDWS - 1 RDWS field is programmed in EPIHB16CFG2. June 18, 2014 Texas Instruments-Production Data...
Page 937: Register 42: Epi Host-Bus 8 Timing Extension (Epihb8Time3), Offset 0X318
Tiva TM4C1294NCPDT Microcontroller Register 42: EPI Host-Bus 8 Timing Extension (EPIHB8TIME3), offset 0x318 Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB8TIME3 to be valid, the MODE field must be 0x2. EPI Host-Bus 8 Timing Extension (EPIHB8TIME3) Base 0x400D.0000...
Page 938 BURST mode. Value Description No change in the number of wait state clock cycles programmed in the RDWS field of EPIHB8CFG3. Wait state value is now: RDWS - 1 RDWS field is programmed in EPIHB8CFG3. June 18, 2014 Texas Instruments-Production Data...
Page 939: Register 43: Epi Host-Bus 16 Timing Extension (Epihb16Time3), Offset 0X318
Tiva TM4C1294NCPDT Microcontroller Register 43: EPI Host-Bus 16 Timing Extension (EPIHB16TIME3), offset 0x318 Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB16TIME3 to be valid, the MODE field must be 0x3. EPI Host-Bus 16 Timing Extension (EPIHB16TIME3) Base 0x400D.0000...
Page 940 BURST mode. Value Description No change in the number of wait state clock cycles programmed in the RDWS field of EPIHB16CFG3. Wait state value is now: RDWS - 1 RDWS field is programmed in EPIHB16CFG3. June 18, 2014 Texas Instruments-Production Data...
Page 941: Register 44: Epi Host-Bus 8 Timing Extension (Epihb8Time4), Offset 0X31C
Tiva TM4C1294NCPDT Microcontroller Register 44: EPI Host-Bus 8 Timing Extension (EPIHB8TIME4), offset 0x31C Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB8TIME4 to be valid, the MODE field must be 0x2. EPI Host-Bus 8 Timing Extension (EPIHB8TIME4) Base 0x400D.0000...
Page 942 BURST mode. Value Description No change in the number of wait state clock cycles programmed in the RDWS field of EPIHB8CFG4. Wait state value is now: RDWS - 1 RDWS field is programmed in EPIHB8CFG4. June 18, 2014 Texas Instruments-Production Data...
Page 943: Register 45: Epi Host-Bus 16 Timing Extension (Epihb16Time4), Offset 0X31C
Tiva TM4C1294NCPDT Microcontroller Register 45: EPI Host-Bus 16 Timing Extension (EPIHB16TIME4), offset 0x31C Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB16TIME4 to be valid, the MODE field must be 0x3. EPI Host-Bus 16 Timing Extension (EPIHB16TIME4) Base 0x400D.0000...
Page 944 BURST mode. Value Description No change in the number of wait state clock cycles programmed in the RDWS field of EPIHB16CFG4. Wait state value is now: RDWS - 1 RDWS field is programmed in EPIHB16CFG4. June 18, 2014 Texas Instruments-Production Data...
Page 945: Register 46: Epi Host-Bus Psram (Epihbpsram), Offset 0X360
Tiva TM4C1294NCPDT Microcontroller Register 46: EPI Host-Bus PSRAM (EPIHBPSRAM), offset 0x360 This register holds the PSRAM configuration register value. When the WRCRE bit in the EPIHB16CFGn register is set, all 21 bits of the EPIHBPSRAM register's CR value are written to the PSRAM's configuration register.
Page 946: Cyclical Redundancy Check (Crc)
(CRCSEED) register at offset 0x410. Depending on the encoding of the INIT field in the CRCCTRL register, the value of the SEED field can initialized to any one of the following: ■ A unique context value written to the CRCSEED register (INIT=0x0) June 18, 2014 Texas Instruments-Production Data...
Page 947: Table 12-1. Endian Configuration
Tiva TM4C1294NCPDT Microcontroller ■ All 0s (INIT=0x2) ■ All 1s (INIT=0x3) Once the operation is done, software should read the result from the CRC Post Processing Result (CRCRSLTPP) register, offset 0x418, and a software channel μDMA interrupt should be used to identify completion.
Page 948: Initialization And Configuration
D7, D8, D9, D11, D12, D13, D14, D15, D16..}, then data should be fed to the CRC engine as follows: ■ If operating in Byte mode, the CRCDIN register should be written in the following order: 1. {00, 00, 00, D0} 2. {00, 00, 00, D1} 3. {00, 00, 00, D2} June 18, 2014 Texas Instruments-Production Data...
Page 949: Register Map
Tiva TM4C1294NCPDT Microcontroller 4. {00, 00, 00, D3} 5. {00, 00, 00, D4} 6. {00, 00, 00, D5} 7. {00, 00, 00, D6} 8..9..■ If operating in word mode, the CRCDIN register should be written in the following order: 1.
Page 950: Register 1: Crc Control (Crcctrl), Offset 0X400
RESINV Result Inverse Enable Value Description No effect Invert the result bits before storing in the CRCRSLTPP register. June 18, 2014 Texas Instruments-Production Data...
Page 951 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description Output Reverse Enable Refer to Table 12-2 on page 947 for more information regarding bit reversal. Value Description No change to result. Bit reverse the output result byte before storing to CRCRSLTPP register.
Page 952: Register 2: Crc Seed/Context (Crcseed), Offset 0X410
Bit/Field Name Type Reset Description 31:0 SEED 0x0000.0000 SEED/Context Value This register contains the starting seed of the CRC and checksum operation. This register also holds the latest result of CRC or checksum operation. June 18, 2014 Texas Instruments-Production Data...
Page 953: Register 3: Crc Data Input (Crcdin), Offset 0X414
Tiva TM4C1294NCPDT Microcontroller Register 3: CRC Data Input (CRCDIN), offset 0x414 The application or µDMA writes the CRC Data Input (CRCDIN) register with the next byte or word to compute. CRC Data Input (CRCDIN) Base 0x4403.0000 Offset 0x414 Type RW, reset 0x0000.0000...
Page 954: Register 4: Crc Post Processing Result (Crcrsltpp), Offset 0X418
CRC Post Processing Result (CRCRSLTPP) Base 0x4403.0000 Offset 0x418 Type RO, reset 0x0000.0000 RSLTPP Type Reset RSLTPP Type Reset Bit/Field Name Type Reset Description 31:0 RSLTPP 0x0000.0000 Post Processing Result This register contains the post-processed CRC result. June 18, 2014 Texas Instruments-Production Data...
Page 955: General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins. The TM4C1294NCPDT General-Purpose Timer Module (GPTM) contains 16/32-bit GPTM blocks. Each 16/32-bit GPTM block provides two 16-bit timers/counters (referred to as Timer A and Timer B) that can be configured to operate independently as timers or event counters, or concatenated to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
Page 956: Block Diagram
Block Diagram In the block diagram, the specific Capture Compare PWM (CCP) pins available depend on the TM4C1294NCPDT device. See Table 13-1 on page 956 for the available CCP pins and their timer assignments. Figure 13-1. GPTM Module Block Diagram 0xFFFF.FFFF (Up Counter Modes, 32-/64-bit)
Page 957: Signal Description
Tiva TM4C1294NCPDT Microcontroller Table 13-1. Available CCP Pins (continued) Timer Up/Down Counter Even CCP Pin Odd CCP Pin Timer A T3CCP0 16/32-Bit Timer 3 Timer B T3CCP1 Timer A T4CCP0 16/32-Bit Timer 4 Timer B T4CCP1 Timer A T5CCP0 16/32-Bit Timer 5...
Page 958: Functional Description
(GPTMTBMR) register (see page 982). When in one of the concatenated modes, Timer A and Timer B can only operate in one mode. However, when configured in an individual mode, Timer A and Timer B can be independently configured in any combination of the individual modes. June 18, 2014 Texas Instruments-Production Data...
Page 959: Gptm Reset Conditions
Tiva TM4C1294NCPDT Microcontroller 13.3.1 GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters Timer A and Timer B are initialized to all 1s, along with their corresponding registers: ■...
Page 960: Table 13-4. Counter Values When The Timer Is Enabled In Periodic Or One-Shot Modes
GPTM Timer n Prescale Match (GPTMTnPMR) registers. This interrupt has the same status, masking, and clearing functions as the time-out interrupt, but uses the match interrupt bits instead (for example, the raw interrupt status is monitored via TnMRIS bit in the GPTM Raw Interrupt Status June 18, 2014 Texas Instruments-Production Data...
Page 961: Table 13-5. 16-Bit Timer With Prescaler Configurations
Tiva TM4C1294NCPDT Microcontroller (GPTMRIS) register). Note that the interrupt status bits are not updated by the hardware unless the TnMIE bit in the GPTMTnMR register is set, which is different than the behavior for the time-out interrupt. The ADC trigger is enabled by setting the TnOTE bit in GPTMCTL and the event that activates the ADC is configured in the GPTM ADC Event (GPTMADCEV) register.
Page 962: Table 13-6. Counter Values When The Timer Is Enabled In Rtc Mode
To place the timer in Edge-Count mode, the TnCMR bit of the GPTMTnMR register must be cleared. The type of edge that the timer counts is June 18, 2014 Texas Instruments-Production Data...
Page 963: Table 13-7. Counter Values When The Timer Is Enabled In Input Edge-Count Mode
Tiva TM4C1294NCPDT Microcontroller determined by the TnEVENT fields of the GPTMCTL register. During initialization in down-count mode, the GPTMTnMATCHR and GPTMTnPMR registers are configured so that the difference between the value in the GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and GPTMTnPMR registers equals the number of edge events that must be counted.
Page 964: Figure 13-2. Input Edge-Count Mode Example, Counting Down
GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the CnEMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register. In this mode, the GPTMTnR and GPTMTnPS registers hold the time at which the selected input event occurred while June 18, 2014 Texas Instruments-Production Data...
Page 965: Figure 13-3. 16-Bit Input Edge-Time Mode Example
Tiva TM4C1294NCPDT Microcontroller the GPTMTnV register holds the free-running timer value. These registers can be read to determine the time that elapsed between the interrupt assertion and the entry into the ISR. In addition to generating interrupts, an ADC and/or a μDMA trigger can be generated. The ADC trigger is enabled by setting the TnOTE bit in GPTMCTL and the event that activates the ADC is configured in the GPTM ADC Event (GPTMADCEV) register.
Page 966: Table 13-9. Counter Values When The Timer Is Enabled In Pwm Mode
Figure 13-4 on page 967 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTMTnILR=0xC350 and the match value is GPTMTnMATCHR=0x411A. June 18, 2014 Texas Instruments-Production Data...
Page 967: Figure 13-4. 16-Bit Pwm Mode Example
Tiva TM4C1294NCPDT Microcontroller Figure 13-4. 16-Bit PWM Mode Example Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0xC350 0x411A Time TnEN set TnPWML = 0 Output Signal TnPWML = 1 When synchronizing the timers using the GPTMSYNC register, the timer must be properly configured to avoid glitches on the CCP outputs. Both the TnPLO and the TnMRSU bits must be set in the GPTMTnMR register.
Page 968: Wait-For-Trigger Mode
Note: If the application requires cyclical daisy-chaining, the TAWOT bit in the GPTMTAMR register of Timer 0 can be set. In this case, Timer 0 waits for a trigger from the last timer module in the chain. June 18, 2014 Texas Instruments-Production Data...
Page 969: Synchronizing Gp Timer Blocks
Tiva TM4C1294NCPDT Microcontroller Figure 13-8. Timer Daisy Chain GP Timer N+1 GPTMTnMR.TnWOT Timer B Timer B ADC Trigger Timer A Timer A ADC Trigger GP Timer N GPTMTnMR.TnWOT Timer B Timer B ADC Trigger Timer A Timer A ADC Trigger 13.3.5...
Page 970: Dma Operation
■ GPTM Timer A Value (GPTMTAV) register [15:0], see page 1014 ■ GPTM Timer B Value (GPTMTBV) register [15:0], see page 1015 ■ GPTM Timer A Match (GPTMTAMATCHR) register [15:0], see page 1006 ■ GPTM Timer B Match (GPTMTBMATCHR) register [15:0], see page 1007 June 18, 2014 Texas Instruments-Production Data...
Page 971: Initialization And Configuration
Tiva TM4C1294NCPDT Microcontroller In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a 32-bit read access to GPTMTAR returns the value:...
Page 972: Real-Time Clock (Rtc) Mode
■ In up-count mode, the timer counts from 0x0 to the value in the GPTMTnMATCHR and GPTMTnPMR registers. Note that when executing an up-count, the value of the GPTMTnPR and GPTMTnILR must be greater than the value of GPTMTnPMR and GPTMTnMATCHR. June 18, 2014 Texas Instruments-Production Data...
Page 973: Input Edge Time Mode
Tiva TM4C1294NCPDT Microcontroller 6. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 8. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
Page 974: Register Map
GPTMCFG 0x0000.0000 GPTM Configuration 0x004 GPTMTAMR 0x0000.0000 GPTM Timer A Mode 0x008 GPTMTBMR 0x0000.0000 GPTM Timer B Mode 0x00C GPTMCTL 0x0000.0000 GPTM Control 0x010 GPTMSYNC 0x0000.0000 GPTM Synchronize 0x018 GPTMIMR 0x0000.0000 GPTM Interrupt Mask June 18, 2014 Texas Instruments-Production Data...
Page 975: Register Descriptions
Tiva TM4C1294NCPDT Microcontroller Table 13-11. Timers Register Map (continued) Offset Name Type Reset Description page 0x01C GPTMRIS 0x0000.0000 GPTM Raw Interrupt Status 0x020 GPTMMIS 0x0000.0000 GPTM Masked Interrupt Status 0x024 GPTMICR 0x0000.0000 GPTM Interrupt Clear 1002 0x028 GPTMTAILR 0xFFFF.FFFF GPTM Timer A Interval Load...
Page 976: Register 1: Gptm Configuration (Gptmcfg), Offset 0X000
For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration. 0x2-0x3 Reserved For a 16/32-bit timer, this value selects the 16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. 0x5-0x7 Reserved June 18, 2014 Texas Instruments-Production Data...
Page 977: Register 2: Gptm Timer A Mode (Gptmtamr), Offset 0X004
Tiva TM4C1294NCPDT Microcontroller Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in PWM mode, set the TAAMS bit, clear the TACMR bit, and configure the TAMR field to 0x1 or 0x2.
Page 978 TAOTE bit in the GPTMCTL register and the CAEDMAEN bit in the GPTMDMAEV register, respectively. Value Description Capture event interrupt is disabled. Capture event interrupt is enabled. This bit is only valid in PWM mode. June 18, 2014 Texas Instruments-Production Data...
Page 979 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description TAILD GPTM Timer A Interval Load Write Value Description Update the GPTMTAR and GPTMTAV registers with the value in the GPTMTAILR register on the next cycle. Also update the GPTMTAPS register with the value in the GPTMTAPR register on the next cycle.
Page 980 To enable PWM mode, you must also clear the TACMR bit and configure the TAMR field to 0x1 or 0x2. TACMR GPTM Timer A Capture Mode The TACMR values are defined as follows: Value Description Edge-Count mode Edge-Time mode June 18, 2014 Texas Instruments-Production Data...
Page 981 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description TAMR GPTM Timer A Mode The TAMR values are defined as follows: Value Description Reserved One-Shot Timer mode Periodic Timer mode Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register.
Page 982: Register 3: Gptm Timer B Mode (Gptmtbmr), Offset 0X008
Clear CCP on Time-Out Set CCP on Time-Out Set CCP immediately and toggle on Time-Out Clear CCP immediately and toggle on Time-Out Set CCP immediately and clear on Time-Out Clear CCP immediately and set on Time-Out June 18, 2014 Texas Instruments-Production Data...
Page 983 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description TBCINTD One-Shot/Periodic Interrupt Disable Value Description Time-out interrupt functions normally Time-out interrupt functionality is disabled Note: Setting the TBCINTD bit in the GPTMTBMR register does not have an effect on the µDMA or ADC interrupt time-out event trigger assertions.
Page 984 GPTMDMAEV register or the TBTOADCEN bit is set in the GPTMADCEV register, a µDMA or ADC match trigger is not sent to the µDMA or ADC, respectively, when the TBMIE bit is clear. June 18, 2014 Texas Instruments-Production Data...
Page 985 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description TBCDIR GPTM Timer B Count Direction Value Description The timer counts down. The timer counts up. When counting up, the timer starts from a value of 0x0. When in PWM or RTC mode, the status of this bit is ignored. PWM mode always counts down and RTC mode always counts up.
Page 986: Register 4: Gptm Control (Gptmctl), Offset 0X00C
EMn bit in the ADCEMUX register (see page 1091). reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 987 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 11:10 TBEVENT GPTM Timer B Event Mode The TBEVENT values are defined as follows: Value Description Positive edge Negative edge Reserved Both edges Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed.
Page 988 Timer A continues counting while the processor is halted by the debugger. Timer A freezes counting while the processor is halted by the debugger. If the processor is executing normally, the TASTALL bit is ignored. June 18, 2014 Texas Instruments-Production Data...
Page 989 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description TAEN GPTM Timer A Enable The TAEN values are defined as follows: Value Description Timer A is disabled. Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register.
Page 990: Register 5: Gptm Synchronize (Gptmsync), Offset 0X010
A timeout event for Timer A of GPTM6 is triggered. A timeout event for Timer B of GPTM6 is triggered. A timeout event for both Timer A and Timer B of GPTM6 is triggered. June 18, 2014 Texas Instruments-Production Data...
Page 991 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description 11:10 SYNCT5 Synchronize GPTM Timer 5 Value Description GPTM5 is not affected. A timeout event for Timer A of GPTM5 is triggered. A timeout event for Timer B of GPTM5 is triggered.
Page 992 A timeout event for Timer A of GPTM0 is triggered. A timeout event for Timer B of GPTM0 is triggered. A timeout event for both Timer A and Timer B of GPTM0 is triggered. June 18, 2014 Texas Instruments-Production Data...
Page 993: Register 6: Gptm Interrupt Mask (Gptmimr), Offset 0X018
Tiva TM4C1294NCPDT Microcontroller Register 6: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Setting a bit enables the corresponding interrupt, while clearing a bit disables it. GPTM Interrupt Mask (GPTMIMR) 16/32-bit Timer 0 base: 0x4003.0000 16/32-bit Timer 1 base: 0x4003.1000...
Page 994 The RTCIM values are defined as follows: Value Description Interrupt is disabled. Interrupt is enabled. CAEIM GPTM Timer A Capture Mode Event Interrupt Mask The CAEIM values are defined as follows: Value Description Interrupt is disabled. Interrupt is enabled. June 18, 2014 Texas Instruments-Production Data...
Page 995 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description CAMIM GPTM Timer A Capture Mode Match Interrupt Mask The CAMIM values are defined as follows: Value Description Interrupt is disabled. Interrupt is enabled. TATOIM GPTM Timer A Time-Out Interrupt Mask The TATOIM values are defined as follows:...
Page 996: Register 7: Gptm Raw Interrupt Status (Gptmris), Offset 0X01C
The Timer B DMA transfer has completed. reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 18, 2014 Texas Instruments-Production Data...
Page 997 Tiva TM4C1294NCPDT Microcontroller Bit/Field Name Type Reset Description TBMRIS GPTM Timer B Match Raw Interrupt Value Description The match value has not been reached. The TBMIE bit is set in the GPTMTBMR register, and the match values in the GPTMTBMATCHR and (optionally) GPTMTBPMR registers have been reached when configured in one-shot or periodic mode.
Page 998 (0 or the value loaded into GPTMTAILR, depending on the count direction). This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR register. June 18, 2014 Texas Instruments-Production Data...
Page 999: Register 8: Gptm Masked Interrupt Status (Gptmmis), Offset 0X020
Tiva TM4C1294NCPDT Microcontroller Register 8: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register.
Page 1000 A Timer A Mode Match interrupt has not occurred or is masked. An unmasked Timer A Mode Match interrupt has occurred. This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR register. 1000 June 18, 2014 Texas Instruments-Production Data...