Texas Instruments Delfino TMS320F2837 S Series Manual

1 Device Overview
1.1 Features
1
• TMS320C28x 32-Bit CPU
– 200 MHz
– IEEE 754 Single-Precision Floating-Point
– Trigonometric Math Unit (TMU)
– Viterbi/Complex Math Unit (VCU-II)
• Programmable Control Law Accelerator (CLA)
– 200 MHz
– IEEE 754 Single-Precision Floating-Point
Executes Code Independently of Main CPU
• On-Chip Memory
– 512KB or 1MB of Flash (ECC-Protected)
– 132KB or 164KB of RAM (ECC or Parity)
– Dual-Zone Security Supporting Third-Party
Development
• Clock and System Control
– Two Internal Zero-Pin 10-MHz Oscillators
– On-Chip Crystal Oscillator and External Clock
Input
– Windowed Watchdog Timer Module
– Missing Clock Detection Circuitry
• 1.2-V Core, 3.3-V I/O Design
• System Peripherals
– Two External Memory Interfaces (EMIFs) With
ASRAM and SDRAM Support
– 6-Channel Direct Memory Access (DMA)
Controller
– Up to 169 Individually Programmable,
Multiplexed General-Purpose Input/Output
(GPIO) Pins With Input Filtering
– Hardware (HW) Interrupt Controller
– Multiple Low-Power Mode Support With External
Wakeup
– JTAG Emulation Connection
• Communications Peripherals
– USB 2.0 (MAC + PHY)
– Support for 12-Pin 3.3 V-Compatible Universal
Parallel Port (uPP) Interface
– Two Controller Area Network, D_CAN, Modules
(Pin-Bootable)
– Three High-Speed (40-MHz) SPI Ports
(Pin-Bootable)
– Two Multichannel Buffered Serial Ports
(McBSPs)
– Up to Four Serial Communications Interfaces
(SCIs) (Pin-Bootable)
2
– Two I C Interfaces (Pin-Bootable)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
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TMS320F2837xS Delfino™ Microcontrollers
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SPRS881A – AUGUST 2014 – REVISED JUNE 2015
• Analog Subsystem
– Up to Four Dual-Mode Analog-to-Digital
Converters (ADCs)
• 16-Bit Mode
– 1.1 MSPS Each (up to 4.4-MSPS
System)
– Differential
– Up to 12 External Channels
• 12-Bit Mode
– 3.5 MSPS Each (up to 14-MSPS System)
– Single-Ended
– Up to 24 External Channels
• Single Sample-and-Hold (S/H) on Each ADC
• HW Integrated Post-Processing of ADC
Conversions
– Saturating Offset Calibration
– Error From Setpoint Calculation
– High, Low, and Zero-Crossing Compare,
With Interrupt Capability
– Trigger-to-Sample Delay Capture
– Eight Windowed Comparators With 12-Bit
Digital-to-Analog Converter (DAC) References
– Three 12-Bit Buffered DAC Outputs
• Enhanced Control Peripherals
– Up to 24 PWM Channels With Enhanced
Features
– Up to 16 High-Resolution Pulse Width
Modulator (HRPWM) Channels
• High Resolution on Both A and B Channels
of 8 PWM Modules
• Dead-Band Support (on Both Standard and
High Resolution)
– Six Enhanced Capture (eCAP) Modules
– Up to Three Enhanced Quadrature Encoder
Pulse (eQEP) Modules
– Eight Sigma-Delta Filter Module (SDFM) Input
Channels, 2 Parallel Filters per Channel
• Standard SDFM Data Filtering
• Comparator Filter for Fast Action for Out of
Range
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