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7.7 DMA Bus State
7.7.1 Bus state types
DMAC bus cycles consist of the 13 states shown below.
(1) TI state
This is an idle state in which there is no access request.
The DMARQ3 to DMARQ0 signals are sampled at the rising edge of the VBCLK signal.
(2) T0 state
This is a DMA transfer ready state (There is a DMA transfer request, and the bus access right has been acquired
for the first DMA transfer).
(3) T1R state
This is the state to which the DMAC moves first for a 2-cycle transfer read.
Address driving begins. After the T1R state, the DMAC always transitions to the T2R state.
(4) T1RI state
This is a state in which the DMAC is awaiting an acknowledge signal for an external memory read request.
After the last T1RI state, the DMAC always transitions to the T2R state.
(5) T2R state
This is a wait state or the last state of a 2-cycle transfer read.
In the last T2R state, read data is sampled. After the read data is sampled, the DMAC always transitions to the
T1W state.
(6) T2RI state
This is a DMA transfer ready state for a DMA transfer to RAM (The bus access right has been acquired for a
DMA transfer to RAM).
After the last T2RI state, the DMAC always transitions to the T1W state.
(7) T1W state
This is the state to which the DMAC moves first for a 2-cycle transfer write.
Address driving begins. After the T1W state, the DMAC always transitions to the T2W state.
(8) T1WI state
This is a state in which the DMAC is awaiting an acknowledge signal for an external memory write request.
After the last T1WI state, the DMAC always transitions to the T2W state.
(9) T2W state
This is a wait state or the last state of a 2-cycle transfer write.
In the last T2W state, the write strobe signal is made inactive.
(10) T1FH state
This is the basic state of a flyby transfer and is the execution cycle of that transfer.
After the T1FH state, the DMAC transitions to the T2FH state.
CHAPTER 7 DMAC
Preliminary User's Manual A14874EJ3V0UM
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