Setting Oscillation Settling Time After Clearing Software Standby Mode; Table 19.2 Oscillation Settling Time Settings - Renesas H8SX/1520 Series Hardware Manual

32-bit cisc microcomputer

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Section 19 Power-Down Modes

Setting Oscillation Settling Time after Clearing Software Standby Mode

Bits STS4 to STS0 in SBYCR should be set as described below.

1. Using a crystal resonator

Set bits STS4 to STS0 so that the standby time is at least equal to the oscillation settling time.

Table 19.2 shows the standby times for operating frequencies and settings of bits STS4 to

2. Using an external clock

A PLL circuit settling time is necessary. Refer to table 19.2 to set the standby time.

STS4 STS3 STS2 STS1 STS0

: Recommended time setting when using a crystal resonator.

: Recommended time setting when using an external clock.

Pφ is the output from the peripheral module frequency divider.

Rev. 3.00 Mar. 14, 2006 Page 682 of 804

REJ09B0104-0300

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