Figure 12.1 Block Diagram Of Sci - Renesas H8SX/1520 Series Hardware Manual

32-bit cisc microcomputer

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Section 12 Serial Communication Interface (SCI)

Clocked Synchronous Mode:

• Data length: 8 bits

• Receive error detection: Overrun errors

Smart Card Interface:

• An error signal can be automatically transmitted on detection of a parity error during reception

• Data can be automatically re-transmitted on receiving an error signal during transmission

• Both direct convention and inverse convention are supported

Rev. 3.00 Mar. 14, 2006 Page 378 of 804

REJ09B0104-0300

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Parity generation

Parity check

Receive shift register

Receive data register

Transmit shift register

SCMR: Smart card mode register

Transmit data register

Serial mode register

Figure 12.1 Block Diagram of SCI

Module data bus

Transmission/

reception control

External clock

Serial control register

Serial status register

Bit rate register

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