Dma Channel Control Registers - Renesas M32R/ECU Series User Manual

9

9.2.1 DMA Channel Control Registers

DMA0 Channel Control Register 0 (DM0CNT0)
b0 1 2
MDSEL0 TREQF0 REQSL0
0 0 0
b Bit Name
0 MDSEL0
DMA0 transfer mode select bit
1 TREQF0
DMA0 transfer request flag bit
2, 3 REQSL0
DMA0 transfer request source select bit
4 TENL0
DMA0 transfer enable bit
5 TSZSL0
DMA0 transfer size select bit
6 SADSL0
DMA0 source address direction select bit
7 DADSL0
DMA0 destination address direction select bit
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA0 Channel Control Register 1 (DM0CNT1)
b8 9 10
0 0 0
b Bit Name
8–11 No function assigned. Fix to "0".
12–15 REQESEL0
Extended DMA0 transfer request source select bit
3 4 5 6
TENL0 TSZSL0 SADSL0 DADSL0
0 0 0 0
11 12 13 14
REQESEL0
0 0 0 0
b7
0
Function
0: Normal mode
1: Ring buffer mode
0: Transfer not requested
1: Transfer requested
00: Software start or one DMA2 transfer completed
01: A-D0 conversion completed
10: MJT (TIO8_udf)
11: Extended DMA0 transfer request source select
(DMA0 Channel Control Register 1)
0: Disable transfer
1: Enable transfer
0: 16 bits
1: 8 bits
0: Fixed
1: Increment
0: Fixed
1: Increment
b15
0
Function
0000: MJT (input event bus 2)
0001: MJT (TID0_udf/ovf)
0010: CAN (CAN0_S0/S15)
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Settings inhibited
| |
1111: Settings inhibited
9-6
9.2 DMAC Related Registers
<Address: H'0080 0410>
<After reset: H'00>
<Address: H'0080 0411>
<After reset: H'00>
32180 Group User's Manual (Rev.1.0)
DMAC
R W
R W
R(Note 1)
R W
R W
R W
R W
R W
R W
0 0
R W