Effective Address Calculation; Figure 2.12 Branch Address Specification In Memory Indirect Mode - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Note that the first part of the address range is also the exception vector area. For further details,

refer to section 4, Exception Handling.

If an odd address is specified in word or longword memory access, or as a branch address, the

least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched

at the address preceding the specified address. (For further information, see section 2.5.2, Memory

Data Formats.)

Note: Normal mode is not available in this LSI.

Note: * Normal mode is not available in this LSI.

Effective Address Calculation

Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal

mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.

Note: Normal mode is not available in this LSI.

Branch address

(a) Normal Mode

Branch address

(b) Advanced Mode

Rev. 6.00 Mar 15, 2006 page 45 of 570

Section 2 CPU

REJ09B0211-0600