Dmac Activation By Interrupt; Figure 5.6 Block Diagram Of Dmac And Interrupt Controller; Table 5.5 Number Of Execution States In Interrupt Handling Routine - Renesas H8SX/1500 Series Hardware Manual

Section 5 Interrupt Controller
Table 5.5 Number of Execution States in Interrupt Handling Routine
Symbol
Vector fetch S
h
Instruction fetch S
I
Stack manipulation S
[Legend]
m: Number of wait cycles in an external device access.
5.6.5

DMAC Activation by Interrupt

The DMAC can be activated by an interrupt. In this case, the following options are available:
• Interrupt request to the CPU
• Activation request to the DMAC
• Combination of the above
For details on interrupt requests that can be used to activate the DMAC, see table 5.2 and
section 7, DMA Controller (DMAC).
Figure 5.6 shows a block diagram of the DMAC and interrupt controller.
Interrupt request
On-chip
peripheral
Interrupt request
module clear signal
Interrupt request
IRQ
Interrupt request clear signal
interrupt
Interrupt controller

Figure 5.6 Block Diagram of DMAC and Interrupt Controller

Rev. 3.00 Mar. 14, 2006 Page 118 of 804
REJ09B0104-0300
8-Bit Bus
On-Chip 2-State
Memory Access
1 8
1 4
2 8
K
Select signal
DMAC
select
circuit
Object of Access
External Device
16-Bit Bus
3-State 2-State
Access Access
12 + 4m 4
6 + 2m 2
12 + 4m 4
DMRSR0 TO DMRSR3
DMAC activation request signal
DMAC request clear signal
CPU
select
circuit
32-Bit Bus
3-State 2-State
Access Access
6 + 2m 2
3 + m 2
6 + 2m 2
Control signal
CPU interrupt request
vector number
Priority
decision
I, I2 to I0
3-State
Access
3 + m
3 + m
3 + m
DMAC
CPU