Figure 13.1 Block Diagram Of The Dmac - Renesas HD6417641 Hardware Manual

Section 13 Direct Memory Access Controller (DMAC)
• Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND
can be set independently.
Figure 13.1 shows the block diagram of the DMAC.
X/Y memory
On-chip
peripheral module
DMA transfer request signal
DMA transfer acknowledge signal
Interrupt controller
External ROM
External RAM
External device
(memory mapped)
External device
(with acknowledge-
ment)
DACK0, DACK1
TEND
DREQ0 , DREQ1
[Legend]
DMA source address register
SAR_n:
DMA destination address register
DAR_n:
DMATCR_n: DMA transfer count register
CHCR_n: DMA channel control register
DMA operation register
DMAOR:
DMA extension resource selector
DMARS0,1:
DMA transfer end interrupt request to the CPU
DEIn:
n: 0, 1, 2, 3
Rev. 4.00 Sep. 14, 2005 Page 406 of 982
REJ09B0023-0400
DEIn
Bus state
controller

Figure 13.1 Block Diagram of the DMAC

DMAC module
Iteration
control
Register
control
DMATCR_n
Start-up
control
Request
DMARS0,1
priority
control
Bus
interface
SAR_n
DAR_n
CHCR_n
DMAOR