Figure 13.18 Bsc Ordinary Memory Access (No Wait, Idle Cycle 1, Longword Access To 16-Bit Device) - Renesas HD6417641 Hardware Manual

To execute a longword access to an 8-bit or 16-bit external device or to execute a word access to
an 8-bit external device, the DACK and TEND outputs are divided for data alignment as shown in
figure 13.18.
Read
Write
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
CKIO
Address
CSn
RD
D15 to D0
WEn
D15 to D0
DACKn
(Active low)
TENDn
(Active low)
WAIT
Note: TEND is asserted for the last transfer unit of DMA transfers.
If a transfer unit is divided into multiple bus cycles and
if CSn is negated during the bus cycle, TEND is also divided.
Figure 13.18 BSC Ordinary Memory Access
Section 13 Direct Memory Access Controller (DMAC)
T T T T
1 2 aw 1
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T
2
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