Circular Buffer Operation Example 2; Bit-Reverse Addressing - Analog Devices adsp-2100 Manual

4 Data Transfer

4.2.4.4 Circular Buffer Operation Example 2

Assume that I0 = 9, M0 = 3, L0 = 5, and the base address = 8. The
five-word buffer resides at locations 8 through 12 inclusive. The next
address is calculated as:
(I0 + M0 – B) mod L0 + B = (9 + 3 – 8) mod 5 + 8 = 12
The successive address calculations using I0 for indirect addressing
produce the sequence: 9, 12, 10, 8, 11, 9 ... This example highlights the fact
that the address sequence does not have to result in a "direct hit" of the
buffer boundary.
4.2.5

Bit-Reverse Addressing

The bit-reverse logic is primarily intended for use in FFT computations
where inputs are supplied or the outputs generated in bit-reversed order.
Bit-reversing is available only on addresses generated by DAG1. The pivot
point for the reversal is the midpoint of the 14-bit address, between bits 6
and 7. This is illustrated in the following chart.
Normal Order
Bit-reversed
Bit-reversed addressing is a mode, enabled and disabled by setting a
mode bit in the mode status register (MSTAT). When enabled, all
addresses generated using index registers I0-3 are bit-reversed upon
output. (The modified valued stored back after post-update remains in
normal order.) This mode continues until the status bit is reset.
It is possible to bit-reverse address values less than 14 bits wide. You must
determine the first address and also initialize the M register to be used
with a value calculated to modify the I register bit-reversed output to the
desired range. This value is:
(14 – N)
2
where N is the number of bits you wish to output reversed. For a
complete example of this, refer to Section 6.6.5.2 "Modified Butterfly" in
Chapter 6, One-Dimensional FFTs, of the applications handbook Digital
Signal Processing Applications Using the ADSP-2100 Family (Volume 1).
4 – 6
Individual address lines (ADDR
13 12 11 10 09 08 07 06 05 04 03 02 01 00
00 01 02 03 04 05 06 07 08 09 10 11 12 13
)
N