Motorola PowerQUICC II MPC8280 Series Reference Manual page 452

Register Descriptions
Table 11-2. BADDR Connections (continued)
64/72-Bit Port
BADDR[x]
Size SDRAM
BADDR[30] N.C.
BADDR[31] N.C.
11.3 Register Descriptions
Table 11-3 lists registers used to control the 60x bus memory controller.
Table 11-3. 60x Bus Memory Controller Registers
Abbreviation
BR0–BR11
OR0–OR11]
PSDMR
LSDMR
MAMR
MBMR
MCMR
MDR
MAR
MPTPR
PURT
PSRT
LURT
LSRT
TESCRx
LTESCRx
11.3.1 Base Registers (BRx)
The base registers (BR0–BR11) contain the base address and address types that the memory
controller uses to compare the address bus value with the current address accessed. Each
register also includes a memory attribute and selects the machine for memory operation
handling. Figure 11-7 shows the BRx register format.
11-14
Freescale Semiconductor, Inc.
Non-SDRAM
32-Bit Port
64-/72-Bit Port
Size SDRAM
Size Device
N.C N.C.
N.C N.C.
Name
Base register banks 0–11
Option register banks 0–11
60x bus SDRAM machine mode register
Local bus SDRAM machine mode register
UPMA mode register
UPMB mode register
UPMC mode register
Memory data register
Memory address register
Memory refresh timer prescaler register
60x bus assigned UPM refresh timer
60x bus assigned SDRAM refresh timer
Local bus assigned UPM refresh timer
Local bus assigned SDRAM refresh timer
60x bus error status and control registers
Local bus error status and control regs
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
Non-SDRAM Any 16-Bit
32-Bit Port Port Size
Size Device Device
N.C Connected
N.C. N.C.
Reference
Section 11.3.1
Section 11.3.2
Section 11.3.3
Section 11.3.4
Section 11.3.5
Section 11.3.6
Section 11.3.7
Section 11.3.12
Section 11.3.8
Section 11.3.10
Section 11.3.9
Section 11.3.11
Section 11.3.13
Section 11.3.14
Any 8-Bit Port
Size Device
Connected
Connected
MOTOROLA