Motorola PowerQUICC II MPC8280 Series Reference Manual page 459

0
Field
Reset
R/W
Addr 0x10104 (OR0); 0x1010C (OR1); 0x10114 (OR2); 0x1011C (OR3); 0x10124 (OR4); 0x1012C (OR5); 0x10134
(OR6); 0x1013C (OR7); 0x10144 (OR8); 0x1014C (OR9); 0x10154 (OR10); 0x1015C (OR11)
16 17 18
Field ...AM —
Reset
R/W
Addr 0x10106 (OR0); 0x1010E (OR1); 0x10116 (OR2); 0x1011E (OR3); 0x10126 (OR4); 0x1012E (OR5); 0x10136
(OR6); 0x1013E (OR7); 0x10146 (OR8); 0x1014E (OR9); 0x10156 (OR10); 0x1015E (OR11)
1
Reset values are for OR0 only. OR1–11 are undefined at reset.
Table 11-7 describes the ORx fields in UPM mode.
Table 11-7. Option Register (ORx)—UPM Mode
Bits Name
0–16 AM Address mask. Provides masking for corresponding BRx bits. By masking address bits
independently, external devices of different size address ranges can be used. Any clear bit masks
the corresponding address bit. Any set bit causes the corresponding address bit to be used in the
comparison with the address pins. Address mask bits can be set or cleared in any order in the field,
allowing a resource to reside in more than one area of the address map. AM can be read or written
at any time.
17–18 — Reserved, should be cleared.
19 BCTLD Data buffer control disable. Disables the assertion of BCTLx (60x bus) and LWR (local bus) during
an access to the current memory bank. See Section 11.2.7, "Data Buffer Controls (BCTLx and
LWR)."
0 BCTLx and LWR are asserted upon an access to the current memory bank.
1 BCTLx and LWR are not asserted upon an access to the current memory bank.
20–22 — Reserved, should be cleared.
23 BI Burst inhibit. Indicates if this memory bank supports burst accesses.
0 The bank supports burst accesses
1 The bank does not support burst accesses. The UPMx executes burst accesses as series of
single accesses.
24–28 — Reserved, should be cleared.
29–30 EHTR Extended hold time on read accesses. Indicates how many cycles are inserted between a read
access from the current bank and the next access.
00 Normal timing is generated by the memory controller. No additional cycles are inserted.
01 One idle clock cycle is inserted.
10 Four idle clock cycles are inserted.
11 Eight idle clock cycles are inserted.
31 — Reserved, should be cleared.
MOTOROLA
Freescale Semiconductor, Inc.
0000_0000_0000_0000
19 20 22
BCTLD —
0000_0000_0000_0000
Figure 11-9. ORx—UPM Mode
Chapter 11. Memory Controller
For More Information On This Product,
Go to: www.freescale.com
AM...
1
R/W
23 24
BI —
1
R/W
Description
Register Descriptions
15
28 29 30 31
EHTR —
11-21