Motorola PowerQUICC II MPC8280 Series Reference Manual page 453

0
Field
Reset
R/W
Addr 0x10100 (BR0); 0x10108 (BR1); 0x10110 (BR2); 0x10118 (BR3); 0x10120 (BR4); 0x10128 (BR5);
0x10130 (BR6); 0x10138 (BR7); 0x10140 (BR8); 0x10148 (BR9); 0x10150 (BR10); 0x10158 (BR11)
16 17 18
Field BA —
Reset 000
R/W
Addr 0x10102 (BR0); 0x1010A (BR1); 0x10112 (BR2); 0x1011A (BR3); 0x10122 (BR4); 0x1012A (BR5);
0x10132 (BR6); 0x1013A (BR7); 0x10142 (BR8); 0x1014A (BR9); 0x10152 (BR10); 0x1015A (BR11)
1
For BR0 these fields depend on reset configuration sequence. See Section 5.4.1, "Hard Reset Configuration Word."
For BR1–11, these fields are cleared at reset.
Table 11-4 describes BRx fields.
Bits Name
0–16 BA Base address. The upper 17 bits of each base address register are compared to the address on the
address bus to determine if the bus master is accessing a memory bank controlled by the memory
controller. Used with ORx[BSIZE].
17–18 — Reserved, should be cleared.
19–20 PS Port size. Specifies the port size of this memory region.
01 8-bit
10 16-bit
11 32-bit
00 64-bit (60x bus only)
21–22 DECC Data error correction and checking. Specifies the method for data error checking and correction.
See Section 11.2.3, "Error Checking and Correction (ECC)," and Section 11.2.4, "Parity Generation
and Checking."
00 Data errors checking disabled
01 Normal parity checking
10 Read-modify-write parity checking
11 ECC correction and checking
23 WP Write protect. Can restrict write accesses within the address range of a BR. An attempt to write to
this address range while WP = 1 can cause TEA to be asserted by the bus monitor logic (if
enabled) which terminates the cycle.
0 Read and write accesses are allowed.
1 Only read accesses are allowed. The memory controller does not assert CSx and PSDVAL on
write cycles to this memory bank. TESCR1[WP] or L_TESCR1[WP] (depending on which bus is
being used) is set if a write to this memory bank is attempted.
MOTOROLA
Freescale Semiconductor, Inc.
0000_0000_0000_0000
19 20 21 22 23
1
PS DECC WP
see note
0000_000
Figure 11-6. Base Registers (BRx)
Table 11-4. BRx Field Descriptions
Chapter 11. Memory Controller
For More Information On This Product,
Go to: www.freescale.com
BA
R/W
24 26 27
1
MS EMEMC
see note
R/W
Description
Register Descriptions
15
28 29 30 31
1
ATOM DR V
see note
000
11-15