Motorola PowerQUICC II MPC8280 Series Reference Manual page 454

Register Descriptions
Table 11-4. BRx Field Descriptions (continued)
Bits Name
24–26 MS Machine select. Specifies machine select for the memory operations handling and assigns the bank
to the 60x or local bus if GPCM or SDRAM are selected. If UPMx is selected, the bus assignment
is determined by MxMR[BSEL].
000 GPCM—60x bus (reset value)
001 GPCM—local bus
010 SDRAM—60x Bus
011 SDRAM—local bus
100 UPMA
101 UPMB
110 UPMC
111 Reserved
27 EMEMC External MEMC enable. Overrides MS and assigns the bank to the 60x bus. However, other BRx
fields remain in effect. See Section 11.2.10, "External Memory Controller Support."
0 Access are handled by the memory controller according to MS.
1 Access are handled by an external memory controller (or other slave) on the 60x bus. The
external memory controller is expected to assert AACK, TA, and PSDVAL.
28–29 ATOM Atomic operation. See Section 11.2.8, "Atomic Bus Operation."
00 The address space controlled by the memory controller bank is not used for atomic operations.
01 Read-after-write-atomic (RAWA).Writes to the address space handled by the memory controller
bank cause the MPC8280 to lock the bus for the exclusive use of the master. The lock is
released when the master performs a read operation from this address space. This feature is
intended for CAM operations.
10 Write-after-read-atomic (WARA). Reads from the address space handled by the memory
controller bank cause the MPC8280 to lock the bus for the exclusive use of the accessing
device. The lock is released when the device performs a write operation to this address space.
11 Reserved
Note: If the device fails to release the bus, the lock is released after 256 clock cycles.
30 DR Data pipelining. See Section 11.2.9, "Data Pipelining."
0 No data pipelining is done.
1 Data beats of accesses to the address space controlled by the memory controller bank are
delayed by one cycle. This feature is intended for memory regions that use ECC or parity checks
and need to improve data setup time.
31 V Valid bit. Indicates that the contents of the BRx and ORx pair are valid. The CS signal does not
assert until V is set.
0 This bank is invalid.
1 This bank is valid
Note: An access to a region that has no V bit set may cause a bus monitor time-out. After a system
reset, BR0[V] is set.
Note: Note: If BRx has been selected as the SDRAM controller and BRx[31] has been set, the
SDRAM controller must be invalidated by doing the following:
1. Disable the SDRAM refresh service by clearing PSDMR/LSDMR[RFEN].
2. Wait at least 100 60x-bus clock cycles.
3. Clear BRx[V].
11.3.2 Option Registers (ORx)
The ORx registers define the sizes of memory banks and access attributes. The ORx
attributes bits support the following three modes of operation as defined by BR[MS].
• SDRAM mode
11-16
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