Signal Descriptions - Texas Instruments MSPM0G350 Series Manual

MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1
SLASF88 – OCTOBER 2023
PIN
PINCMx
NAME
ANALOG
56 PB25 A0_4
57 PB26 COMP1_IN0+
58 PB27 COMP1_IN0-
(1) Set PINCM.PF and PINCM.PC in
digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired
Pin Function using the PINCM.PF control bits.
(2) Standard with Wake allows the I/O to wake up the device from the lowest low-power mode of SHUTDOWN. All I/O can be configured
to wakeup the MCU from higher low-power modes. See section GPIO FastWake in the
Technical Reference Manual
IO STRUCTURE
Standard drive
(2)
Standard drive with wake
High drive
High speed
5-V tolerant open drain

6.3 Signal Descriptions

SIGNAL
FUNCTION
NAME
A0_0
A0_1
A0_2
A0_3
A0_4
A0_5
A0_6
A0_7
ADC A0_12
A1_0
A1_1
A1_2
A1_3
A1_4
A1_5
A1_6
A1_7
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Table 6-1. Pin Attributes (continued)
SIGNAL NAMES
DIGITAL [PIN FUNCTION]
UART0_CTS [2] / SPI0_CS0 [3] / TIMA_FAL2 [4]
UART0_RTS [2] / SPI0_CS1 [3] / TIMA0_C3 [4] /
TIMG6_C0 [5] / [6]
COMP2_OUT [2] / SPI1_CS1 [3] / TIMA0_C3N [4] /
TIMG6_C1 [5] / TIMA1_C1 [6]
IOMUX to 0 for analog functions (for example, OPA inputs or outputs, and COMP inputs). Each
for details.
Table 6-2. Digital IO Features by IO Type
INVERSION
CONTROL
Y
Y
Y
Y
Y
Table 6-3. Signal Descriptions
(1)
PIN NO.
48 PT, 32 28
64 PM
RGZ RHB DGS28
31 47 31 2
30 46 30 1
26 45 29 28
25 44 28 27
27 – – –
23 42 – –
19 41 – –
18 40 26 25
7 29 18 17
8 30 19 18
9 31 20 19
10 32 21 20
11 33 22 21
14 36 – –
15 37 – –
16 38 – –
17 39 25 24
Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
(1)
MSPM0 G-Series 80-MHz Microcontrollers
DRIVE
HYSTERESIS
STRENGTH
CONTROL
CONTROL
Y
Y
Y
PIN TYPE
24
(2)
RGE
– I
22 I
21 I
20 I
– I
– I
– I
18 I
– I
11 I
12 I
13 I
14 I
– I
– I
– I
17 I
PIN NUMBER
27 – – – -
28 – – – 22
29 – – – -
PULLUP PULLDOWN
RESISTOR RESISTOR
Y Y
Y Y
Y Y
Y Y
Y
DESCRIPTION
ADC0 analog input 0
ADC0 analog input 1
ADC0 analog input 2
ADC0 analog input 3
ADC0 analog input 4
ADC0 analog input 5
ADC0 analog input 6
ADC0 analog input 7
ADC0 analog input 12
ADC1 analog input 0
ADC1 analog input 1
ADC1 analog input 2
ADC1 analog input 3
ADC1 analog input 4
ADC1 analog input 5
ADC1 analog input 6
ADC1 analog input 7
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IO
STRUCTU
RE
Standard
Standard
Standard
WAKEUP
LOGIC
Y
Y
Y