Renesas RL78/G15 User Manual
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Renesas RL78/G15 User Manual

Renesas RL78/G15 User Manual

16-bit single-chip microcontrollers
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RL78/G15
16
16-Bit Single-Chip Microcontrollers
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
User's Manual: Hardware
Rev.1.10 Mar, 2023

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Summary of Contents for Renesas RL78/G15

  • Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
  • Page 2 Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document.
  • Page 3 Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
  • Page 4 How to Use This Manual Readers This manual is intended for user engineers who wish to understand the functions of the RL78/G15 and design and develop application systems and programs for these devices. The target products are as follows. ●...
  • Page 5 For the documentation of PG-FP6, see the website below. https://www.renesas.com/us/en/software-tool/pg-fp6 Note 2. For the documentation of Renesas Flash Programmer, see the website below. https://www.renesas.com/us/en/software-tool/renesas-flash-programmer-programming-gui Caution The related documents listed above are subject to change without notice. Be sure to use the...
  • Page 6 All trademarks and registered trademarks are the property of their respective owners. EEPROM is a trademark of Renesas Electronics Corporation. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan.

  • Page 7: Table Of Contents

    Table of Contents CHAPTER 1 OUTLINE ....................19 Features ............................19 List of Part Numbers ........................22 Pin Configuration (Top View) ......................24 1.3.1 8-pin products ........................24 1.3.2 10-pin products ........................25 1.3.3 16-pin products ........................26 1.3.4 20-pin products ........................29 Pin Identification ..........................
  • Page 8 3.3.2 General-purpose registers ....................68 3.3.3 ES and CS registers ......................69 3.3.4 Special function registers (SFRs) ..................70 3.3.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) ..... 73 Instruction Address Addressing ...................... 78 3.4.1 Relative addressing ......................78 3.4.2 Immediate addressing ......................
  • Page 9 4.5.2 Register settings for alternate function whose output function is not used ....... 117 4.5.3 Register setting examples for used port and alternate functions ........118 Cautions When Using Port Function .................... 127 4.6.1 Cautions on 1-bit manipulation instruction for port register n (Pn) ........127 4.6.2 Notes on specifying the pin settings ..................
  • Page 10 6.3.1 Peripheral enable register 0 (PER0) .................. 178 6.3.2 Timer clock select register m (TPSm) ................179 6.3.3 Timer mode register mn (TMRmn) ..................183 6.3.4 Timer status register mn (TSRmn) ..................189 6.3.5 Timer channel enable status register m (TEm) ..............190 6.3.6 Timer channel start register m (TSm) ................
  • Page 11 6.9.4 Operation as two-channel input with one-shot pulse output function ........ 290 6.10 Cautions When Using Timer Array Unit ..................299 6.10.1 Cautions when using timer output ..................299 CHAPTER 7 12-BIT INTERVAL TIMER ..............300 Functions of 12-bit Interval Timer ....................300 Configuration of 12-bit Interval Timer ...................
  • Page 12 10.3.5 8-bit A/D conversion result register (ADCRH) ..............328 10.3.6 Analog input channel specification register (ADS) ............. 329 10.3.7 A/D test register (ADTES) ....................330 10.3.8 Registers controlling port function of analog input pins ............. 330 10.4 A/D Converter Conversion Operations ..................331 10.5 Input Voltage and Conversion Results ..................
  • Page 13 11.4 Comparator n Operation (n = 0, 1) ....................357 11.4.1 Comparator n Digital Filter Operation (n = 0, 1)..............358 11.4.2 Comparator n Interrupt Operation (n = 0, 1) ..............358 11.4.3 Comparator n Output (n = 0, 1) ..................358 11.5 Comparator Setting Flowcharts ....................
  • Page 14 12.5.6 Slave Transmission/Reception ..................444 12.5.7 Calculating Transfer Clock Frequency ................455 12.5.8 Procedure for Processing Errors that Occurred During Simplified SPI (CSI00, CSI01) Communication ........................457 12.6 Operation of UART (UART0) Communication ................458 12.6.1 UART Transmission ......................460 12.6.2 UART Reception ........................
  • Page 15 13.5.9 Address match detection method ..................541 13.5.10 Error detection ........................541 13.5.11 Extension code ........................542 13.5.12 Arbitration ........................... 543 13.5.13 Wakeup function ........................ 545 13.5.14 Communication reservation ....................548 13.5.15 Cautions ..........................552 13.5.16 Communication operations ....................554 13.5.17 I C interrupt request (INTIICA0) generation timing ............
  • Page 16 CHAPTER 17 SELECTABLE POWER-ON-RESET CIRCUIT ........644 17.1 Functions of Selectable Power-on-reset Circuit ................644 17.2 Configuration of Selectable Power-on-reset Circuit ..............645 17.3 Operation of Selectable Power-on-reset Circuit ................646 17.4 Cautions for Selectable Power-on-reset Circuit ................647 CHAPTER 18 OPTION BYTE ..................648 18.1 Functions of Option Bytes ......................
  • Page 17 19.6.2 Procedure for executing self-programming of code/data flash memory ......678 19.6.3 Notes on self-programming ....................681 19.7 Data Flash ............................ 682 19.7.1 Data flash overview ......................682 19.7.2 Procedure for accessing data flash memory ..............682 CHAPTER 20 ON-CHIP DEBUG FUNCTION ............... 683 20.1 Connecting E2, E2 Lite On-chip Debugging Emulator ..............
  • Page 18 23.6.4 SPOR circuit characteristics ....................727 23.6.5 Power supply voltage rising slope characteristics ............. 727 23.7 RAM Data Retention Characteristics .................... 728 23.8 Flash Memory Programming Characteristics ................729 23.9 Dedicated Flash Memory Programmer Communication (UART) ..........729 23.10 Timing of Entry to Flash Memory Programming Mode ..............730 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T = −40 to +105°C, T = −40 to...

  • Page 19: Chapter 1 Outline

    RL78/G15 R01UH0959EJ0110 Rev.1.10 RENESAS MCU Mar 7, 2023 CHAPTER 1 OUTLINE Features Low power consumption technology = single power supply voltage of 2.4 to 5.5 V  HALT mode  STOP mode  RL78 CPU core CISC architecture with 3-stage pipeline ...
  • Page 20 RL78/G15 CHAPTER 1 OUTLINE High-speed on-chip oscillator Select from 16 MHz, 8 MHz, 4 MHz, 2 MHz, and 1 MHz  Frequency accuracy ±1.0% (V = 2.4 to 5.5 V, T = −20 to +85°C)  (G: Industrial applications, M: Industrial applications) ...
  • Page 21 RL78/G15 CHAPTER 1 OUTLINE Comparator 1 to 2 channels   Operation mode: High-speed mode, low-speed mode  External reference voltage or internal reference voltage can be selected as the reference voltage. I/O port I/O port: 6 to 18 (N-ch open drain output [withstand voltage of V ]: 2 to 9) ...

  • Page 22: List Of Part Numbers

    RL78/G15 CHAPTER 1 OUTLINE List of Part Numbers Figure 1-1. Part Number, Memory Size, and Package of RL78/G15 Part No.　R 5 F 1 2 0 6 8 M S P #V0 Packaging specifications #00: Tray (Full carton) (HWQFN) #10: Tray (Full carton) (LSSOP, SSOP, WDFN)
  • Page 23 (4.4 × 6.5 mm, 0.65-mm pitch) R5F12068GSP, R5F12067GSP R5F12068MSP, R5F12067MSP For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G15. Note 1. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website.

  • Page 24: Pin Configuration (Top View)

    RL78/G15 CHAPTER 1 OUTLINE Pin Configuration (Top View) 1.3.1 8-pin products 8-pin plastic WDFN (3 × 3 mm, 0.65-mm pitch)  P40/TOOL0/PCLBUZ0/VCOUT0/INTP2/(TI01/TO01) P137/INTP0/TI00 RL78/G15 P125/RESET/INTP1/(VCOUT0) P04/ANI3/IVREF0/INTP3/TI01/TO01/SCK00/SCL00 (Top View) P03/TOOLTxD/ANI2/IVCMP0/INTP4/TO00/SO00/TxD0/SCLA0/(TI00) P01/TOOLRxD/ANI0/INTP5/TI02/TO02/SI00/RxD0/SDA00/SDAA0 Table 1-2. Multiplexed Functions of 8-pin Products Analog Timer Communications Interface TOOL0 —...

  • Page 25: 10-Pin Products

    RL78/G15 CHAPTER 1 OUTLINE 1.3.2 10-pin products 10-pin plastic LSSOP (4.4 × 3.6 mm, 0.65-mm pitch)  P40/TOOL0/INTP2/(TI01/TO01)/(PCLBUZ0) P04/ANI3/IVREF0/INTP3/TI01/TO01 P125/RESET/INTP1/(VCOUT0) P03/ANI2/INTP4/IVCMP0/TO00/SCLA0/(TI00) RL78/G15 P137/INTP0/TI00 P02/PCLBUZ0/ANI1/INTP7/VCOUT0/SCK00/SCL00/(TI01/TO01) (Top View) P01/TOOLRxD/ANI0/INTP5/TI02/TO02/SI00/RxD0/SDA00/SDAA0 P00/TOOLTxD/INTP6/SO00/TxD0 Table 1-3. Multiplexed Functions of 10-pin Products Analog Timer Communications Interface TOOL0 —...

  • Page 26: 16-Pin Products

    RL78/G15 CHAPTER 1 OUTLINE 1.3.3 16-pin products 16-pin plastic SSOP (4.4 × 5.0 mm, 0.65-mm pitch)  P41/TI03/TO03/(INTP4)/(TI02/TO02) P07/ANI6/SCK01/SCL01/SDAA0/(INTP5)/(TO03) P40/TOOL0/INTP2/(PCLBUZ0)/(TI01/TO01) P06/ANI5/SI01/SDA01/SCLA0/(PCLBUZ0)/(INTP7)/(SCK00/SCL00) P125/RESET/INTP1/(VCOUT0) P05/ANI4/TI02/TO02/SO01/(INTP6)/(SCK00/SCL00)/(SI00/RxD0/SDA00) RL78/G15 P137/INTP0/TI00 P04/ANI3/IVREF0/INTP3/TI01/TO01/(SI00/RxD0/SDA00)/(SO00/TxD0) (Top View) P122/X2/EXCLK/TI05/TO05/(INTP2) P03/ANI2/IVCMP0/INTP4/TO00/(TI00)/(SO00/TxD0) P121/X1/TI07/TO07/(INTP3) P02/PCLBUZ0/ANI1/VCOUT0/INTP7/SCK00/SCL00/(TI01/TO01)/(SO01) P01/TOOLRxD/ANI0/INTP5/SI00/RxD0/SDA00/(TI02/TO02)/(SI01)/(SDA01)/(SDAA0) P00/TOOLTxD/INTP6/SO00/TxD0/(SCK01/SCL01)/(SCLA0) R01UH0959EJ0110 Rev.1.10 Page 26 of 765...
  • Page 27 RL78/G15 CHAPTER 1 OUTLINE 16-pin plastic HWQFN (3 × 3 mm, 0.5-mm pitch)  P125/RESET/INTP1/(VCOUT0) P05/ANI4/TI02/TO02/SO01/(INTP6)/(SCK00/SCL00)/(SI00/RxD0/SDA00) RL78/G15 P137/INTP0/TI00 P04/ANI3/IVREF0/INTP3/TI01/TO01/(SI00/RxD0/SDA00)/(SO00/TxD0) (Top View) P122/X2/EXCLK/TI05/TO05/(INTP2) P03/ANI2/IVCMP0/INTP4/TO00/(TI00)/(SO00/TxD0) P121/X1/TI07/TO07/(INTP3) P02/PCLBUZ0/ANI1/VCOUT0/INTP7/SCK00/SCL00/(TI01/TO01)/(SO01) R01UH0959EJ0110 Rev.1.10 Page 27 of 765 Mar 7, 2023...
  • Page 28 RL78/G15 CHAPTER 1 OUTLINE Table 1-4. Multiplexed Functions of 16-pin Products Pin No. Analog Timer Communications Interface — — — (INTP4) TI03/TO03 — — (TI02/TO02) TOOL0 — — INTP2 (TI01/TO01) — — (PCLBUZ0) ¯¯¯¯¯¯ P125 RESET — (VCOUT0) INTP1 —...

  • Page 29: 20-Pin Products

    RL78/G15 CHAPTER 1 OUTLINE 1.3.4 20-pin products 20-pin plastic LSSOP (4.4 × 6.5 mm, 0.65-mm pitch)  P21/ANI9/IVCMP1/(INTP7)/(TO00) P22/ANI8/TI06/TO06/(INTP5)/(SDA01) P20/ANI10/IVREF1/(INTP1)/(TI00)/(TI03/TO03)/(SCK01/SCL01) P23/ANI7/TI04/TO04/(INTP6)/(SCL01) P41/VCOUT1/TI03/TO03/(INTP4)/(TI02/TO02)/(SO01)/(SDA01) P07/ANI6/SCK01/SCL01/SDAA0/(INTP5)/(TO03) P40/TOOL0/INTP2/(PCLBUZ0)/(TI01/TO01) P06/ANI5/SI01/SDA01/SCLA0/(PCLBUZ0)/(INTP7)/(SCK00/SCL00) RL78/G15 P125/RESET/INTP1/(VCOUT0)/(VCOUT1)/(SI01) P05/ANI4/TI02/TO02/SO01/(INTP6)/(SCK00/SCL00)/(SI00/RxD0/SDA00) (Top View) P137/INTP0/TI00 P04/ANI3/IVREF0/INTP3/TI01/TO01/(SI00/RxD0/SDA00)/(SO00/TxD0) P122/X2/EXCLK/TI05/TO05/(INTP2) P03/ANI2/IVCMP0/INTP4/TO00/(TI00)/(SO00/TxD0) P121/X1/TI07/TO07/(INTP3) P02/PCLBUZ0/ANI1/VCOUT0/INTP7/SCK00/SCL00/(TI01/TO01)/(SO01) P01/TOOLRxD/ANI0/INTP5/SI00/RxD0/SDA00/(TI02/TO02)/(SI01)/(SDA01)/(SDAA0) P00/TOOLTxD/INTP6/SO00/TxD0/(SCK01/SCL01)/(SCLA0) Table 1-5. Multiplexed Functions of 20-pin Products (1/2)
  • Page 30 RL78/G15 CHAPTER 1 OUTLINE Table 1-5. Multiplexed Functions of 20-pin Products (2/2) Analog Timer Communications Interface — ANI7 — (INTP6) TI04/TO04 (SCL01) — — ANI8 — (INTP5) TI06/TO06 (SDA01) — Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2.

  • Page 31: Pin Identification

    RL78/G15 CHAPTER 1 OUTLINE Pin Identification ANI0 to ANI10 : Analog Input INTP0 to INTP7 : Interrupt Request From Peripherals P00 to P07 : Port 0 P20 to P23 : Port 2 P40, P41 : Port 4 P121, P122, P125...

  • Page 32: Block Diagram

    RL78/G15 CHAPTER 1 OUTLINE Block Diagram 1.5.1 8-pin products TAU0 (8ch) TI00/TO00 ch00 P01, P03, P04 PORT 0 TI01/TO01 ch01 PORT 4 TI02/TO02 ch02 P125 PORT 12 CODE DATA FLASH FLASH ch03 4, 8 KB 1 KB P137 PORT 13...

  • Page 33: 10-Pin Products

    RL78/G15 CHAPTER 1 OUTLINE 1.5.2 10-pin products TAU0 (8ch) TI00/TO00 ch00 P00 to P04 PORT 0 TI01/TO01 ch01 PORT 4 TI02/TO02 ch02 PORT 12 P125 CODE DATA FLASH FLASH ch03 4, 8 KB 1 KB PORT 13 P137 ch04 BUZZER/CLOCK...

  • Page 34: 16-Pin Products

    RL78/G15 CHAPTER 1 OUTLINE 1.5.3 16-pin products TAU0 (8ch) TI00/TO00 ch00 P00 to P07 PORT 0 TI01/TO01 ch01 PORT 4 P40, P41 TI02/TO02 ch02 PORT 12 P121, P122, P125 CODE DATA FLASH FLASH TI03/TO03 ch03 4, 8 KB 1 KB...

  • Page 35: 20-Pin Products

    RL78/G15 CHAPTER 1 OUTLINE 1.5.4 20-pin products TAU0 (8ch) PORT 0 P00 to P07 TI00/TO00 ch00 P20 to P23 PORT 2 TI01/TO01 ch01 PORT 4 P40, P41 TI02/TO02 ch02 P121, P122, P125 PORT 12 CODE DATA TI03/TO03 ch03 FLASH FLASH...

  • Page 36: Outline Of Functions

    RL78/G15 CHAPTER 1 OUTLINE Outline of Functions This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 8-pin 10-pin 16-pin 20-pin R5F12007 R5F12008 R5F12017 R5F12018 R5F12047 R5F12048 R5F12067 R5F12068 Code flash memory...
  • Page 37 RL78/G15 CHAPTER 1 OUTLINE (2/2) Item 8-pin 10-pin 16-pin 20-pin R5F12007 R5F12008 R5F12017 R5F12018 R5F12047 R5F12048 R5F12067 R5F12068 On-chip debug function Provided Power supply voltage = 2.4 to 5.5 V Operating ambient temperature = −40 to +85°C (A: Consumer applications), T = −40 to +105°C (G: Industrial applications), T...

  • Page 38: Chapter 2 Pin Functions

    RL78/G15 CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS Port Function The input or output, buffer, and pull-up resistor settings on each port are also valid for the alternate functions.  2.1.1 8-pin products Function Pin Type After Reset Alternate Function...

  • Page 39: 10-Pin Products

    RL78/G15 CHAPTER 2 PIN FUNCTIONS  2.1.2 10-pin products Function Pin Type After Reset Alternate Function Function Name Release 7-1-2 Input port TOOLTxD/INTP6/SO00/TxD0 Port 0. 5-bit I/O port. TOOLRxD/ANI0/INTP5/TI02/ 7-3-2 Analog input Input/output can be specified in 1-bit units. TO02/SI00/RxD0/SDA00/...

  • Page 40: 16-Pin Products

    RL78/G15 CHAPTER 2 PIN FUNCTIONS  2.1.3 16-pin products Function Pin Type After Reset Alternate Function Function Name Release TOOLTxD/INTP6/SO00/ 7-1-2 Input port Port 0. TxD0/(SCK01/SCL01)/ 8-bit I/O port. (SCLA0) Input/output can be specified in 1-bit units. 7-3-2 Analog input...

  • Page 41: 20-Pin Products

    RL78/G15 CHAPTER 2 PIN FUNCTIONS  2.1.4 20-pin products (1/2) Function Pin Type After Reset Alternate Function Function Name Release 7-1-2 Input port TOOLTxD/INTP6/SO00/ Port 0. TxD0/(SCK01/SCL01)/ 8-bit I/O port. (SCLA0) Input/output can be specified in 1-bit units. 7-3-2 Analog input...
  • Page 42 RL78/G15 CHAPTER 2 PIN FUNCTIONS (2/2) Function After Reset Pin Type Alternate Function Function Name Release P121 7-2-2 Input port X1/TI07/TO07/(INTP3) Port 12. 3-bit I/O port. P122 X2/EXCLK/TI05/TO05/ Use of an on-chip pull-up resistor can be (INTP2) specified by a software setting at P121, P122, ¯¯¯¯¯¯...

  • Page 43: Functions Other Than Port Pins

    RL78/G15 CHAPTER 2 PIN FUNCTIONS Functions other than port pins 2.2.1 Functions for each product Function 20-pin 16-pin 10-pin 8-pin Function 20-pin 16-pin 10-pin 8-pin Name products products products products Name products products products products     ...

  • Page 44: Pins For Each Product (Pins Other Than Port Pins)

    RL78/G15 CHAPTER 2 PIN FUNCTIONS 2.2.2 Pins for each product (pins other than port pins) Function Name Function ANI0 to ANI10 Input A/D converter analog input (see Figure 10-23 Internal Equivalent Circuit of ANIn Pin). VCOUT0, VCOUT1 Output Comparator output...

  • Page 45: Connection Of Unused Pins

    RL78/G15 CHAPTER 2 PIN FUNCTIONS Connection of Unused Pins Table 2-2 shows the connections of unused pins. Remark The pins mounted depend on the product. Refer to 1.3 Pin Configuration (Top View) and 2.1 Port Function. Table 2-2. Connections of Unused Pins...

  • Page 46: Block Diagrams Of Pins

    RL78/G15 CHAPTER 2 PIN FUNCTIONS Block Diagrams of Pins Figure 2-1 to Figure 2-9 show the block diagrams of the pins described in 2.1.1 8-pin products to 2.1.4 20-pin products. Figure 2-1. Pin Block Diagram for Pin Type 2-1-2 Alternate function...
  • Page 47 RL78/G15 CHAPTER 2 PIN FUNCTIONS Figure 2-2. Pin Block Diagram for Pin Type 3-2-1 PU register (PUmn) P-ch Alternate function PORT PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU) ______ RESET PORTSELB Remark 1.
  • Page 48 RL78/G15 CHAPTER 2 PIN FUNCTIONS Figure 2-3. Pin Block Diagram for Pin Type 7-1-1 PU register (PUmn) P-ch Alternate function PORT PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU) Remark 1.
  • Page 49 RL78/G15 CHAPTER 2 PIN FUNCTIONS Figure 2-4. Pin Block Diagram for Pin Type 7-1-2 PU register (PUmn) P-ch Alternate function PORT PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) POM register (POMmn) Alternate function (SAU) Alternate function (other than SAU)
  • Page 50 RL78/G15 CHAPTER 2 PIN FUNCTIONS Figure 2-5. Pin Block Diagram for Pin Type 7-2-2 Clock generator OSCSEL Alternate function PORT <1> <3> P122/X2/EXCLK/Alternate function <5> EXCLK, OSCSEL <7> N-ch P-ch Alternate function PORT <2> <4> P121/X1/Alternate function <6> PU register...
  • Page 51 RL78/G15 CHAPTER 2 PIN FUNCTIONS Figure 2-6. Pin Block Diagram for Pin Type 7-3-1 PU register (PUmn) P-ch PMC register (PMCmn) Alternate function PORT PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU)
  • Page 52 RL78/G15 CHAPTER 2 PIN FUNCTIONS Figure 2-7. Pin Block Diagram for Pin Type 7-3-2 PU register (PUmn) P-ch PMC register (PMCmn) Alternate function PORT PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) POM register (POMmn) Alternate function (SAU) Alternate function...
  • Page 53 RL78/G15 CHAPTER 2 PIN FUNCTIONS Figure 2-8. Pin Block Diagram for Pin Type 7-9-1 PU register (PUmn) P-ch PMC register (PMCmn) Alternate function PORT PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU)
  • Page 54 RL78/G15 CHAPTER 2 PIN FUNCTIONS Figure 2-9. Pin Block Diagram for Pin Type 7-9-2 PU register (PUmn) P-ch PMC register (PMCmn) Alternate function PORT PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) POM register (POMmn) Alternate function (SAU) Alternate function...

  • Page 55: Chapter 3 Cpu Architecture

    The RL78/G15 has the RL78-S2 CPU core. Its main features are as follows. ...

  • Page 56: Memory Space

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE Memory Space Products in the RL78/G15 can access a 1-MB address space. Figure 3-1 and Figure 3-2 show the memory maps. Figure 3-1. Memory Map (R5F120x8 (x = 0, 1, 4, 6)) FFFFFH 01FFFH Special function register (SFR)
  • Page 57 RL78/G15 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (R5F120x7 (x = 0, 1, 4, 6)) FFFFFH 00FFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Note 1 1 KB FFB00H FFAFFH Reserved F9400H...
  • Page 58 RL78/G15 CHAPTER 3 CPU ARCHITECTURE Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory. 01FFFH Block 07H...

  • Page 59: Internal Program Memory Space

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.2.1 Internal program memory space The internal program memory space stores the program and table data. The RL78/G15 products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Internal ROM...
  • Page 60 RL78/G15 CHAPTER 3 CPU ARCHITECTURE The internal program memory space is divided into the following areas. (1) Vector table area The 128-byte area 00000H to 0007FH is reserved as a vector table area. The program start addresses for branch upon reset or generation of each interrupt request are stored in the vector table area.
  • Page 61 RL78/G15 CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT). Set the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is of 2 bytes).

  • Page 62: Mirror Area

    3.2.2 Mirror area The RL78/G15 mirrors the code flash area of 00800H to 01FFFH, to F0800H to F1FFFH. It also mirrors the data flash area of 09000H to 093FFH, to F9000H to F93FFH. By reading data from F0800H to F1FFFH and F9000H to F93FFH, an instruction that does not have the ES register as an operand can be used, and thus the contents of the code flash can be read with the shorter code.

  • Page 63: Internal Data Memory Space

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Internal data memory space The RL78/G15 products incorporate the following RAMs. Table 3-4. Internal RAM Capacity Part Number Internal RAM R5F120x8 (x = 0, 1, 4, 6) 1024 × 8 bits (FFB00H to FFEFFH)

  • Page 64: Data Memory Addressing

    Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the RL78/G15, based on operability and other considerations. In particular, special addressing methods designed for the functions of the special function registers (SFR) and general-purpose registers are available for use. Figure 3-3 shows correspondence between data memory and addressing.

  • Page 65: Processor Registers

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE Processor Registers The RL78/G15 products incorporate the following processor registers. 3.3.1 Control registers The control registers control the program sequence, status, and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
  • Page 66 RL78/G15 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled.
  • Page 67 RL78/G15 CHAPTER 3 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can be set as the stack area. Figure 3-6. Format of Stack Pointer...

  • Page 68: General-Purpose Registers

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.3.2 General-purpose registers General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The general- purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).

  • Page 69: And Cs Registers

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.3.3 ES and CS registers The ES register and CS register are used to specify the higher address for data access and when a branch instruction is executed (register indirect addressing), respectively. The default value of the ES register after reset is 0FH, and that of the CS register is 00H.

  • Page 70: Special Function Registers (Sfrs)

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.3.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type.
  • Page 71 RL78/G15 CHAPTER 3 CPU ARCHITECTURE Remark For extended SFRs (2nd SFRs), see 3.3.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers). Table 3-5. SFR List (1/2) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset...
  • Page 72 RL78/G15 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (2/2) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit  FFF6EH Timer data register 07 TDR07 — — 0000H FFF6FH  FFF90H Interval timer control register ITMC —...

  • Page 73: Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.3.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area.
  • Page 74 RL78/G15 CHAPTER 3 CPU ARCHITECTURE Caution Do not access addresses to which extended SFRs (2nd SFRs) are not assigned. Remark For SFRs in the SFR area, see 3.2.4 Special function register (SFR) area. Table 3-6. Extended SFR (2nd SFR) List (1/4)
  • Page 75 RL78/G15 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (2/4) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit   F0100H Serial status register 00 SSR00L SSR00 — 0000H F0101H —...
  • Page 76 RL78/G15 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (3/4) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit  F018EH Timer counter register 07 TCR07 — — FFFFH F018FH ...
  • Page 77 RL78/G15 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (4/4) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    F01BAH Timer output enable register 0 TOE0L TOE0 0000H F01BBH —...

  • Page 78: Instruction Address Addressing

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE Instruction Address Addressing 3.4.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: −128 to +127 or −32768 to +32767) to the program counter (PC)’s value (the start address of the next instruction), and specifies the program address to be used as the branch destination.

  • Page 79: Immediate Addressing

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.4.2 Immediate addressing [Function] Immediate addressing stores immediate data of the instruction word in the program counter, and specifies the program address to be used as the branch destination. For immediate addressing, CALL !!addr20 or BR !!addr20 is used to specify 20-bit addresses and CALL !addr16 or BR !addr16 is used to specify 16-bit addresses.

  • Page 80: Register Indirect Addressing

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address in the program counter (PC) as 16-bit data, and specifies the program address.

  • Page 81: Addressing For Processing Data Addresses

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE Addressing for Processing Data Addresses 3.5.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word.

  • Page 82: Register Addressing

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.5.2 Register addressing [Function] Register addressing accesses a general-purpose register as an operand. The instruction word of 3-bit long is used to select an 8-bit register and the instruction word of 2-bit long is used to select a 16-bit register.

  • Page 83: Direct Addressing

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.5.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier Description !addr16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable)

  • Page 84: Short Direct Addressing

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.5.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH. [Operand format]...

  • Page 85: Sfr Addressing

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.5.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format]...

  • Page 86: Register Indirect Addressing

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.5.6 Register indirect addressing [Function] Register indirect addressing specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier Description — [DE], [HL] (only the space from F0000H to FFFFFH is specifiable) —...

  • Page 87: Based Addressing

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.5.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as the base address and specifies the target addresses using the result of adding the 8-bit immediate data or 16-bit immediate data as the offset data to the base address.
  • Page 88 RL78/G15 CHAPTER 3 CPU ARCHITECTURE Figure 3-24. Example of [HL + byte], [DE + byte] [HL + byte], [DE + byte] <1> <2> <1> <2> FFFFFH Instruction code OP-code Target memory Target array of data <2> Offset <2> byte <1>...
  • Page 89 RL78/G15 CHAPTER 3 CPU ARCHITECTURE Figure 3-27. Example of ES:[HL + byte], ES:[DE + byte] [HL + byte], [DE + byte] <1> <2> <3> <1> <2> <3> XFFFFH Instruction code <2> OP-code Target memory Target array of data <3> Offset <3>...
  • Page 90 RL78/G15 CHAPTER 3 CPU ARCHITECTURE Figure 3-29. Example of ES:word[BC] ES: word [BC] <1> <2> <3> XFFFFH Array of Instruction code <3> Target memory word-sized data <3> OP-code Offset rp (BC) <2> Low Addr. Address of a word within an array <2>...

  • Page 91: Based Indexed Addressing

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.5.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address and specifies the target addresses using the result of adding the contents of the B register or C register similarly specified with the instruction word as the offset address to the base address.

  • Page 92: Stack Addressing

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE 3.5.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) values. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request.
  • Page 93 RL78/G15 CHAPTER 3 CPU ARCHITECTURE Figure 3-33. Example of POP <1> <2> SP + 2 <1> Instruction code Stack SP + 1 (SP + 1) <3> area (SP) <2> OP-code F0000H • Stack addressing is specified <1>. • The contents of addresses SP and SP + 1 are stored in the lower-order and higher-order bytes of the pair of registers indicated by rp <2>, respectively.
  • Page 94 RL78/G15 CHAPTER 3 CPU ARCHITECTURE Figure 3-36. Example of Interrupt, BRK <2> <1> Instruction code SP – 1 Stack PC19 to PC16 SP – 2 OP-code SP – 3 area PC15 to PC8 SP – 4 <3> PC7 to PC0 Interrupt <2>...

  • Page 95: Illegal Memory Access Detection Function

    RL78/G15 CHAPTER 3 CPU ARCHITECTURE Illegal Memory Access Detection Function The IEC60730 checks for the correct operation of the CPU and interrupts. The illegal memory access detection function generates a reset when the specified illegal access detection space is accessed.
  • Page 96 RL78/G15 CHAPTER 3 CPU ARCHITECTURE R01UH0959EJ0110 Rev.1.10 Page 96 of 765 Mar 7, 2023...

  • Page 97: Chapter 4 Port Functions

    RL78/G15 CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS Port Functions The RL78 microcontrollers are provided with digital I/O ports, which enable variety of control operations. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS.

  • Page 98: Port 0

    RL78/G15 CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port Note 1 mode register 0 (PM0). When the P00 to P07 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).

  • Page 99: Port 12

    RL78/G15 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 12 Port 12 is an I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port Note 1 Note 1 mode register 12 (PM12). When the P121...

  • Page 100: Port13

    RL78/G15 CHAPTER 4 PORT FUNCTIONS Registers Controlling Port Function Port functions are controlled by the following registers. ● Port mode registers 0, 2, 4, 12 (PM0, PM2, PM4, PM12) ● Port registers 0, 2, 4, 12, 13 (P0, P2, P4, P12, P13) ●...
  • Page 101 RL78/G15 CHAPTER 4 PORT FUNCTIONS Table 4-4. Pm, PMn, PUp, POMq, PMCr Registers and the Bits (16-pin Products) Port Bit name Pm register PMn register PUp register POMq register PMCr register PORT0 PM00 PU00 POM00 — PM01 PU01 POM01 PMC01...
  • Page 102 RL78/G15 CHAPTER 4 PORT FUNCTIONS Table 4-5. Pm, PMn, PUp, POMq, PMCr Registers and the Bits (20-pin Products) Port Bit name Pm register PMn register PUp register POMq register PMCr register PORT0 PM00 PU00 POM00 — PM01 PU01 POM01 PMC01...

  • Page 103: Port Mode Registers 0, 2, 4, 12 (Pm0, Pm2, Pm4, Pm12)

    RL78/G15 CHAPTER 4 PORT FUNCTIONS 4.3.1 Port mode registers 0, 2, 4, 12 (PM0, PM2, PM4, PM12) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 104 RL78/G15 CHAPTER 4 PORT FUNCTIONS PMmn Pmn pin I/O mode selection Output mode (output buffer on) Input mode (output buffer off) Remark m = 0, 2, 4, 12 n = 0 to 7 Caution Be sure to set bits that are not mounted to their initial values.

  • Page 105: Port Registers 0, 2, 4, 12, 13 (P0, P2, P4, P12, P13)

    RL78/G15 CHAPTER 4 PORT FUNCTIONS 4.3.2 Port registers 0, 2, 4, 12, 13 (P0, P2, P4, P12, P13) These registers set the output latch value of a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is...
  • Page 106 RL78/G15 CHAPTER 4 PORT FUNCTIONS 20-pin products Symbol Address After reset FFF00H 00H (output latch) FFF02H 00H (output latch) FFF04H 00H (output latch) P125 P122 P121 FFF0CH 00H (output latch) P137 FFF0DH Undefined Output data control (in output mode) Input data read (in input mode)

  • Page 107: Pull-Up Resistor Option Registers 0, 2, 4, 12 (Pu0, Pu2, Pu4, Pu12)

    RL78/G15 CHAPTER 4 PORT FUNCTIONS 4.3.3 Pull-up resistor option registers 0, 2, 4, 12 (PU0, PU2, PU4, PU12) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits that satisfy the following usage conditions for the pins to which the use of an on-chip pull-up resistor has been specified in these registers.
  • Page 108 RL78/G15 CHAPTER 4 PORT FUNCTIONS 20-pin products Symbol Address After reset PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00 F0030H PU23 PU22 PU21 PU20 F0032H PU41 PU40 F0034H PU125 PU12 PU122 PU121 F003CH Note 1 PUmn Pmn pin on-chip pull-up resistor selection...

  • Page 109: Port Input Mode Registers 0, 2, 4 (Pom0, Pom2, Pom4)

    RL78/G15 CHAPTER 4 PORT FUNCTIONS 4.3.4 Port input mode registers 0, 2, 4 (POM0, POM2, POM4) These registers set CMOS output or N-ch open drain output in 1-bit units. N-ch open drain output (V tolerance) mode can be selected for the SDA00 and SDA01 pins during simplified I communication with an external device.

  • Page 110: Port Mode Control Registers 0, 2 (Pmc0, Pmc2)

    RL78/G15 CHAPTER 4 PORT FUNCTIONS 4.3.5 Port mode control registers 0, 2 (PMC0, PMC2) These registers set the digital I/O/analog input in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to FFH.

  • Page 111: Peripheral I/O Redirection Registers 0 To 3 (Pior0 To Pior3)

    RL78/G15 CHAPTER 4 PORT FUNCTIONS 4.3.6 Peripheral I/O redirection registers 0 to 3 (PIOR0 to PIOR3) These registers are used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned.
  • Page 112 RL78/G15 CHAPTER 4 PORT FUNCTIONS 8-pin products Function Setting value PIOR02 TI01/TO01 PIOR00 TI00 P137 PIOR32 VCOUT0 P125 10-pin products Function Setting value PIOR00 TI00 P137 PIOR32 VCOUT0 P125 PIOR30 PCLBUZ0 Function Setting value PIOR03 PIOR02 TI01/TO01 Setting prohibited R01UH0959EJ0110 Rev.1.10...
  • Page 113 RL78/G15 CHAPTER 4 PORT FUNCTIONS 16-pin products Function Setting value PIOR06 TO03 PIOR00 TI00 P137 PIOR14 SCLA0 SDAA0 PIOR12 SCK01/SCL01 SI01/SDA01 SO01 PIOR26 INTP6 PIOR24 INTP5 PIOR23 INTP4 PIOR22 INTP3 P121 PIOR21 INTP2 P122 PIOR34 INTP7 PIOR32 VCOUT0 P125 Function...
  • Page 114 RL78/G15 CHAPTER 4 PORT FUNCTIONS 20-pin products Function Setting value PIOR14 SCLA0 SDAA0 PIOR23 INTP4 PIOR22 INTP3 P121 PIOR21 INTP2 P122 PIOR20 INTP1 P125 PIOR33 VCOUT1 P125 PIOR32 VCOUT0 P125 Function Setting value PIOR07 PIOR06 TI03 Setting prohibited TO03 PIOR05...

  • Page 115: Port Function Operations

    RL78/G15 CHAPTER 4 PORT FUNCTIONS Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port 1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.

  • Page 116: Register Settings When Using Alternate Function

    RL78/G15 CHAPTER 4 PORT FUNCTIONS Register Settings When Using Alternate Function 4.5.1 Basic concept when using alternate function In the beginning, for a pin also assigned to be used for analog input, use the port mode control registers 0, 2 (PMC0, PMC2) to specify whether to use the pin for analog input or digital input/output.

  • Page 117: Register Settings For Alternate Function Whose Output Function Is Not Used

    RL78/G15 CHAPTER 4 PORT FUNCTIONS Table 4-6. Concept of Basic Settings Output Function of Used Pin Output Settings of Unused Alternate Function Output Function for Port Output Function for SAU Output Function for other than SAU Output function for port —...

  • Page 118: Register Setting Examples For Used Port And Alternate Functions

    RL78/G15 CHAPTER 4 PORT FUNCTIONS (5) PCLBUZ0 = 0 (setting when clock/buzzer output is not used) When the clock/buzzer output is not used, set the PCLOE0 bit in clock output select register 0 (CKS0) to 0 (output disabled). This is the same setting as the initial state.
  • Page 119 RL78/G15 CHAPTER 4 PORT FUNCTIONS  Table 4-7. Setting Examples of Registers and Output Latches When Using Pin Function (2/10) Used Function PIORr POMp PMCq PMn Pm Alternate Function Output Name Function SAU Output Function Other than SAU Name ...
  • Page 120 RL78/G15 CHAPTER 4 PORT FUNCTIONS  Table 4-7. Setting Examples of Registers and Output Latches When Using Pin Function (3/10) Used Function PIORr POMp PMCq PMn Pm Alternate Function Output Name Function SAU Output Function Other than SAU Name ...
  • Page 121 RL78/G15 CHAPTER 4 PORT FUNCTIONS  Table 4-7. Setting Examples of Registers and Output Latches When Using Pin Function (4/10) Used Function PIORr POMp PMCq PMn Pm Alternate Function Output Name Function SAU Output Function Other than SAU Name ...
  • Page 122 RL78/G15 CHAPTER 4 PORT FUNCTIONS  Table 4-7. Setting Examples of Registers and Output Latches When Using Pin Function (5/10) Used Function PIORr POMp PMCq PMn Pm Alternate Function Output Name Function SAU Output Function Other than SAU Name ...
  • Page 123 RL78/G15 CHAPTER 4 PORT FUNCTIONS  Table 4-7. Setting Examples of Registers and Output Latches When Using Pin Function (6/10) Used Function PIORr POMp PMCq PMn Pm Alternate Function Output Name Function SAU Output Function Other than SAU Name ...
  • Page 124 RL78/G15 CHAPTER 4 PORT FUNCTIONS  Table 4-7. Setting Examples of Registers and Output Latches When Using Pin Function (7/10) Used Function PIORr POMp PMCq PMn Pm Alternate Function Output Name Function SAU Output Function Other than SAU Name ...
  • Page 125 RL78/G15 CHAPTER 4 PORT FUNCTIONS  Table 4-7. Setting Examples of Registers and Output Latches When Using Pin Function (8/10) Used Function PIORr POMp PMCq PMn Pm Alternate Function Output Name Function SAU Output Function Other than SAU Name ...
  • Page 126 RL78/G15 CHAPTER 4 PORT FUNCTIONS Table 4-7. Setting Examples of Registers and Output Latches When Using Pin Function (9/10) Used Function PIORr POMp PMCq PMn Pm Alternate Name (EXCLK,OSCSEL) Function Output Function Name   P121 P121 Input — —...

  • Page 127: Cautions When Using Port Function

    RL78/G15 CHAPTER 4 PORT FUNCTIONS Cautions When Using Port Function 4.6.1 Cautions on 1-bit manipulation instruction for port register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.

  • Page 128: Notes On Specifying The Pin Settings

    RL78/G15 CHAPTER 4 PORT FUNCTIONS 4.6.2 Notes on specifying the pin settings For an output pin to which multiple alternate functions are assigned, the output of the unused alternate functions must be set to its initial state so as to prevent conflicting outputs. This also applies to the functions assigned by using the peripheral I/O redirection register 0 to 3 (PIOR0 to PIOR3).

  • Page 129: Chapter 5 Clock Generator

    RL78/G15 CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable.
  • Page 130 RL78/G15 CHAPTER 5 CLOCK GENERATOR 2) Low-speed on-chip oscillator clock This circuit oscillates a clock of f = 15 kHz (typ.). The low-speed on-chip oscillator clock cannot be used as the CPU clock. Only the following peripheral hardware runs on the low-speed on-chip oscillator clock.

  • Page 131: Configuration Of Clock Generator

    RL78/G15 CHAPTER 5 CLOCK GENERATOR Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration 8-pin 10-pin 16-pin 20-pin products products products products   Control registers Clock operation mode control register (CMC) —...
  • Page 132 RL78/G15 CHAPTER 5 CLOCK GENERATOR R01UH0959EJ0110 Rev.1.10 Page 132 of 765 Mar 7, 2023...

  • Page 133: Registers Controlling Clock Generator

    RL78/G15 CHAPTER 5 CLOCK GENERATOR Remark : X1 clock oscillation frequency : High-speed on-chip oscillator clock frequency : External main system clock frequency : High-speed system clock frequency : Main system clock frequency MAIN : CPU/peripheral hardware clock frequency : Low-speed on-chip oscillator clock frequency Registers Controlling Clock Generator The clock generator is controlled by the following registers depending on the products.

  • Page 134: Clock Operation Mode Control Register (Cmc)

    RL78/G15 CHAPTER 5 CLOCK GENERATOR 5.3.1 Clock operation mode control register (CMC) This register is used to set the operation mode of the X1/P121/TI07/TO07/(INTP3) and X2/EXCLK/P122/TI05/TO05/(INTP2) pins, and to select a gain of the oscillator. The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release. This register can be read by an 8-bit memory manipulation instruction.

  • Page 135: System Clock Control Register (Ckc)

    RL78/G15 CHAPTER 5 CLOCK GENERATOR 5.3.2 System clock control register (CKC) This register is used to select a main system clock. The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.

  • Page 136: Clock Operation Status Control Register (Csc)

    RL78/G15 CHAPTER 5 CLOCK GENERATOR 5.3.3 Clock operation status control register (CSC) This register is used to control the operations of the high-speed system clock and high-speed on-chip oscillator clock (except the low-speed on-chip oscillator clock). The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 137 RL78/G15 CHAPTER 5 CLOCK GENERATOR Table 5-2. Conditions Before Clock Oscillation Is Stopped and Flag Settings Clock Conditions Before Clock Oscillation Is Stopped Flag Settings of CSC Register X1 clock CPU/peripheral hardware clock operates with the high-speed MSTOP = 1 on-chip oscillator clock (MCS = 0).

  • Page 138: Oscillation Stabilization Time Counter Status Register (Ostc)

    RL78/G15 CHAPTER 5 CLOCK GENERATOR 5.3.4 Oscillation stabilization time counter status register (OSTC) This register is used to indicate the count status of the X1 clock oscillation stabilization time counter. The X1 clock oscillation stabilization time can be checked in the following case.
  • Page 139 RL78/G15 CHAPTER 5 CLOCK GENERATOR Caution 2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the oscillation stabilization time select register (OSTS). In the following cases, set the oscillation stabilization time of the OSTS register to the value greater than the count value which is to be checked by the OSTC register.

  • Page 140: Oscillation Stabilization Time Select Register (Osts)

    RL78/G15 CHAPTER 5 CLOCK GENERATOR 5.3.5 Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization time at releasing of the STOP mode. When the X1 clock is selected as the CPU clock, the operation automatically waits for the time set using the OSTS register after the STOP mode is released.
  • Page 141 RL78/G15 CHAPTER 5 CLOCK GENERATOR Caution 5. The X1 clock oscillation stabilization time does not include the time until clock oscillation starts (“a” below). STOP mode release X1 pin voltage waveform Remark : X1 clock oscillation frequency R01UH0959EJ0110 Rev.1.10 Page 141 of 765...

  • Page 142: Peripheral Enable Register 0 (Per0)

    RL78/G15 CHAPTER 5 CLOCK GENERATOR 5.3.6 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise.
  • Page 143 RL78/G15 CHAPTER 5 CLOCK GENERATOR Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/2) Address: F00F0H After reset: 00H □ □ □ □ □ □ Symbol Note 1 Note 1 Note 1 PER0 TMKAEN CMPEN ADCEN IICA0EN SAU0EN TAU0EN...

  • Page 144: Operation Speed Mode Control Register (Osmc)

    RL78/G15 CHAPTER 5 CLOCK GENERATOR 5.3.7 Operation speed mode control register (OSMC) This register is used to control supply of the operation clock for the 12-bit interval timer. When operating the 12-bit interval timer, set WUTMMCK0 = 1 beforehand and do not set WUTMMCK0 = 0 until the timer is stopped.

  • Page 145: High-Speed On-Chip Oscillator Frequency Select Register (Hocodiv)

    RL78/G15 CHAPTER 5 CLOCK GENERATOR 5.3.8 High-speed on-chip oscillator frequency select register (HOCODIV) This register is used to change the frequency of the high-speed on-chip oscillator which is set by an option byte (000C2H). The HOCODIV register can be set by an 8-bit memory manipulation instruction.

  • Page 146: High-Speed On-Chip Oscillator Trimming Register (Hiotrm)

    RL78/G15 CHAPTER 5 CLOCK GENERATOR 5.3.9 High-speed on-chip oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the high-speed on-chip oscillator. With self-measurement of the high-speed on-chip oscillator frequency via a timer using high-accuracy external clock input (timer array unit), and so on, the accuracy can be adjusted.

  • Page 147: System Clock Oscillator

    RL78/G15 CHAPTER 5 CLOCK GENERATOR System Clock Oscillator 5.4.1 X1 oscillator (16-pin and 20-pin products only) The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 12 MHz) connected to the X1 pin and X2 pin. An external clock can also be input. In this case, input the clock signal to the EXCLK pin.
  • Page 148 RL78/G15 CHAPTER 5 CLOCK GENERATOR Figure 5-12 shows examples of incorrect resonator connection. Figure 5-12. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT (c) The X1 and X2 signal line wires cross. (d) A power supply/GND pattern exists under the X1 and X2 wires.
  • Page 149 RL78/G15 CHAPTER 5 CLOCK GENERATOR Figure 5-12. Examples of Incorrect Resonator Connection (2/2) (e) Wiring near high alternating current (f) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (g) Signals are fetched R01UH0959EJ0110 Rev.1.10...

  • Page 150: High-Speed On-Chip Oscillator

    RL78/G15 CHAPTER 5 CLOCK GENERATOR 5.4.2 High-speed on-chip oscillator The high-speed on-chip oscillator is incorporated. The frequency can be selected from among 16, 8, 4, 2, or 1 MHz by using the option byte (000C2H). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC).
  • Page 151 RL78/G15 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned On Power supply voltage (V SPOR reset release voltage ________________ <1> Internal reset signal Switched by SPOR reset software Note 3 processing <5> <3>...

  • Page 152: Controlling Clock

    RL78/G15 CHAPTER 5 CLOCK GENERATOR Controlling Clock 5.6.1 Example of setting high-speed on-chip oscillator After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. The frequency of the high-speed on-chip oscillator can be selected by using FRQSEL0 to FRQSEL2 of the option byte (000C2H).

  • Page 153: Example Of Setting X1 Oscillation Clock

    RL78/G15 CHAPTER 5 CLOCK GENERATOR 5.6.2 Example of setting X1 oscillation clock After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. To subsequently change the clock to the X1 clock, set the oscillator and start oscillation by using the...

  • Page 154: Cpu Clock Status Transition Diagram

    RL78/G15 CHAPTER 5 CLOCK GENERATOR 5.6.3 CPU clock status transition diagram Figure 5-14 shows the CPU clock status transition diagram of this product. Figure 5-14. CPU Clock Status Transition Diagram Power ON High-speed on-chip oscillator: Woken up Note 1 X1 oscillation/EXCLK input: Stops (input port mode) being greater than the detection voltage for the SPOR circuit and release from the reset state due to any reset source.
  • Page 155 RL78/G15 CHAPTER 5 CLOCK GENERATOR Table 5-3 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-3. CPU Clock Transition and SFR Register Setting Examples for 16-Pin and 20-Pin Products (1/2) CPU clock changing from high-speed on-chip oscillator clock (A) to high-speed system clock (B) (The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (A).)
  • Page 156 RL78/G15 CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples for 16-Pin and 20-Pin Products (2/2) CPU clock changing from high-speed system clock (B) to high-speed on-chip oscillator clock (A) (Setting sequence of SFR registers)

  • Page 157: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock

    RL78/G15 CHAPTER 5 CLOCK GENERATOR 5.6.4 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5-4. Changing CPU Clock CPU Clock...

  • Page 158: Time Required For Switchover Of Cpu Clock And Main System Clock

    RL78/G15 CHAPTER 5 CLOCK GENERATOR 5.6.5 Time required for switchover of CPU clock and main system clock The main system clock can be switched between the high-speed on-chip oscillator clock and the high-speed system clock by specifying bit 4 (MCM0) of the system clock control register (CKC).

  • Page 159: Resonator And Oscillator Constants

    Resonator and Oscillator Constants For the resonators for which the operation is verified and their oscillator constants, refer to the target product page of the Renesas Electronics website. Caution 1. The constants for these oscillator circuits are reference values based on specific environments set up for evaluation by the manufacturers.

  • Page 160: Chapter 6 Timer Array Unit

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT CHAPTER 6 TIMER ARRAY UNIT Units Channels 20, 16, 10, 8-pin  Unit 0 Channel 0  Channel 1  Channel 2  Channel 3  Channel 4  Channel 5  Channel 6 ...
  • Page 161 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT For details about each function, see the table below. Independent channel operation function Simultaneous channel operation function ● ● Interval timer (→ refer to 6.8.1 Operation as interval One-shot pulse output (→ refer to 6.9.1 Operation as one- timer/square wave output.)

  • Page 162: Functions Of Timer Array Unit

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Functions of Timer Array Unit Timer array unit has the following functions. 6.1.1 Independent channel operation function By operating a channel independently, it can be used for the following purposes without being affected by the operation mode of other channels.
  • Page 163 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 3) External event counter Each timer of a unit can be used as an event counter that generates an interrupt when the number of the valid edges of a signal input to the timer input pin (TImn) has reached a specific value.
  • Page 164 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6) Measurement of high-/low-level width of input signal Counting is started by a single edge of the signal input to the timer input pin (TImn), and the count value is captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured.

  • Page 165: Simultaneous Channel Operation Function

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.1.2 Simultaneous channel operation function By using the combination of a master channel (a reference timer mainly controlling the cycle) and slave channels (timers operating according to the master channel), channels can be used for the following purposes.
  • Page 166 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 3) Multiple PWM (Pulse Width Modulation) output By extending the PWM function and using one master channel and two or more slave channels, up to seven types of PWM signals that have a specific period and a specified duty factor can be generated.

  • Page 167: 8-Bit Timer Operation Function (Channels 1 And 3 Only)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.1.3 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8-bit timer channels. This function can only be used for channels 1 and 3.

  • Page 168: Configuration Of Timer Array Unit

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Configuration of Timer Array Unit Timer array unit includes the following hardware. Table 6-1. Configuration of Timer Array Unit Item Configuration Timer/counter Timer count register mn (TCRmn) Register Timer data register mn (TDRmn) Note 1...
  • Page 169 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT The presence or absence of timer I/O pins in each timer array unit channel depends on the product. Table 6-2. Timer I/O Pins provided in Each Product Timer array unit channels I/O Pins of Each Product...
  • Page 170 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-1 shows the block diagrams of the timer array unit. Figure 6-1. Entire Block Diagram of Timer Array Unit Timer clock select register 0 (TPS0) Prescaler Selector Selector Peripheral enable TAU0EN register 0 (PER0)
  • Page 171 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-2. Internal Block Diagram of Channels 0, 2, 4, 6 of Timer Array Unit Note 1 Input signal from the master channel CK00 Timer controller Output TCLK TO0n controller CK01 Output latch Mode...
  • Page 172 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-4. Internal Block Diagram of Channel 3 of Timer Array Unit Input signal from the master channel CK00 Timer controller CK01 Output TCLK TO0n controller CK02 CK03 Output latch Mode PMxx (Pxx) selection...

  • Page 173: Timer Count Register Mn (Tcrmn)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.2.1 Timer count register mn (TCRmn) The TCRmn register is a 16-bit read-only register and is used to count clocks. The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock.
  • Page 174 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT The TCRmn register read value differs as follows according to operation mode changes and the operating status. Table 6-3. Timer Count Register mn (TCRmn) Read Value in Various Operation Modes Note 1 Operation Mode...

  • Page 175: Timer Data Register Mn (Tdrmn)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.2.2 Timer data register mn (TDRmn) This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn).
  • Page 176 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT (ii) When timer data register mn (TDRmn) is used as capture register The count value of timer count register mn (TCRmn) is captured to the TDRmn register when the capture trigger is input. A valid edge of the TImn pin can be selected as the capture trigger. This selection is made by timer mode register mn (TMRmn).

  • Page 177: Registers Controlling Timer Array Unit

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers. ● Peripheral enable register 0 (PER0) ● Timer clock select register m (TPSm) ● Timer mode register mn (TMRmn) ●...

  • Page 178: Peripheral Enable Register 0 (Per0)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.

  • Page 179: Timer Clock Select Register M (Tpsm)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.3.2 Timer clock select register m (TPSm) The TPSm register is a 16-bit register that is used to select two types or four types of operation clocks (CKm0, CKm1, CKm2, CKm3) that are commonly supplied to each channel. CKm0 is selected by using bits 3 to 0 of the TPSm register, and CKm1 is selected by using bits 7 to 4 of the TPSm register.
  • Page 180 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-10. Format of Timer Clock Select register m (TPSm) (1/2) Address: F01B6H, F01B7H (TPS0) After reset: 0000H Symbol TPSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm Note 1...
  • Page 181 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-10. Format of Timer Clock Select register m (TPSm) (2/2) Address: F01B6H, F01B7H (TPS0) After reset: 0000H Symbol TPSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm Note 1...
  • Page 182 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT By using channels 1 and 3 in the 8-bit timer mode and specifying CKm2 or CKm3 as the operation clock, the interval times shown in Table 6-4 can be achieved by using the interval timer function.

  • Page 183: Timer Mode Register Mn (Tmrmn)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.3.3 Timer mode register mn (TMRmn) The TMRmn register sets an operation mode of channel n. This register is used to select the operation clock (f select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event counter, one-count, or capture and one-count).
  • Page 184 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register mn (TMRmn) (1/5) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMRmn CKSm CKSm CCSm MAST STSmn STSmn STSmn CISmn CISmn MDmn MDmn...
  • Page 185 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register mn (TMRmn) (2/5) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMRmn CKSm CKSm CCSm MAST STSmn STSmn STSmn CISmn CISmn MDmn MDmn...
  • Page 186 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Note 1. Bit 11 is a read-only bit and fixed to 0. Writing to this bit is ignored. Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7) Figure 6-11. Format of Timer Mode Register mn (TMRmn) (3/5)
  • Page 187 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register mn (TMRmn) (4/5) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMRmn CKSm CKSm CCSm MAST STSmn STSmn STSmn CISmn CISmn MDmn MDmn...
  • Page 188 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register mn (TMRmn) (5/5) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMRmn CKSm CKSm CCSm MAST STSmn STSmn STSmn CISmn CISmn MDmn MDmn...

  • Page 189: Timer Status Register Mn (Tsrmn)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.3.4 Timer status register mn (TSRmn) The TSRmn register indicates the overflow status of the counter of channel n. The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode (MDmn3 to MDmn1 = 110B).

  • Page 190: Timer Channel Enable Status Register M (Tem)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.3.5 Timer channel enable status register m (TEm) The TEm register is used to display whether the timer operation of each channel is enabled or stopped. Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and the timer channel stop register m (TTm).

  • Page 191: Timer Channel Start Register M (Tsm)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.3.6 Timer channel start register m (TSm) The TSm register is a trigger register that is used to initialize timer count register mn (TCRmn) and start the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is set to 1.
  • Page 192 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Caution 1. Be sure to clear bits 15 to 12, 10, and 8 to 0. Caution 2. When switching from a function that does not use TImn pin input to one that does, the following wait period is required from when timer mode register mn (TMRmn) is set until the TSmn (TSHm1, TSHm3) bit is set to 1.

  • Page 193: Timer Channel Stop Register M (Ttm)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.3.7 Timer channel stop register m (TTm) The TTm register is a trigger register that is used to stop the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is cleared to 0.

  • Page 194: Timer Output Enable Register M (Toem)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.3.8 Timer output enable register m (TOEm) The TOEm register is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOmn bit of timer output register m (TOm) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TOmn).

  • Page 195: Timer Output Register M (Tom)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.3.9 Timer output register m (TOm) The TOm register is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TOmn) of each channel.

  • Page 196: Timer Output Level Register M (Tolm)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.3.10 Timer output level register m (TOLm) The TOLm register is a register that controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOEmn = 1) in the simultaneous channel operation function (TOMmn = 1).

  • Page 197: Timer Output Mode Register M (Tomm)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.3.11 Timer output mode register m (TOMm) The TOMm register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0.

  • Page 198: Input Switch Control Register (Isc)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.3.12 Input switch control register (ISC) The ISC register is used to implement UART0 baud rate correction by using channel 1 in association with the serial array unit. When the ISC1 bit is set to 1, the input signal of the serial data input (RxD0) pin is selected as a timer input.

  • Page 199: Noise Filter Enable Registers 1 (Nfen1)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.3.13 Noise filter enable registers 1 (NFEN1) The NFEN1 register is used to set whether the noise filter can be used for the timer input signal to each channel. Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
  • Page 200 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-21. Format of Noise Filter Enable Registers 1 (NFEN1) (2/2) Address: F0071H After reset: 00H Symbol NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00 TNFEN02 Enable/disable using noise filter of TI02 pin...

  • Page 201: Registers Controlling Port Functions Of Pins To Be Used For Timer I/O

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.3.14 Registers controlling port functions of pins to be used for timer I/O Using port pins for the timer array unit functions requires setting of the registers that control the port functions multiplexed on the target pins (port mode register (PMxx), port register (Pxx), and port mode control register (PMCxx)). For details, see 4.3.1 Port mode registers 0, 2, 4, 12 (PM0, PM2, PM4, PM12), 4.3.2 Port registers 0, 2, 4, 12, 13 (P0, P2, P4,...

  • Page 202: Basic Rules Of Timer Array Unit

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Basic Rules of Timer Array Unit 6.4.1 Basic rules of simultaneous channel operation function When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply.
  • Page 203 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT The rules of the simultaneous channel operation function are applied in a channel group (a master channel and slave channels forming one simultaneous channel operation function). If two or more channel groups that do not operate in combination are specified, the basic rules of the simultaneous channel operation function in 6.4.1 Basic rules of simultaneous channel operation function do not apply to the channel...

  • Page 204: Basic Rules Of 8-Bit Timer Operation Function (Channels 1 And 3 Only)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8-bit timer channels.

  • Page 205: Operation Of Counter

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Operation of Counter 6.5.1 Count clock (f TCLK The count clock (f ) of the timer array unit can be selected between the following by CCSmn bit of timer mode register TCLK mn (TMRmn).
  • Page 206 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1) The count clock (f ) becomes the signal that detects valid edge of input signal via the TImn pin and synchronizes next...

  • Page 207: Start Timing Of Counter

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.5.2 Start timing of counter Timer count register mn (TCRmn) becomes enabled to operation by setting of TSmn bit of timer channel start register m (TSm). Operations from count operation enabled state to timer count register mn (TCRmn) count start is shown in Table 6-6.

  • Page 208: Operation Of Counter

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.5.3 Operation of counter Here, the counter operation in each mode is explained. (1) Operation of interval timer mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. Timer count register mn (TCRmn) holds the initial value until count clock generation.
  • Page 209 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT (2) Operation of event counter mode <1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0). <2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
  • Page 210 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT (3) Operation of capture mode (input pulse interval measurement) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until count clock generation.
  • Page 211 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Remark Figure 6-26 shows the timing when the noise filter is not used. By making the noise filter on-state, the edge detection becomes 2 f cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TImn input. The...
  • Page 212 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT (5) Operation of capture & one-count mode (high-level width measurement) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm). <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation.

  • Page 213: Channel Output (Tomn Pin) Control

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Channel Output (TOmn pin) Control 6.6.1 TOmn pin output circuit configuration Figure 6-29. Output Circuit Configuration <5> TOmn register Interrupt signal of the master channel (INTTMmn) TOmn pin Interrupt signal of the slave channel...
  • Page 214 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Remark m: Unit number (m = 0) n: Channel number n = 0 to 7 (n = 0, 2, 4, 6 for master channel) p: Slave channel number n < p ≤ 7 R01UH0959EJ0110 Rev.1.10...

  • Page 215: Tomn Pin Output Setting

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.6.2 TOmn pin output setting The following figure shows the procedure and status transition of the TOmn output pin from initial setting to timer operation start. Figure 6-30. Status Transition from Timer Output Setting to Operation Start...

  • Page 216: Cautions On Channel Output Operation

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.6.3 Cautions on channel output operation (1) Changing values set in the registers TOm, TOEm, and TOLm during timer operation Since the timer operations (operations of timer count register mn (TCRmn) and timer data register mn (TDRmn)) are...
  • Page 217 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT (2) Default level of TOmn pin and output level after timer operation start The change in the output level of the TOmn pin when timer output register m (TOm) is written while timer output is disabled (TOEmn = 0), the initial level is changed, and then timer output is enabled (TOEmn = 1) before port output is enabled, is shown below.
  • Page 218 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT (b) When operation starts with slave channel output mode (TOMmp = 1) setting (PWM output)) When slave channel output mode (TOMmp = 1), the active level is determined by timer output level register m (TOLm) setting.
  • Page 219 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT (3) Operation of TOmn pin in slave channel output mode (TOMmn = 1) (a) When timer output level register m (TOLm) setting has been changed during timer operation When the TOLm register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TOmn pin change condition.
  • Page 220 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-34. Set/Reset Timing Operating Status (1) Basic operation timing TCLK INTTMmn Master Internal reset signal channel TOmn pin/ TOmn Toggle Toggle Internal set signal 1 clock delay INTTMmp Slave channel Internal reset signal...
  • Page 221 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Remark 1. Internal reset signal: TOmn pin reset/toggle signal Internal set signal: TOmn pin set signal Remark 2. m: Unit number (m = 0) n: Channel number n = 0 to 7 (n = 0, 2, 4, 6 for master channel) p: Slave channel number n <...

  • Page 222: Collective Manipulation Of Tomn Bit

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.6.4 Collective manipulation of TOmn bit In timer output register m (TOm), the setting bits (TOmn) for all the channels are located in one register in the same way as timer channel start register m (TSm). Therefore, the TOmn bit of all the channels can be manipulated collectively.
  • Page 223 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-36. TO0n Pin Status by Collective Manipulation of TO0n Bit Two or more TO0n output can be changed simultaneously TO07 Output does not change TO06 when the value does not change TO05 TO04...

  • Page 224: Timer Interrupt And Tomn Pin Output At Count Operation Start

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.6.5 Timer interrupt and TOmn pin output at count operation start In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or not to generate a timer interrupt at count start.

  • Page 225: Timer Input (Timn) Control

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Timer Input (TImn) Control 6.7.1 TImn input circuit configuration A signal is input from a timer input pin, goes through a noise filter and an edge detector, and is sent to a timer controller.

  • Page 226: Cautions On Channel Input Operation

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.7.3 Cautions on channel input operation When a timer input pin is set as unused, the operation clock is not supplied to the noise filter. Therefore, after settings are made to use the timer input pin, the following wait time is necessary before a trigger is specified to enable operation of the channel corresponding to the timer input pin.

  • Page 227: Independent Channel Operation Function Of Timer Array Unit

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Independent Channel Operation Function of Timer Array Unit 6.8.1 Operation as interval timer/square wave output (1) Interval timer The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals.
  • Page 228 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-40. Block Diagram of Operation as Interval Timer/Square Wave Output CKm1 Operation clock Note 1 Timer counter register mn Output TOmn pin CKm0 (TCRmn) controller Interrupt signal Timer data register mn Interrupt TSmn...
  • Page 229 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-42. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/2) (a) Timer mode register mn (TMRmn) TMRmn CKSm CKSm CCSm STSmn STSmn STSmn CISmn CISmn MDmn MDmn MDmn...
  • Page 230 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-42. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/2) (b) Timer output register m (TOm) Bit n TOmn 0: Outputs 0 from TOmn. 1: Outputs 1 from TOmn.
  • Page 231 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Operation Procedure of Interval Timer/Square Wave Output Function (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register setting is disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
  • Page 232 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Operation Procedure of Interval Timer/Square Wave Output Function (2/2) Software Operation Hardware Status TAU stop To hold the TOmn pin output level Clears the TOmn bit to 0 after the value to be held is set to the port register.

  • Page 233: Operation As External Event Counter

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.8.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TImn pin. When a specified count value is reached, the event counter generates an interrupt.
  • Page 234 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-45. Example of Basic Timing of Operation as External Event Counter TSmn TEmn TImn TCRmn 0000H TDRmn 0003H 0002H INTTMmn 4 events 4 events 3 events Remark 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7) Remark 2.
  • Page 235 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-46. Example of Set Contents of Registers in External Event Counter Mode (1/2) (a) Timer mode register mn (TMRmn) TMRmn CKSm CKSm CCSm STSmn STSmn STSmn CISmn CISmn MDmn MDmn MDmn MDmn Note 1...
  • Page 236 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-46. Example of Set Contents of Registers in External Event Counter Mode (2/2) (b) Timer output register m (TOm) Bit n TOmn 0: Outputs 0 from TOmn. (c) Timer output enable register m (TOEm)
  • Page 237 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-47. Operation Procedure When External Event Counter Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register setting is disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.

  • Page 238: Operation As Frequency Divider (Channels 0 And 3 Only)

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.8.3 Operation as frequency divider (channels 0 and 3 only) The timer array unit can be used as a frequency divider that divides a clock input to the TI0n pin and outputs the result from the TO0n pin.
  • Page 239 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-48. Block Diagram of Operation as Frequency Divider TNFEN0n Edge TI0n pin Noise filter Timer counter register 0n Output detection TO0n pin (TCR0n) controller Timer data register 0n TS0n (TDR0n) Remark n: Channel number (n = 0, 3) R01UH0959EJ0110 Rev.1.10...
  • Page 240 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-49. Example of Basic Timing of Operation as Frequency Divider (MD0n0 = 1) TS0n TE0n TI0n TCR0n 0000H TDR0n 0002H 0001H TO0n INTTM0n Divided by 6 Divided by 4 Remark 1. n: Channel number (n = 0, 3) Remark 2.
  • Page 241 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-50. Example of Set Contents of Registers During Operation as Frequency Divider (1/2) (a) Timer mode register 0n (TMR0n) Note 1 TMR0n CKS0n CKS0n CCS0n S STS0n STS0n STS0n CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0...
  • Page 242 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-50. Example of Set Contents of Registers During Operation as Frequency Divider (2/2) (b) Timer output register 0 (TO0) Bit n TO0n 0: Outputs 0 from TO0n. 1: Outputs 1 from TO0n. (c) Timer output enable register 0 (TOE0)
  • Page 243 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-51. Operation Procedure When Frequency Divider Function Is Used (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register setting is disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1.
  • Page 244 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-51. Operation Procedure When Frequency Divider Function Is Used (2/2) Software Operation Hardware Status Operation Sets the TOE0n bit to 1 (only when operation is start resumed). Sets the TS0n bit to 1.

  • Page 245: Operation As Input Pulse Interval Measurement

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.8.4 Operation as input pulse interval measurement The count value can be captured on detection of a valid edge of TImn pin input and the interval of the pulse input to TImn pin can be measured. In addition, the count value can be captured by setting TSmn to 1 by software during the period of TEmn = 1.
  • Page 246 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-52. Block Diagram of Operation as Input Pulse Interval Measurement CKm1 Operation clock Note 1 Timer counter register mn CKm0 (TCRmn) TNFENmn Edge TImn pin Noise filter detection Interrupt signal Timer data register mn...
  • Page 247 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-54. Example of Set Contents of Registers to Measure Input Pulse Interval (1/2) (a) Timer mode register mn (TMRmn) TMRmn CKSm CKSm CCSm STSmn STSmn STSmn CISmn CISmn MDmn MDmn MDmn MDmn Note 1...
  • Page 248 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-54. Example of Set Contents of Registers to Measure Input Pulse Interval (2/2) (b) Timer output register m (TOm) Bit n TOmn 0: Outputs 0 from TOmn. (c) Timer output enable register m (TOEm)
  • Page 249 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-55. Operation Procedure When Input Pulse Interval Measurement Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register setting is disabled.) Sets the TAUmEN bit of peripheral enable register m to 1.

  • Page 250: Operation As Input Signal High-/Low-Level Width Measurement

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.8.5 Operation as input signal high-/low-level width measurement By starting counting at one edge of the TImn pin input and capturing the number of counts at another edge, the signal width (high-level width/low-level width) of TImn can be measured. The signal width of TImn can be calculated by the following expression.
  • Page 251 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-56. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement CKm1 Operation clock Note 1 Timer counter register mn CKm0 (TCRmn) TNFENmn Interrupt signal Edge Timer data register mn Interrupt TImn pin...
  • Page 252 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-58. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width (1/2) (a) Timer mode register mn (TMRmn) TMRmn CKSm CKSm CCSn0 M/S STSmn STSmn STSmn CISmn CISmn MDmn MDmn MDmn...
  • Page 253 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-58. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width (2/2) (b) Timer output register m (TOm) Bit n TOmn 0: Outputs 0 from TOmn. (c) Timer output enable register m (TOEm)
  • Page 254 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register setting is disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.

  • Page 255: Operation As Delay Counter

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.8.6 Operation as delay counter It is possible to start counting down when the valid edge of the TImn pin input is detected (an external event), and then generate INTTMmn (a timer interrupt) after any specified interval.
  • Page 256 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-61. Example of Basic Timing of Operation as Delay Counter TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn INTTMmn a + 1 b + 1 Remark 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7) Remark 2.
  • Page 257 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-62. Example of Set Contents of Registers to Delay Counter (1/2) (a) Timer mode register mn (TMRmn) TMRmn CKSm CKSm CCSm STSmn STSmn STSmn CISmn CISmn MDmn MDmn MDmn MDmn Note 1 Operation mode of channel n...
  • Page 258 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-62. Example of Set Contents of Registers to Delay Counter (2/2) (b) Timer output register m (TOm) Bit n TOmn 0: Outputs 0 from TOmn. (c) Timer output enable register m (TOEm) Bit n...
  • Page 259 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-63. Operation Procedure When Delay Counter Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register setting is disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.

  • Page 260: Simultaneous Channel Operation Function Of Timer Array Unit

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Simultaneous Channel Operation Function of Timer Array Unit 6.9.1 Operation as one-shot pulse output function By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input to the TImn pin.
  • Page 261 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-64. Block Diagram of Operation as One-Shot Pulse Output Function Master channel (one-count mode) CKm1 Operation clock Timer counter register mn CKm0 (TCRmn) TNFENmn TSmn Interrupt signal Timer data register mn Interrupt (TDRmn)
  • Page 262 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-65. Example of Basic Timing of Operation as One-Shot Pulse Output Function TSmn TEmn TImn Master FFFFH channel TCRmn 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp 0000H Slave channel TDRmp TOmp INTTMmp...
  • Page 263 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-66. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel) (1/2) (a) Timer mode register mn (TMRmn) TMRmn CKSm CKSm CCSm MAST STSmn STSmn STSmn CISmn CISmn...
  • Page 264 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-66. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel) (2/2) (b) Timer output register m (TOm) Bit n TOmn 0: Outputs 0 from TOmn. (c) Timer output enable register m (TOEm)
  • Page 265 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-67. xample of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel) (1/2) (a) Timer mode register mp (TMRmp) TMRmp CKSm CKSm CCSm STSmp STSmp STSmp CISmp CISmp MDmp...
  • Page 266 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-67. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel) (2/2) (b) Timer output register m (TOm) Bit p TOmp 0: Outputs 0 from TOmp. 1: Outputs 1 from TOmp.
  • Page 267 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Operation Procedure of One-Shot Pulse Output Function (1/3) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register setting is disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
  • Page 268 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Operation Procedure of One-Shot Pulse Output Function (2/3) Software Operation Hardware Status Operation Sets the TOEmp bit (slave) to 1 (only when operation start is resumed). The TSmn (master) and TSmp (slave) bits of timer channel start register m (TSm) are set to 1 at the same time.
  • Page 269 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Operation Procedure of One-Shot Pulse Output Function (3/3) Software Operation Hardware Status TAU stop To hold the TOmp pin output level Clears the TOmp bit to 0 after the value to be held is set to the port register.

  • Page 270: Operation As Pwm Function

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.9.2 Operation as PWM function Two channels can be used as a set to generate a pulse of any period and duty factor. The period and duty factor of the output pulse can be calculated by the following expressions.
  • Page 271 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Block Diagram of Operation as PWM Function Master channel (interval timer mode) CKm1 Operation clock Timer counter register mn CKm0 (TCRmn) Interrupt signal Timer data register mn Interrupt TSmn (TDRmn) controller (INTTMmn)
  • Page 272 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-70. Example of Basic Timing of Operation as PWM Function TSmn TEmn FFFFH TCRmn Master 0000H channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp 0000H Slave channel TDRmp TOmp INTTMmp a + 1...
  • Page 273 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-71. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used (1/2) (a) Timer mode register mn (TMRmn) TMRmn CKSm CKSm CCSm MAST STSmn STSmn STSmn CISmn CISmn MDmn MDmn...
  • Page 274 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-71. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used (2/2) (b) Timer output register m (TOm) Bit n TOmn 0: Outputs 0 from TOmn. (c) Timer output enable register m (TOEm)
  • Page 275 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-72. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used (1/2) (a) Timer mode register mp (TMRmp) TMRmp CKSm CKSm CCSm STSmp STSmp STSmp CISmp CISmp MDmp MDmp MDmp...
  • Page 276 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-72. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used (2/2) (b) Timer output register m (TOm) Bit p TOmp 0: Outputs 0 from TOmp. 1: Outputs 1 from TOmp.
  • Page 277 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-73. Operation Procedure When PWM Function Is Used (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register setting is disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
  • Page 278 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-73. Operation Procedure When PWM Function Is Used (2/2) Software Operation Hardware Status Operation Sets the TOEmp bit (slave) to 1 (only when operation start is resumed). The TSmn (master) and TSmp (slave) bits of timer channel start register m (TSm) are set to 1 at the same time.

  • Page 279: Operation As Multiple Pwm Output Function

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.9.3 Operation as multiple PWM output function By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values can be output. For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the following expressions.
  • Page 280 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-74. Block Diagram of Operation as Multiple PWM Output Function (Output Two Types of PWMs) Master channel (interval timer mode) CKm1 Operation clock Timer counter register mn CKm0 (TCRmn) Interrupt signal Timer data register mn...
  • Page 281 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-75. Example of Basic Timing of Operation as Multiple PWM Output Function (Output Two Types of PWMs) TSmn TEmn FFFFH TCRmn Master 0000H channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp 0000H Slave...
  • Page 282 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Remark 1. m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4) p: Slave channel number, q: Slave channel number n < p < q ≤ 7 (Where p and q are integers greater than n) Remark 2.
  • Page 283 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-76. Example of Set Contents of Registers When Multiple PWM Output Function (Master Channel) Is Used (1/2) (a) Timer mode register mn (TMRmn) TMRmn CKSm CKSm CCSm MAST STSmn STSmn STSmn CISmn CISmn...
  • Page 284 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-76. Example of Set Contents of Registers When Multiple PWM Output Function (Master Channel) Is Used (2/2) (b) Timer output register m (TOm) Bit n TOmn 0: Outputs 0 from TOmn. (c) Timer output enable register m (TOEm)
  • Page 285 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-77. Example of Set Contents of Registers When Multiple PWM Output Function (Slave Channel) Is Used (Output Two Types of PWMs) (1/2) (a) Timer mode register mp, mq (TMRmp, TMRmq) TMRmp CKSm CKSm...
  • Page 286 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-77. Example of Set Contents of Registers When Multiple PWM Output Function (Slave Channel) Is Used (Output Two Types of PWMs) (2/2) (b) Timer output register m (TOm) Bit q Bit p TOmq TOmp 0: Outputs 0 from TOmp or TOmq.
  • Page 287 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-78. Operation Procedure When Multiple PWM Output Function Is Used (Output Two Types of PWMs) (1/3) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register setting is disabled.)
  • Page 288 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-78. Operation Procedure When Multiple PWM Output Function Is Used (Output Two Types of PWMs) (2/3) Software Operation Hardware Status Operation (Sets the TOEmp and TOEmq (slave) bits to 1 only start when resuming operation.)
  • Page 289 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-78. Operation Procedure When Multiple PWM Output Function Is Used (Output Two Types of PWMs) (3/3) Software Operation Hardware Status TAU stop To hold the TOmp and TOmq pin output levels Clears the TOmp, TOmq bits to 0 after the value to be held is set to the port register.

  • Page 290: Operation As Two-Channel Input With One-Shot Pulse Output Function

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.9.4 Operation as two-channel input with one-shot pulse output function By using signal input to two pins (TI0n and TI0p), a one-shot pulse having any delay pulse width can be generated. The delay (output delay time) and one-shot pulse width can be calculated by the following expressions.
  • Page 291 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-79. Block Diagram of Operation for Two-channel Input with One-shot Pulse Output Function Master channel (one-count mode) CK01 Operation clock Timer counter register 0n CK00 (TCR0n) TS0n Interrupt signal Timer data register 0n...
  • Page 292 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-80. Example of Basic Timing of Operation for Two-channel Input with One-shot Pulse Output Function TS0n TE0n TI0n FFFFH Master channel TCR0n 0000H TDR0n TO0n INTTM0n TS0p TE0p TI0p FFFFH TCR0p Slave channel...
  • Page 293 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-81. Example of Set Contents of Registers for Two-channel Input with One-shot Pulse Output Function (Master Channel) (1/2) (a) Timer mode register 0n (TMR0nH, TMR0nL) TMR0nH TMR0nL Note 1 TMR0n CKS0n CCS0n M...
  • Page 294 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-81. Example of Set Contents of Registers for Two-channel Input with One-shot Pulse Output Function (Master Channel) (2/2) (b) Timer output register 0 (TO0) Bit n TO0n 0: Outputs 0 from TO0n. (c) Timer output enable register 0 (TOE0)
  • Page 295 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-82. Example of Set Contents of Registers for Two-channel Input with One-shot Pulse Output Function (Slave Channel) (1/2) (a) Timer mode register 0p (TMR0pH, TMR0pL) TMR0pH TMR0pL TMR0p CKS0p CCS0p STS0p STS0p STS0p...
  • Page 296 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-82. Example of Set Contents of Registers for Two-channel Input with One-shot Pulse Output Function (Slave Channel) (2/2) (b) Timer output register 0 (TO0) Bit p TO0p 0: Outputs 0 from TO0p. 1: Outputs 1 from TO0p.
  • Page 297 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-83. Operation Procedure of Two-channel Input with One-shot Pulse Output Function (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to SFR of the setting TAU is disabled.)
  • Page 298 RL78/G15 CHAPTER 6 TIMER ARRAY UNIT Figure 6-83. Operation Procedure of Two-channel Input with One-shot Pulse Output Function (2/2) Software Operation Hardware Status Operation Sets the TOE0p bit of the slave channel to 1 to enable start TO0p operation (only when operation is resumed).

  • Page 299: Cautions When Using Timer Array Unit

    RL78/G15 CHAPTER 6 TIMER ARRAY UNIT 6.10 Cautions When Using Timer Array Unit 6.10.1 Cautions when using timer output Depending on the product, a timer output and other alternate functions may be assigned to some pins. In such case, the outputs of the other alternate functions must be set to their initial states.

  • Page 300: Chapter 7 12-Bit Interval Timer

    RL78/G15 CHAPTER 7 12-BIT INTERVAL TIMER CHAPTER 7 12-BIT INTERVAL TIMER Functions of 12-bit Interval Timer An interrupt request signal (INTIT) is generated at any previously specified time interval. It can be utilized as the trigger for waking up from STOP mode and HALT mode.

  • Page 301: Registers Controlling 12-Bit Interval Timer

    RL78/G15 CHAPTER 7 12-BIT INTERVAL TIMER Registers Controlling 12-bit Interval Timer The 12-bit interval timer is controlled by the following registers. ● Peripheral enable register 0 (PER0) ● Operation speed mode control register (OSMC) ● Interval timer control register (ITMC) 7.3.1...

  • Page 302: Operation Speed Mode Control Register (Osmc)

    RL78/G15 CHAPTER 7 12-BIT INTERVAL TIMER 7.3.2 Operation speed mode control register (OSMC) The WUTMMCK0 bit can be used to control supply of the 12-bit interval timer count clock. Set the WUTMMCK0 bit to 1 before operating the 12-bit interval timer. Do not clear the WUTMMCK0 bit to 0 before counter operation has stopped.

  • Page 303: Interval Timer Control Register (Itmc)

    RL78/G15 CHAPTER 7 12-BIT INTERVAL TIMER 7.3.3 Interval timer control register (ITMC) This register is used to set up the starting and stopping of the 12-bit interval timer operation and to specify the timer compare value. The ITMC register can be set by a 16-bit memory manipulation instruction.

  • Page 304: 12-Bit Interval Timer Operation

    RL78/G15 CHAPTER 7 12-BIT INTERVAL TIMER 12-bit Interval Timer Operation 7.4.1 12-bit interval timer operation timing The count value specified for the ITCMP11 to ITCMP0 bits is used as an interval to operate a 12-bit interval timer that repeatedly generates interrupt requests (INTIT).

  • Page 305: Start Of Count Operation And Re-Enter To Halt/Stop Mode After Returned From Halt/Stop Mode

    RL78/G15 CHAPTER 7 12-BIT INTERVAL TIMER 7.4.2 Start of count operation and re-enter to HALT/STOP mode after returned from HALT/STOP mode When setting the RINTE bit after returned from HALT or STOP mode and entering HALT or STOP mode again, write 1 to the RINTE bit, and confirm the written value of the RINTE bit is reflected or wait for at least one cycle of the count clock.

  • Page 306: Chapter 8 Clock Output/Buzzer Output Controller

    RL78/G15 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for clock output for supply to peripheral ICs. Buzzer output is a function to output a square wave of buzzer frequency.

  • Page 307: Configuration Of Clock Output/Buzzer Output Controller

    RL78/G15 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 8-1. Configuration of Clock Output/Buzzer Output Controller Item Configuration Control registers Clock output select register 0 (CKS0)

  • Page 308: Clock Output Select Register 0 (Cks0)

    RL78/G15 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 8.3.1 Clock output select register 0 (CKS0) This register enables or disables output from the pin for clock output or buzzer frequency output (PCLBUZ0) and sets the output clock. The CKS0 register is set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 309: Registers Controlling Port Functions Of Clock Output/Buzzer Output Pin

    RL78/G15 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 8.3.2 Registers controlling port functions of clock output/buzzer output pin Using the port pin for the clock output/buzzer output controller requires setting of the registers that control the port function multiplexed on the clock output/buzzer output pin (PCLBUZ0 pin): (port mode registers 0, 4 (PM0, PM4), port registers 0, 4 (P0, P4), port mode control register 0 (PMC0), peripheral I/O redirection register 3 (PIOR3)).

  • Page 310: Operations Of Clock Output/Buzzer Output Controller

    RL78/G15 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Operations of Clock Output/Buzzer Output Controller One pin can be used to output a clock or buzzer sound. The PCLBUZ0 pin outputs a clock/buzzer selected by clock output select register 0 (CKS0). 8.4.1 Operation as output pin The PCLBUZ0 pin is output as the following procedure.

  • Page 311: Chapter 9 Watchdog Timer

    RL78/G15 CHAPTER 9 WATCHDOG TIMER CHAPTER 9 WATCHDOG TIMER Functions of Watchdog Timer The counting operation of the watchdog timer is set by the user option byte (000C0H). The watchdog timer operates on the low-speed on-chip oscillator clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated.

  • Page 312: Configuration Of Watchdog Timer

    RL78/G15 CHAPTER 9 WATCHDOG TIMER Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 9-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled and the overflow time are set by the option byte.

  • Page 313: Register Controlling Watchdog Timer

    RL78/G15 CHAPTER 9 WATCHDOG TIMER Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). 9.3.1 Watchdog timer enable register (WDTE) Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again.

  • Page 314: Operation Of Watchdog Timer

    RL78/G15 CHAPTER 9 WATCHDOG TIMER Operation of Watchdog Timer 9.4.1 Controlling operation of watchdog timer <1> When the watchdog timer is used, its operation is specified by the option byte (000C0H). ● Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 18 OPTION BYTE).

  • Page 315: Setting Time Of Watchdog Timer

    RL78/G15 CHAPTER 9 WATCHDOG TIMER 9.4.2 Setting time of watchdog timer Set the overflow time and interval interrupt time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H). If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts counting again by writing “ACH”...

  • Page 316: Chapter 10 A/D Converter

    RL78/G15 CHAPTER 10 A/D CONVERTER CHAPTER 10 A/D CONVERTER The number of analog input channels of the A/D converter differs depending on the product.  Note 1 8-pin products: 3 channels (ANI0, ANI2, ANI3), internal reference voltage (0.815 V (typ.)) ...
  • Page 317 RL78/G15 CHAPTER 10 A/D CONVERTER R01UH0959EJ0110 Rev.1.10 Page 317 of 765 Mar 7, 2023...

  • Page 318: Configuration Of A/D Converter

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.2 Configuration of A/D Converter The A/D converter includes the following hardware. Note 1 1) ANI0 to ANI10 These are the analog input pins of the 11 channels of the A/D converter. They input analog signals to be converted into digital signals.
  • Page 319 RL78/G15 CHAPTER 10 A/D CONVERTER 5) Successive approximation register (SAR) The SAR register is used to set voltage tap data whose values from the comparison voltage generator match the voltage values of the analog input pins, one bit at a time starting from the most significant bit (MSB).

  • Page 320: Registers Controlling A/D Converter

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.3 Registers Controlling A/D Converter The A/D converter is controlled by the following registers. ● Peripheral enable register 0 (PER0) ● A/D converter mode register 0 (ADM0) ● A/D converter mode register 2 (ADM2) ●...

  • Page 321: Peripheral Enable Register 0 (Per0)

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.3.1 Peripheral enable register 0 (PER0) The PER0 register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise.

  • Page 322: A/D Converter Mode Register 0 (Adm0)

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.3.2 A/D converter mode register 0 (ADM0) This register sets the time for converting analog input to digital data, and starts and stops conversion operation. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 323 RL78/G15 CHAPTER 10 A/D CONVERTER Table 10-1. Settings of ADCS and ADCE Bits ADCS ADCE A/D Conversion Operation Conversion stopped state Conversion standby state Setting prohibited Conversion-in-progress state Figure 10-4. Timing Chart when A/D Voltage Comparator Is Used A/D voltage comparator: operation enabled...
  • Page 324 RL78/G15 CHAPTER 10 A/D CONVERTER Table 10-2. 10-Bit Resolution A/D Conversion Time Selection Conversion Time Selection (μs) A/D Converter Mode Conversion Number of Conversion Register 0 (ADM0) Clock Conversion Time Clocks Note 2 1 MHz 4 MHz 8 MHz 10 MHz...
  • Page 325 RL78/G15 CHAPTER 10 A/D CONVERTER Caution 2. When the internal reference voltage is selected as the target of conversion by the A/D converter, the internal reference voltage cannot be used as the reference voltage of the comparator. Caution 3. Only rewrite the FR1, FR0, and LV0 bits while in the conversion standby state (ADCS = 0, ADCE = 1) or conversion is stopped (ADCS = 0, ADCE = 0).

  • Page 326: A/D Converter Mode Register 2 (Adm2)

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.3.3 A/D converter mode register 2 (ADM2) This register is used to set the resolution of the A/D converter. The ADM2 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.

  • Page 327: 10-Bit A/D Conversion Result Register (Adcr)

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.3.4 10-bit A/D conversion result register (ADCR) This is a 16-bit register which holds the result of A/D conversion. The six lower-order bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR). The eight higher- order bits of the conversion result are stored in FFF1FH and the two lower-order bits are stored in the two higher-order bits of FFF1EH.

  • Page 328: 8-Bit A/D Conversion Result Register (Adcrh)

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.3.5 8-bit A/D conversion result register (ADCRH) This is an 8-bit register which holds the result of A/D conversion. When A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR). In the case of 10-bit resolution, the eight higher-order bits are stored.

  • Page 329: Analog Input Channel Specification Register (Ads)

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.3.6 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 330: A/D Test Register (Adtes)

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.3.7 A/D test register (ADTES) This register is used to select V as the analog input to be A/D converted. When the internal reference voltage (0.815 V (typ.)) is selected as the target of A/D conversion, the sampling capacitor must be discharged before A/D conversion of this voltage proceeds.

  • Page 331: A/D Converter Conversion Operations

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. <1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation ends.
  • Page 332 RL78/G15 CHAPTER 10 A/D CONVERTER Figure 10-11. Conversion Operation of A/D Converter (Software Trigger Mode) Writing 1 to ADCS ADCS Conversion time Sampling time A/D converter Conversion Conversion A/D conversion Sampling operation standby standby Conversion Undefined result Conversion ADCR, ADCRH...

  • Page 333: Input Voltage And Conversion Results

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.5 Input Voltage and Conversion Results The relationship between the analog input voltage input to the analog input (ANI0 to ANI10, internal reference voltage) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.
  • Page 334 RL78/G15 CHAPTER 10 A/D CONVERTER Figure 10-12 shows the relationship between the analog input voltage and the A/D conversion result. Figure 10-12. Relationship between Analog Input Voltage and A/D Conversion Result ADCR 1023 FFC0H 1022 FF80H 1021 FF40H A/D conversion...

  • Page 335: A/D Converter Operation Modes

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.6 A/D Converter Operation Modes The operation of the A/D converter is described below. In addition, the setting procedure is described in 10.7 A/D Converter Setup Flowchart. <1> While conversion is stopped, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the conversion standby state.

  • Page 336: A/D Converter Setup Flowchart

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.7 A/D Converter Setup Flowchart The A/D converter setup flowchart is described below. 10.7.1 Setting up ANI0 to ANI10 for A/D conversion Figure 10-14. Setting up ANI0 to ANI10 for A/D Conversion Start of setup...

  • Page 337: Setting Up The Internal Reference Voltage For A/D Conversion

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.7.2 Setting up the internal reference voltage for A/D conversion Figure 10-15. Setting up Internal Reference Voltage for A/D Conversion Start of setup The ADCEN bit of the PER0 register is set (1), and a clock is supplied Set the PER0 register to the A/D converter.

  • Page 338: How To Read A/D Converter Characteristics Table

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.8 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. 10.8.1 Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).

  • Page 339: Quantization Error

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.8.3 Quantization error When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of ±1/2LSB is converted to the same digital code, so a quantization error cannot be avoided.

  • Page 340: Differential Linearity Error

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.8.7 Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 10-18. Zero-Scale Error Figure 10-19. Full-Scale Error Full-scale error...

  • Page 341: Conversion Time

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.8.8 Conversion time This expresses the time from the start of sampling to when the digital output is obtained. The sampling time is included in the conversion time in the characteristics table. 10.8.9 Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample &...

  • Page 342: Notes On A/D Converter

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.9 Notes on A/D Converter 10.9.1 Operating current in STOP mode Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time.

  • Page 343: Analog Input (Anin) Pins

    RL78/G15 CHAPTER 10 A/D CONVERTER Figure 10-22. Analog Input Pin Connection If there is a possibility that noise equal to or higher than V equal to or lower than V may enter, clamp with a diode with a small V value (0.3 V or lower).

  • Page 344: Input Impedance Of Analog Input (Anin) Pins

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.9.6 Input impedance of analog input (ANIn) pins This A/D converter charges a sampling capacitor for sampling during sampling time. Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor flows during sampling.

  • Page 345: 10.9.10 Internal Equivalent Circuit

    RL78/G15 CHAPTER 10 A/D CONVERTER 10.9.10 Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 10-23. Internal Equivalent Circuit of ANIn Pin ANIn Table 10-4. Resistance and Capacitance Values of Equivalent Circuit R1 (kΩ)

  • Page 346: Chapter 11 Comparator

    RL78/G15 CHAPTER 11 COMPARATOR CHAPTER 11 COMPARATOR Caution 16-, 10-, and 8-pin products have only one comparator channel. 20-pin products have two comparator channels. This chapter mainly describes the comparator in the case of 20-pin products. 11.1 Comparator Functions The comparator has the following functions.

  • Page 347: Comparator Configuration

    RL78/G15 CHAPTER 11 COMPARATOR 11.2 Comparator Configuration The comparator consists of the following hardware: 1) IVCMPn Pin The comparator analog input pin. An analog signal to be compared by the comparator is input to this pin. Remark n = 0, 1 2) IVREFn Pin An input pin to supply the reference voltage externally.
  • Page 348 RL78/G15 CHAPTER 11 COMPARATOR Figure 11-1 shows the block diagram of the comparator. Figure 11-1. Block Diagram of the Comparator Comparator mode setting register Comparator filter control register CnMON CnVRF CnENB CnEDG CnEPO CnFCK1 CnFCK0 (COMPMDR) (COMPFIR) Sampling clock Digital filter...

  • Page 349: Registers Controlling The Comparator

    RL78/G15 CHAPTER 11 COMPARATOR 11.3 Registers Controlling the Comparator The following lists the registers to control the comparator. ● Peripheral enable register 0 (PER0) ● Comparator mode setting register (COMPMDR) ● Comparator filter control register (COMPFIR) ● Comparator output control register (COMPOCR) ●...

  • Page 350: Peripheral Enable Register 0 (Per0)

    RL78/G15 CHAPTER 11 COMPARATOR 11.3.1 Peripheral Enable Register 0 (PER0) This register enables or disables clock supply to each peripheral hardware macro. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.

  • Page 351: Comparator Mode Setting Register (Compmdr)

    RL78/G15 CHAPTER 11 COMPARATOR 11.3.2 Comparator Mode Setting Register (COMPMDR) This register selects the comparator reference voltage, starts/stops the comparison operation, and indicates the comparison result state. The COMPMDR register can be set by a 1-bit or 8-bit memory manipulation instruction. Note that the CnMON bit (n = 1, 0) can only be read.
  • Page 352 RL78/G15 CHAPTER 11 COMPARATOR Note 4. After the comparator 0 operation is enabled (C0ENB = 1), the IVREF0 pin state can be read from the C0MON bit setting. When the comparator 0 operation is then disabled (C0ENB = 0), the C0MON bit value is undefined.

  • Page 353: Comparator Filter Control Register (Compfir)

    RL78/G15 CHAPTER 11 COMPARATOR 11.3.3 Comparator Filter Control Register (COMPFIR) This register selects the effective edge for the comparator interrupt signal, and enables or disables the digital filter. If noise elimination is required, set the CnFCK1 and CnFCK0 bits (n = 1, 0) so that the digital filter is enabled. When the digital filter is enabled, the comparator output is checked if its level remains the same for three consecutive digital filter sampling clock cycles.
  • Page 354 RL78/G15 CHAPTER 11 COMPARATOR Note 3. To use the comparator in STOP mode, disable the digital filter (C1FCK1 and C1FCK0 = 00B). Note 4. If the C0EDG, C0EPO, and C0FCK1 or C0FCK0 bits are changed while operation of the comparator 0 is enabled, a comparator detection 0 interrupt (INTCMP0) may be generated.

  • Page 355: Comparator Output Control Register (Compocr)

    RL78/G15 CHAPTER 11 COMPARATOR 11.3.4 Comparator Output Control Register (COMPOCR) This register selects the comparator response speed, controls the VCOUTn output, and enables or disables the interrupt request signal. Remark n = 0, 1 The COMPOCR register can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 356: Registers Controlling Port Functions Of Comparator I/O Pins

    RL78/G15 CHAPTER 11 COMPARATOR 11.3.5 Registers Controlling Port Functions of Comparator I/O Pins The port mode register 0 (PM0), port mode register 2 (PM2), port register 0 (P0), port register 2 (P2), port mode control register 0 (PMC0), and port mode control register 2 (PMC2) should be appropriately set to control the functions of the port pins that are also used for input and output of the comparator.

  • Page 357: Comparator N Operation (N = 0, 1)

    RL78/G15 CHAPTER 11 COMPARATOR 11.4 Comparator n Operation (n = 0, 1) The CnMON bit in the COMPMDR register is set to 1 when the analog input voltage on the IVCMPn (n = 0, 1) pin is higher than the reference voltage. When lower, the CnMON bit is set to 0.

  • Page 358: Comparator N Digital Filter Operation (N = 0, 1)

    RL78/G15 CHAPTER 11 COMPARATOR 11.4.1 Comparator n Digital Filter Operation (n = 0, 1) Comparator n incorporates a digital filter. The sampling clock is selected by the CnFCK1 and CnFCK0 bits in the COMPFIR register. The comparator n output signal is sampled every sampling clock, and when the level of the output signal matches three times, the digital filter output changes at the next sampling clock.

  • Page 359: Comparator Setting Flowcharts

    RL78/G15 CHAPTER 11 COMPARATOR 11.5 Comparator Setting Flowcharts The following shows the comparator setting flowcharts. R01UH0959EJ0110 Rev.1.10 Page 359 of 765 Mar 7, 2023...

  • Page 360: Enabling Comparator Operation (In The Case Of Cmp0)

    RL78/G15 CHAPTER 11 COMPARATOR 11.5.1 Enabling Comparator Operation (in the Case of CMP0) Figure 11-8. Procedure for Enabling Comparator Operation Start Set the CMPEN bit in PER0 to 1 to supply clock to comparator. (Mandatory) Set the PER0 register Set the ports for the IVCMP0 and IVREF0 pins to analog input function.

  • Page 361: Disabling Comparator Operation (In The Case Of Cmp0)

    RL78/G15 CHAPTER 11 COMPARATOR 11.5.2 Disabling Comparator Operation (in the Case of CMP0) Figure 11-9. Procedure for Disabling Comparator Operation Start Disable comparator interrupt request. Set the C0IE bit (Mandatory)  Clear the C0IE bit in COMPOCR to 0 to disable interrupt request.

  • Page 362: Chapter 12 Serial Array Unit

    ), UART, and simplified I C communication. Function assignment of each channel supported by the RL78/G15 is as shown below. Note 1. Although the CSI function is generally called SPI, it is also called CSI in this product, so it is referred to as such in this manual.

  • Page 363: Functions Of Serial Array Unit

    CHAPTER 12 SERIAL ARRAY UNIT 12.1 Functions of Serial Array Unit Each serial interface supported by the RL78/G15 has the following features. 12.1.1 Simplified SPI (CSI00, CSI01) Data is transmitted or received in synchronization with the serial clock (SCK) output from the master.

  • Page 364: Uart (Uart0)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.1.2 UART (UART0) This is a start-stop synchronization communication function using two lines: serial data transmission (TxD) and serial data reception (RxD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.

  • Page 365: Simplified I C (Iic00, Iic01)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.1.3 Simplified I C (IIC00, IIC01) This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master.

  • Page 366: Configuration Of Serial Array Unit

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.2 Configuration of Serial Array Unit The serial array unit includes the following registers, and input and output pins. Table 12-1. Configuration of Serial Array Unit Item Configuration Note 1 Shift register 8 or 9 bits...
  • Page 367 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-1 shows the block diagram of serial array unit 0. Figure 12-1. Block Diagram of Serial Array Unit 0 Serial output register 0 (SO0) Noise filter enable register 0 (NFEN0) CKO01 CKO00 SO01 SO00...

  • Page 368: Shift Register

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.2.1 Shift Register This is a 9-bit register that converts parallel data into serial data or vice versa. In case of the UART communication of nine bits of data, nine bits (bits 0 to 8) are used.

  • Page 369: Lower 8 Or 9 Bits Of The Serial Data Register Mn (Sdrmn)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.2.2 Lower 8 or 9 bits of the serial data register mn (SDRmn) The SDRmn is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) or bits 7 to 0 (lower 8 bits) function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (f When data is received, parallel data converted by the shift register is stored in the lower 8 or 9 bits.
  • Page 370 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-2. Format of Serial Data Register mn (SDRmn) (mn = 00, 01) Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) After reset: 0000H FFF11H (SDR00) FFF10H (SDR00) Symbol SDRmn Shift register Remark For the function of the higher 7 bits of the SDRmn register, see 12.3 Registers to Control the Serial Array Unit.

  • Page 371: Registers To Control The Serial Array Unit

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3 Registers to Control the Serial Array Unit The following registers are used to control the serial array unit. ● Peripheral enable register 0 (PER0) ● Serial clock select register m (SPSm) ● Serial mode register mn (SMRmn) ●...

  • Page 372: Peripheral Enable Register 0 (Per0)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.1 Peripheral enable register 0 (PER0) The PER0 register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise.

  • Page 373: Serial Clock Select Register M (Spsm)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.2 Serial clock select register m (SPSm) The SPSm is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register, and CKm0 is selected by bits 3 to 0.

  • Page 374: Serial Mode Register Mn (Smrmn)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.3 Serial mode register mn (SMRmn) The SMRmn register is used to set an operation mode of channel n. It is also used to select an operation clock (f specify whether the serial clock (f...
  • Page 375 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-5. Format of Serial Mode Register mn (SMRmn) (2/2) Address: F0110H, F0111H (SMR00) to F0112H, F0113H (SMR01) After reset: 0020H Symbol SMRmn CKSm CCSm STSmn SISmn MDmn MDmn MDmn Note 1 Note 1...

  • Page 376: Serial Communication Operation Setting Register Mn (Scrmn)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.4 Serial communication operation setting register mn (SCRmn) The SCRmn is a communication operation setting register of channel n. It is used to set a data transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit, stop bit, and data length.
  • Page 377 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-6. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/2) Address: F0118H, F0119H (SCR00) to F011AH, F011BH (SCR01) After reset: 0087H Symbol SCRmn TXEmn RXEm DAPm CKPm EOCm PTCm PTCm DIRmn SLCmn...
  • Page 378 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Note 2. When using CSImn not with EOCmn = 0, error interrupt INTSREn may be generated. Note 3. 0 is always added regardless of the data contents. Caution Be sure to clear bits 3, 6, and 11 to 0 (Also clear bit 5 of the SCR01 register to 0). Be sure to set bit 2 to 1.

  • Page 379: Serial Data Register Mn (Sdrmn)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.5 Serial data register mn (SDRmn) The SDRmn is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) of SDR00 and SDR01 function as a transmit/receive buffer register, and bits 15 to 9 (higher 7...
  • Page 380 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Caution 1. Setting SDRmn[15:9] to 0000000B or 0000001B is prohibited when UART is used. Caution 2. Setting SDRmn[15:9] to 0000000B is prohibited when simplified I C is used. Set SDRmn[15:9] to 0000001B or greater.

  • Page 381: Serial Flag Clear Trigger Register Mn (Sirmn)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.6 Serial flag clear trigger register mn (SIRmn) The SIRmn is a trigger register that is used to clear each error flag of channel n. When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of serial status register mn is cleared to 0.

  • Page 382: Serial Status Register Mn (Ssrmn)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.7 Serial status register mn (SSRmn) The SSRmn register indicates the state of communications and occurrence of errors for channel n. The errors indicated by this register are a framing error, parity error, and overrun error.
  • Page 383 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-9. Format of Serial Status Register mn (SSRmn) (2/2) Address: F0100H, F0101H (SSR00) to F0102H, F0103H (SSR01) After reset: 0000H Symbol SSRmn TSFmn BFFmn FEFmn PEFmn OVFm Note 1 FEFmn Framing error detection flag of channel n Note 1 No error occurs.

  • Page 384: Serial Channel Start Register M (Ssm)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.8 Serial channel start register m (SSm) The SSm is a trigger register that is used to enable starting communication/count by each channel. When 1 is written to a bit (SSmn) of this register, the corresponding bit (SEmn) of serial channel enable status register m (SEm) is set to 1 (operation is enabled).

  • Page 385: Serial Channel Stop Register M (Stm)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.9 Serial channel stop register m (STm) The STm is a trigger register that is used to enable stopping communication/count by each channel. When 1 is written to a bit (STmn) of this register, the corresponding bit (SEmn) of serial channel enable status register m (SEm) is cleared to 0 (operation is stopped).

  • Page 386: Serial Channel Enable Status Register M (Sem)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.10 Serial channel enable status register m (SEm) The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped. When 1 is written to a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1. When 1 is written to a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0.

  • Page 387: Serial Output Enable Register M (Soem)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.11 Serial output enable register m (SOEm) The SOEm register is used to enable or stop output of the serial communication operation of each channel. For channel n whose serial output is enabled, the value of the SOmn bit of serial output register m (SOm) to be described later cannot be rewritten by software, and a value reflected by a communication operation is output from the serial data output pin.

  • Page 388: Serial Output Register M (Som)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.12 Serial output register m (SOm) The SOm is a buffer register for serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n.

  • Page 389: Serial Output Level Register M (Solm)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.13 Serial output level register m (SOLm) The SOLm register is used to set inversion of the data output level of each channel. This register can be set only in the UART mode. Be sure to set 0 for the bit corresponding the channel used in the simplified SPI (CSI) mode or simplified I C mode.
  • Page 390 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-16. Examples of Reverse Transmit Data (a) Non-reverse Output (SOLmn = 0) SOLmn = 0 output TxDq Transmit data (b) Reverse Output (SOLmn = 1) SOLmn = 1 output TxDq Transmit data (inverted)

  • Page 391: Input Switch Control Register (Isc)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.14 Input switch control register (ISC) The ISC1 and ISC0 bits in the ISC register are used to handle the combination of the external interrupt and the timer array unit at the time of baud rate correction of UART0.

  • Page 392: Noise Filter Enable Register 0 (Nfen0)

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.15 Noise filter enable register 0 (NFEN0) The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel.

  • Page 393: 12.3.16 Registers Controlling Port Functions Of Serial Input/Output Pins

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.3.16 Registers controlling port functions of serial input/output pins Using the serial array unit requires setting of the registers that control the port functions multiplexed on the target channel (port mode register (PMxx), port register (Pxx), port output mode register (POMxx), port mode control register (PMCxx)).

  • Page 394: Operation Stop Mode

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.4 Operation Stop Mode Each serial interface of serial array unit has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pin for serial interface can be used as port function pins in this mode.

  • Page 395: Stopping The Operation By Channels

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.4.2 Stopping the Operation by Channels The stopping of the operation by channels is set using each of the following registers. Figure 12-20. Each Register Setting When Stopping the Operation by Channels (1/2) (a) Serial channel stop register m (STm) … The STm is a trigger register that is used to enable stopping communication/count by each channel.
  • Page 396 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-20. Each Register Setting When Stopping the Operation by Channels (2/2) (d) Serial output register m (SOm) … The SOm is a buffer register for serial output of each channel. CKOm CKOm SOm1 SOm0...

  • Page 397: Operation Of Simplified Spi (Csi00, Csi01) Communication

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.5 Operation of Simplified SPI (CSI00, CSI01) Communication This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines. [Data transmission/reception] ● Data length of 7 or 8 bits ●...
  • Page 398 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT The channels supporting simplified SPI (CSI00, CSI01) are channels 0 and 1 of SAU0.  10- and 8-pin products Unit Channel Used as simplified SPI (CSI) Used as UART Used as Simplified I CSI00...

  • Page 399: Master Transmission

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.5.1 Master Transmission Master transmission is that the RL78 microcontroller outputs a transfer clock and transmits data to another device. Simplified SPI CSI00 CSI01 Target channel Channel 0 of SAU0 Channel 1 of SAU0...
  • Page 400 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-21. Example of Contents of Registers for Master Transmission of simplified SPI (CSI00, CSI01) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSm CCSm STSm SISmn MDmn MDmn MDmn Operation clock (f...
  • Page 401 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-21. Example of Contents of Registers for Master Transmission of simplified SPI (CSI00, CSI01) (2/2) (e) Serial output enable register m (SOEm) … Set only the bit of the target channel to 1.
  • Page 402 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-22. Initial Setting Procedure for Master Transmission Starting initial setting Release the serial array unit from the reset state, and Setting the PER0 register start clock supply to the serial array unit.
  • Page 403 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-24. Procedure for Resuming Master Transmission Starting setting for resumption Wait until stop the communication target (slave) or communication operation completed. (Essential) Slave ready? Disable data output and clock output of the target...
  • Page 404 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-25. Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2...
  • Page 405 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-26. Flowchart of Master Transmission (in Single-Transmission Mode) Starting simplified SPI (CSI) communication For the initial setting, refer to Figure 12-22. SAU initial setting (Select the transfer end interrupt.) Set data for transmission and the number of data. Clear communication end flag.
  • Page 406 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-27. Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = SSmn <1> STmn <6> SEmn SDRmn Transmit data 1...
  • Page 407 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-28. Flowchart of Master Transmission (in Continuous Transmission Mode) Starting setting For the initial setting, refer to Figure 12-22. <1> SAU initial setting (Select buffer empty interrupt.) Set the data pointer for transmission and the number of data items. Clear...

  • Page 408: Master Reception

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.5.2 Master Reception Master reception is that the RL78 microcontroller outputs a transfer clock and receives data from another device. Simplified SPI CSI00 CSI01 Target channel Channel 0 of SAU0 Channel 1 of SAU0...
  • Page 409 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-29. Example of Contents of Registers for Master Reception of simplified SPI (CSI00, CSI01) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSm CCSm STSm SISmn MDmn MDmn MDmn Operation clock (f...
  • Page 410 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-29. Example of Contents of Registers for Master Reception of simplified SPI (CSI00, CSI01) (2/2) (e) Serial output enable register m (SOEm) … This register is not used in this mode. SOEm SOEm SOEm ×...
  • Page 411 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-30. Initial Setting Procedure for Master Reception Starting initial setting Release the serial array unit from the reset state, and Setting the PER0 register start clock supply to the serial array unit.
  • Page 412 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-32. Procedure for Resuming Master Reception Starting setting for resumption Wait until stop the communication target (slave) or communication operation completed. Completing slave (Essential) preparations? Disable clock output of the target channel by setting a...
  • Page 413 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 12-33. Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2 Receive data 3...
  • Page 414 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-34. Flowchart of Master Reception (in Single-Reception Mode) Starting simplified SPI (CSI) communication For the initial setting, refer to Figure 12-30. SAU initial setting (Select transfer end interrupt) Setting storage area of the receive data, number of communication data...
  • Page 415 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous reception mode) Figure 12-35. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn <1> STmn <8> SEmn Receive data 3...
  • Page 416 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-36. Flowchart of Master Reception (in Continuous Reception Mode) Starting simplified SPI (CSI) communication For the initial setting, refer to Figure 12-30. <1> SAU initial setting (Select buffer empty interrupt) Setting storage area of the receive data, number of communication data...
  • Page 417 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 12-35 Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0). R01UH0959EJ0110 Rev.1.10...

  • Page 418: Master Transmission/Reception

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.5.3 Master Transmission/Reception Master transmission/reception is that the RL78 microcontroller outputs a transfer clock and transmits/receives data to/from another device. Simplified SPI CSI00 CSI01 Target channel Channel 0 of SAU0 Channel 1 of SAU0...
  • Page 419 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-37. Example of Contents of Registers for Master Transmission/Reception of simplified SPI (CSI00, CSI01) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSm CCSm STSm SISmn MDmn MDmn MDmn Operation clock (f...
  • Page 420 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-37. Example of Contents of Registers for Master Transmission/Reception of simplified SPI (CSI00, CSI01) (2/2) (e) Serial output enable register m (SOEm) … Set only the bit of the target channel to 1.
  • Page 421 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-38. Initial Setting Procedure for Master Transmission/Reception Starting initial setting Release the serial array unit from the reset state, and Setting the PER0 register start clock supply to the serial array unit.
  • Page 422 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-40. Procedure for Resuming Master Transmission/Reception Starting setting for resumption Wait until stop the communication target (slave) or communication operation completed. Completing slave (Essential) preparations? Disable data output and clock output of the target...
  • Page 423 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 12-41. Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2 Receive data 3...
  • Page 424 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-42. Flowchart of Master Transmission/Reception (in Single-Transmission/Reception Mode) Starting simplified SPI (CSI) communication For the initial setting, refer to Figure 12-38. SAU initial setting (Select transfer end interrupt) Setting storage data and number of data for transmission/reception data...
  • Page 425 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 12-43. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn <1> STmn <8> SEmn Receive data 3...
  • Page 426 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-44. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, refer to Figure 12-38. <1> SAU initial setting (Select buffer empty interrupt) Setting storage data and number of data for transmission/reception data...
  • Page 427 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 12-43 Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0). R01UH0959EJ0110 Rev.1.10...

  • Page 428: Slave Transmission

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.5.4 Slave Transmission Slave transmission is that the RL78 microcontroller transmits data to another device in the state of a transfer clock being input from another device. Simplified SPI CSI00 CSI01 Target channel Channel 0 of SAU0...
  • Page 429 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-45. Example of Contents of Registers for Slave Transmission of simplified SPI (CSI00, CSI01) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSm CCSm STSm SISmn MDmn MDmn MDmn Operation clock (f...
  • Page 430 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-45. Example of Contents of Registers for Slave Transmission of simplified SPI (CSI00, CSI01) (2/2) (e) Serial output enable register m (SOEm) … Set only the bit of the target channel to 1.
  • Page 431 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-46. Initial Setting Procedure for Slave Transmission Starting initial setting Release the serial array unit from the reset state, and Setting the PER0 register start clock supply to the serial array unit.
  • Page 432 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-48. Procedure for Resuming Slave Transmission Starting setting for resumption Wait until stop the communication target (master) or operation completed. Completing master (Essential) preparations? Disable data output of the target channel by setting a port...
  • Page 433 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-49. Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2...
  • Page 434 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-50. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting simplified SPI (CSI) communication For the initial setting, refer to Figure 12-46. SAU initial setting (Select transfer end interrupt) Set storage area and the number of data for transmit data...
  • Page 435 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-51. Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = SSmn <1> STmn <6> SEmn SDRmn Transmit data 1...
  • Page 436 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-52. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting setting For the initial setting, refer to Figure 12-46. <1> SAU initial setting (Select buffer empty interrupt) Set storage area and the number of data for transmit data...

  • Page 437: Slave Reception

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.5.5 Slave Reception Slave reception is that the RL78 microcontroller receives data from another device in the state of a transfer clock being input from another device. Simplified SPI CSI00 CSI01 Target channel Channel 0 of SAU0...
  • Page 438 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-53. Example of Contents of Registers for Slave Reception of simplified SPI (CSI00, CSI01) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSm CCSm STSm SISmn MDmn MDmn MDmn Operation clock (f...
  • Page 439 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-53. Example of Contents of Registers for Slave Reception of simplified SPI (CSI00, CSI01) (2/2) (e) Serial output enable register m (SOEm) … This register is not used in this mode. SOEm SOEm SOEm ×...
  • Page 440 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-54. Initial Setting Procedure for Slave Reception Starting initial setting Release the serial array unit from the reset state, and Setting the PER0 register start clock supply to the serial array unit.
  • Page 441 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-56. Procedure for Resuming Slave Reception Starting setting for resumption Wait until stop the communication target (master) or operation completed Completing master (Essential) preparations? Disable data output of the target channel by setting a port...
  • Page 442 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 12-57. Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Receive data 1...
  • Page 443 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-58. Flowchart of Slave Reception (in Single-Reception Mode) Starting simplified SPI (CSI) communication For the initial setting, refer to Figure 12-54. SAU initial setting (Select transfer end interrupt) Clear storage area setting and the number of receive data...

  • Page 444: Slave Transmission/Reception

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.5.6 Slave Transmission/Reception Slave transmission/reception is that the RL78 microcontroller transmits/receives data to/from another device in the state of a transfer clock being input from another device. Simplified SPI CSI00 CSI01 Target channel Channel 0 of SAU0...
  • Page 445 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-59. Example of Contents of Registers for Slave Transmission/Reception of simplified SPI (CSI00, CSI01) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSm CCSm STSm SISmn MDmn MDmn MDmn Operation clock (f...
  • Page 446 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-59. Example of Contents of Registers for Slave Transmission/Reception of simplified SPI (CSI00, CSI01) (2/2) (e) Serial output enable register m (SOEm) … Set only the bit of the target channel to 1.
  • Page 447 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-60. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Release the serial array unit from the reset state, and Setting the PER0 register start clock supply to the serial array unit.
  • Page 448 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-61. Procedure for Stopping Slave Transmission/Reception Starting setting to stop If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait.) (Selective) TSFmn = 0?
  • Page 449 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-62. Procedure for Resuming Slave Transmission/Reception Starting setting for resumption Wait until stop the communication target (master) or operation completed. Completing master (Essential) preparations? Disable data output of the target channel by setting a port...
  • Page 450 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 12-63. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2 Receive data 3...
  • Page 451 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-64. Flowchart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) Starting simplified SPI (CSI) communication For the initial setting, refer to Figure 12-60. SAU initial setting (Select transfer end interrupt) Setting storage area and number of data for transmission/reception data...
  • Page 452 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 12-65. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn <1> STmn <8> SEmn Receive data 3...
  • Page 453 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-66. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, refer to Figure 12-60. <1> SAU initial setting (Select buffer empty interrupt) Setting storage area and number of data for transmission/reception data...
  • Page 454 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Caution Be sure to set transmit data to the SlOp register before the clock from the master is started. Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 12-65 Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0).

  • Page 455: Calculating Transfer Clock Frequency

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.5.7 Calculating Transfer Clock Frequency The transfer clock frequency for simplified SPI (CSI00, CSI01) communication can be calculated by the following expressions. (1) Master ( Transfer clock frequency ) = { Operation clock (f ) frequency of target channel } ÷...
  • Page 456 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Table 12-2. Selection of Operation Clock For Simplified SPI Note 1 SMRmn SPSm Register Operation Clock (f Register CKSmn = 16 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz...

  • Page 457: Procedure For Processing Errors That Occurred During Simplified Spi (Csi00, Csi01) Communication

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Note 1. When changing the clock selected for f (by changing the system clock control register (CKC) value), do so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit (SAU).

  • Page 458: Operation Of Uart (Uart0) Communication

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.6 Operation of UART (UART0) Communication This is a start-stop synchronization communication function using two lines: serial data transmission (TxD) and serial data reception (RxD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
  • Page 459 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT UART0 uses channels 0 and 1 of SAU0.  10- and 8-pin products Unit Channel Used as simplified SPI (CSI) Used as UART Used as Simplified I CSI00 UART0 IIC00 — —  20- and 16-pin products...

  • Page 460: Uart Transmission

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.6.1 UART Transmission UART transmission is an operation to transmit data from the RL78 microcontroller to another device asynchronously (start-stop synchronization). Of two channels used for UART, the even channel is used for UART transmission.
  • Page 461 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-68. Example of Contents of Registers for UART Transmission of UART (UART0) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSm CCSm MDmn MDmn MDmn Operation clock (f ) of channel n...
  • Page 462 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-68. Example of Contents of Registers for UART Transmission of UART (UART0) (2/2) (e) Serial output register m (SOm) … Set only the bit of the target channel. CKOm CKOm SOm1 SOm0 Note 2 ×...
  • Page 463 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-69. Initial Setting Procedure for UART Transmission Starting initial setting Release the serial array unit from the reset state, and Setting the PER0 register start clock supply to the serial array unit.
  • Page 464 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-70. Procedure for Stopping UART Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait.) (Selective) TSFmn = 0?
  • Page 465 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-71. Procedure for Resuming UART Transmission Starting setting for resumption Wait until stop the communication target or communication operation completed Communication target (Essential) is ready ? Disable data output of the target channel by setting a port...
  • Page 466 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-72. Timing Chart of UART Transmission (in Single-Transmission Mode) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 TxDq pin Transmit data 1...
  • Page 467 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-73. Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication For the initial setting, refer to Figure 12-69. SAU initial setting (Select transfer end interrupt) Set data for transmission and the number of data. Clear communication end flag...
  • Page 468 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-74. Timing Chart of UART Transmission (in Continuous Transmission Mode) SSmn <1> STmn <6> SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 TxDq pin...
  • Page 469 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-75. Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART communication For the initial setting, refer to Figure 12-69. <1> SAU initial setting (Select buffer empty interrupt) Set the data pointer for transmission and the number of data items. Clear...

  • Page 470: Uart Reception

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.6.2 UART Reception UART reception is an operation wherein the RL78 microcontroller asynchronously receives data from another device (start-stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set.
  • Page 471 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-76. Example of Contents of Registers for UART Reception of UART (UART0) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSm CCSm STSm SISmn MDmn MDmn MDmn Operation clock (f...
  • Page 472 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-76. Example of Contents of Registers for UART Reception of UART (UART0) (2/2) (e) Serial output register m (SOm) … This register is not used in this mode. CKOm CKOm SOm1 SOm0 ×...
  • Page 473 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-77. Initial Setting Procedure for UART Reception Starting initial setting Release the serial array unit from the reset state, and Setting the PER0 register start clock supply to the serial array unit.
  • Page 474 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-79. Procedure for Resuming UART Reception Starting setting for resumption Wait until the communication target stops or communication operation is completed. Communication target (Essential) is ready? Re-set the register to change the operation clock setting.
  • Page 475 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow Figure 12-80. Timing Chart of UART Reception SSmn STmn SEmn Receive data 3 SDRmn Receive data 1 Receive data 2 RxDq pin Receive data 1 Receive data 2 Receive data 3...
  • Page 476 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-81. Flowchart of UART Reception Starting UART communication For the initial setting, refer to Figure 12-77. SAU initial setting (setting to mask for error interrupt) Setting storage area of the receive data, number of communication data...

  • Page 477: Calculating Baud Rate

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.6.3 Calculating Baud Rate (1) Baud rate calculation expression The baud rate for UART (UART0) communication can be calculated by the following expressions. (Baud rate) = { Operation clock (f ) frequency of target channel } ÷ ( SDRmn[15: 9] + 1 ) ÷ 2[bps] Caution Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B, 0000001B) is prohibited.
  • Page 478 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Table 12-3. Selection of Operation Clock For UART Note 1 SMRmn SPSm Register Operation Clock (f Register CKSmn = 16 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz...
  • Page 479 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Note 1. When changing the clock selected for f (by changing the system clock control register (CKC) value), do so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit (SAU).
  • Page 480 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (2) Baud rate error during transmission The baud rate error of UART (UART0) communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
  • Page 481 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (3) Permissible baud rate range for reception The permissible baud rate range for reception during UART (UART0) communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.

  • Page 482: Procedure For Processing Errors That Occurred During Uart (Uart0) Communication

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.6.4 Procedure for Processing Errors that Occurred During UART (UART0) Communication The procedure for processing errors that occurred during UART (UART0) communication is described in Figure 12-83 and Figure 12-84. Figure 12-83. Processing Procedure in Case of Parity Error or Overrun Error...

  • Page 483: Operation Of Simplified I C (Iic00, Iic01) Communication

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.7 Operation of Simplified I C (IIC00, IIC01) Communication This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master.
  • Page 484 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT The channel supporting simplified I C (IIC00, IIC01) is channels 0 and 1 of SAU0.  10- and 8-pin products Unit Channel Used as simplified SPI (CSI) Used as UART Used as Simplified I...

  • Page 485: Address Field Transmission

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.7.1 Address Field Transmission Address field transmission is a transmission operation that first executes in I C communication to identify the target for transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are transmitted in one frame.
  • Page 486 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-85. Example of Contents of Registers for Address Field Transmission of Simplified I C (IIC00, IIC01) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSm CCSm STSm SISmn MDmn MDmn...
  • Page 487 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-85. Example of Contents of Registers for Address Field Transmission of Simplified I C (IIC00, IIC01) (2/2) (f) Serial channel start register m (SSm) … Set only the bit of the target channel to 1.
  • Page 488 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-86. Initial Setting Procedure for Simplified I C Address Field Transmission Starting initial setting Release the serial array unit from the reset state, and Setting the PER0 register start clock supply to the serial array unit.
  • Page 489 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow Figure 12-87. Timing Chart of Address Field Transmission SSmn SEmn SOEmn SDRmn Address field transmission SCLr output CKOm bit manipulation SDAr output SOmn bit manipulation Address SDAr input Shift Shift operation...
  • Page 490 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-88. Flowchart of Simplified I C Address Field Transmission Transmitting address field For the initial setting, refer to Figure 12-86. Default setting Set the SOmn bit to 0. Writing 0 to the SOmn bit...

  • Page 491: Data Transmission

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.7.2 Data Transmission Data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address field. After all data are transmitted to the slave, a stop condition is generated and the bus is released.
  • Page 492 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-89. Example of Contents of Registers for Data Transmission of Simplified I C (IIC00, IIC01) (a) Serial mode register mn (SMRmn) … Do not manipulate this register during data transmission/reception.
  • Page 493 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Note 1. The SMR01 register only. Note 2. The SCR00 register only. Note 3. Because the setting is completed by address field transmission, setting is not required. Note 4. The value varies depending on the communication data during communication operation.
  • Page 494 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (2) Processing flow Figure 12-90. Timing Chart of Data Transmission SSmn “L” SEmn “H” SOEmn “H” SDRmn Transmit data 1 SCLr output SDAr output Address SDAr input Shift Shift operation register mn INTIICr TSFmn Figure 12-91.

  • Page 495: Data Reception

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.7.3 Data Reception Data reception is an operation to receive data from the target for transfer (slave) after transmission of an address field. After all data are received from the slave, a stop condition is generated and the bus is released.
  • Page 496 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-92. Example of Contents of Registers for Data Reception of Simplified I C (IIC00, IIC01) (a) Serial mode register mn (SMRmn) … Do not manipulate this register during data transmission/reception.
  • Page 497 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Note 1. The SMR01 and SMR03 registers only Note 2. The SCR00 and SCR02 registers only Note 3. Because the setting is completed by address field transmission, setting is not required. Note 4. The value varies depending on the communication data during communication operation.
  • Page 498 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT (2) Processing flow Figure 12-93. Timing Chart of Data Reception (a) When starting data reception SSmn STmn SEmn SOEmn “H” TXEmn, TXEmn = 1 / RXEmn = 0 TXEmn = 0 / RXEmn = 1...
  • Page 499 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-94. Flowchart of Data Reception Address field transmission completed Data reception Stop operation for rewriting SCRmn register. Writing 1 to the STmn bit Set the operation of the channel to receive- Writing 0 to the TXEmn bit, and only mode.

  • Page 500: Stop Condition Generation

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.7.4 Stop Condition Generation After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released. (1) Processing flow Figure 12-95. Timing Chart of Stop Condition Generation...

  • Page 501: Calculating Transfer Rate

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.7.5 Calculating Transfer Rate The transfer rate for simplified I C (IIC00, IIC01) communication can be calculated by the following expressions. (Transfer rate) = { Operation clock (f ) frequency of target channel } ÷ ( SDRmn[15: 9] + 1 ) ÷ 2 Caution SDRmn[15:9] must not be set to 00000000B.
  • Page 502 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Table 12-4. Selection of Operation Clock For Simplified I Note 1 SMRmn SPSm Register Operation Clock (f Register CKSmn = 16 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500k Hz...
  • Page 503 RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT Here is an example of setting an I C transfer rate where f = 16 MHz. C Transfer Mode = 16 MHz (Desired Transfer Rate) Operation Clock (f SDRmn[15:9] Calculated Transfer Rate Error from Desired Transfer...

  • Page 504: Procedure For Processing Errors That Occurred During Simplified I

    RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT 12.7.6 Procedure for Processing Errors that Occurred during Simplified I C (IIC00, IIC01) Communication The procedure for processing errors that occurred during simplified I C (IIC00, IIC01) communication is described in Figure 12-97 and Figure 12-98.

  • Page 505: Chapter 13 Serial Interface Iica

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA CHAPTER 13 SERIAL INTERFACE IICA 13.1 Functions of Serial Interface IICA The serial interface IICA has the following three modes. 1) Operation stop mode This mode is used when serial transfers are not performed. The operating power can be reduced in this mode.
  • Page 506 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-1 shows a block diagram of serial interface IICA. Figure 13-1. Block Diagram of Serial Interface IICA Internal bus IICA status register 0 (IICS0) WUP0 ALD0 EXC0 COI0 TRC0 STD0 SPD0 MSTS0 ACKD0...
  • Page 507 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-2 shows a serial bus configuration example. Figure 13-2. Serial Bus Configuration Example Using I C Bus Serial data bus Master CPU2 Master CPU1 SDAA0 SDAA0 Slave CPU1 Slave CPU2 Serial clock SCLA0...

  • Page 508: Configuration Of Serial Interface Iica

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.2 Configuration of Serial Interface IICA Serial interface IICA includes the following hardware. Table 13-1. Configuration of Serial Interface IICA Item Configuration Registers IICA shift register 0 (IICA0) Slave address register 0 (SVA0） Control registers...
  • Page 509 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (1) IICA shift register 0 (IICA0) The IICA0 register is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial clock. The IICA0 register can be used for both transmission and reception.
  • Page 510 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (3) SO latch The SO latch is used to retain the output level of the SDAA0 pin. (4) Wakeup controller This circuit generates an interrupt request (INTIICA0) when the received address matches the address value set in slave address register 0 (SVA0) or when an extension code is received.
  • Page 511 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (10) Data hold time correction circuit This circuit generates the hold time for data after the falling edge of the serial clock. (11) Start condition generator This circuit generates a start condition when the STT0 bit is set to 1.

  • Page 512: Registers Controlling Serial Interface Iica

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.3 Registers Controlling Serial Interface IICA Serial interface IICA is controlled by the following registers. ● Peripheral enable register 0 (PER0) ● IICA control register 00 (IICCTL00) ● IICA flag register 0 (IICF0) ●...

  • Page 513: Peripheral Enable Register 0 (Per0)

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.3.1 Peripheral enable register 0 (PER0) The PER0 register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise.

  • Page 514: Iica Control Register 00 (Iicctl00)

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.3.2 IICA control register 00 (IICCTL00) This register is used to enable or stop I C operations, set the timing of clock stretching, and set other I C operations. The IICCTL00 register can be set by a 1-bit or 8-bit memory manipulation instruction. Note that the SPIE0, WTIM0, and ACKE0 bits must be set while the setting of IICE0 is 0 or during the clock stretch period.
  • Page 515 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (2/4) WREL0 Release clock stretching Note 2, Note 3 Clock stretching is not released. Clock stretching is released. This bit is automatically cleared to 0 after clock stretching has been released.
  • Page 516 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (3/4) ACKE0 Acknowledgment control Note 4, Note 5 Disables acknowledgment. Enables acknowledgment. During the 9th clock period, the SDAA0 line is set to low level.
  • Page 517 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (4/4) Note 7 SPT0 Stop condition trigger A stop condition is not generated. A stop condition is generated (termination of transfer as a master). Cautions concerning set timing ●...

  • Page 518: Iica Status Register 0 (Iics0)

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.3.3 IICA status register 0 (IICS0) This register indicates the state of the I The IICS0 register can only be read by a 1-bit or 8-bit memory manipulation instruction while the setting of STT0 is 1 or during the clock stretch period.
  • Page 519 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-7. Format of IICA Status Register 0 (IICS0) (2/3) EXC0 Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXC0 = 0) Condition for setting (EXC0 = 1) ●...
  • Page 520 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-7. Format of IICA Status Register 0 (IICS0) (3/3) ACKD0 Acknowledge (ACK) detection Acknowledge was not detected. Acknowledge was detected. Condition for clearing (ACKD0 = 0) Condition for setting (ACKD0 = 1) ●...

  • Page 521: Iica Flag Register 0 (Iicf0)

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.3.4 IICA flag register 0 (IICF0) This register sets the operation mode of I C and indicates the state of the I C bus. The IICF0 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STT0 clear flag (STCF0) and I C bus status flag (IICBSY0) bits are read-only.
  • Page 522 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-8. Format of IICA Flag Register 0 (IICF0) (2/2) IICRSV0 Communication reservation function disable bit Enable communication reservation. Disable communication reservation. Condition for clearing (IICRSV0 = 0) Condition for setting (IICRSV0 = 1) ●...

  • Page 523: Iica Control Register 01 (Iicctl01)

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.3.5 IICA control register 01 (IICCTL01) This register is used to set the operation mode of I C and detect the states of the SCLA0 and SDAA0 pins. The IICCTL01 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read-only.
  • Page 524 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-9. Format of IICA Control Register 01 (IICCTL01) (2/2) CLD0 SCLA0 pin level detection (valid only when IICE0 = 1) The SCLA0 pin was detected to be at the low level. The SCLA0 pin was detected to be at the high level.
  • Page 525 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Caution When setting the transfer clock, take care with the minimum operation frequency of f . The minimum operation frequency of f for serial interface IICA is determined according to the mode. Normal mode: f = 1 MHz (min.)

  • Page 526: Iica Low-Level Width Setting Register 0 (Iicwl0)

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.3.6 IICA low-level width setting register 0 (IICWL0) This register is used to set the low-level width (tLOW) of the SCLA0 pin signal that is output by serial interface IICA and to control the SDAA0 pin signal.

  • Page 527: Registers Controlling Port Functions Of Iica Serial Input/Output Pins

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.3.8 Registers controlling port functions of IICA serial input/output pins When the IICA is to be used, set the registers that control the port functions multiplexed on the IICA serial I/O pins (SCLA0 and SDAA0 pins): port mode register (PM0), port register (P0), port output mode register (POM0), and port mode control register (PMC0).

  • Page 528: I 2 C Bus Mode Functions

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.4 C Bus Mode Functions 13.4.1 Pin configuration The serial clock pin (SCLA0) and the serial data bus pin (SDAA0) are configured as follows. (1) SCLA0 This pin is used for serial clock input and output.

  • Page 529: Setting Transfer Clock By Using Iicwl0 And Iicwh0 Registers

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers (1) Setting transfer clock on master side Transfer clock = IICWL + IICWH + f At this time, the optimal setting values of the IICWL0 and IICWH0 registers are as follows.
  • Page 530 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (2) Setting IICWL0 and IICWH0 registers on slave side (The fractional parts of all setting values are rounded up.) ● In fast mode IICWL0 = 1.3 μs × f IICWH0 = ( 1.2 μs − t ) ×...

  • Page 531: I 2 C Bus Definitions And Control Methods

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.5 C Bus Definitions and Control Methods The following describes the serial data communication format of the I C bus and the signals to be used. Figure 13-13 shows the timing of transfer of the “start condition”, “address”, “data”, and “stop condition” which are generated on the serial data bus of the I C bus.

  • Page 532: Start Condition

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.5.1 Start condition A start condition is generated when the SDAA0 pin changes from the high to the low level while the SCLA0 pin is at the high level. A start condition is a signal that the master generates to the slave when starting a serial transfer. When the device is used as a slave, a start condition can be detected.

  • Page 533: Address

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.5.2 Address 7-bit data that follows a start condition is defined as address. An address is a 7-bit data segment that is output in order for the master to select a certain slave from among multiple slaves connected to the bus line.

  • Page 534: Transfer Direction Specification

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.5.3 Transfer direction specification Following the 7-bit address, the master sends 1-bit data to specify the transfer direction. When this transfer direction specification bit is 0, it indicates that the master is transmitting data to a slave. When the transfer direction specification bit is 1, it indicates that the master is receiving data from a slave.
  • Page 535 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA When the master does not require the next data item during reception (TRC0 = 0), it must clear the ACKE0 bit to 0 so that ACK is not generated. In this way, the master informs the slave (transmission side) of the end of data (transmission will be stopped).

  • Page 536: Stop Condition

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.5.5 Stop condition A stop condition is generated when the SDAA0 pin changes from the low to the high level while the SCLA0 pin is at the high level. A stop condition is a signal that the master generates to the slave when serial transfer has been completed. A stop condition can be detected when the device is used as a slave.

  • Page 537: Clock Stretching

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.5.6 Clock stretching Clock stretching is used to notify the other party in communications that a master or slave is preparing to transmit or receive data (i.e., in the clock stretch state). By setting the SCLA0 pin to the low level, the other party is notified of the clock stretch state. When both the master and slave are released from the clock stretch state, the next data transfer can be started.
  • Page 538 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-19. Clock Stretching (2/2)  (2) When clock stretching occurs at the falling edge of the 9th clock for both master and slave (master: transmission, slave: reception, and ACKE0 = 1) The clock is stretched after the 9th...

  • Page 539: Releasing Clock Stretching

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.5.7 Releasing clock stretching The I C interface usually releases clock stretching by the following processing. ● Writing data to IICA shift register 0 (IICA0) ● Setting bit 5 (WREL0) of IICA control register 00 (IICCTL00) (releasing clock stretching) ●...

  • Page 540: Interrupt Request (Intiica0) Generation Timing And Clock Stretching Control

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.5.8 Interrupt request (INTIICA0) generation timing and clock stretching control The setting of bit 3 (WTIM0) of IICA control register 00 (IICCTL00) generates INTIICA0 and controls clock stretching at the timing shown in Table 13-2.

  • Page 541: Address Match Detection Method

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (4) Releasing clock stretching There are four methods for releasing clock stretching as follows. ● Writing data to the IICA shift register 0 (IICA0) ● Setting bit 5 (WREL0) of IICA control register 00 (IICCTL00) (releasing clock stretching) ●...

  • Page 542: 13.5.11 Extension Code

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.5.11 Extension code When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag (EXC0) is set to 1 for extension code reception and an interrupt request (INTIICA0) is generated at the falling edge of the 8th clock.

  • Page 543: 13.5.12 Arbitration

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.5.12 Arbitration When several masters simultaneously generate a start condition (when the STT0 bit is set to 1 before the STD0 bit is set to 1), master communication is performed while adjusting the clock cycles until the data differs. This kind of operation is called arbitration.
  • Page 544 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Table 13-4. State when Arbitration Occurred and Interrupt Request Generation Timing State when Arbitration Occurred Interrupt Request Generation Timing Note 1 During address transmission Falling edge of 8th or 9th clock following byte transfer...

  • Page 545: 13.5.13 Wakeup Function

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.5.13 Wakeup function This is a slave function of I C to generate an interrupt request signal (INTIICA0) when the local address and an extension code are received. When the addresses do not match, an unnecessary INTIICA0 signal is not generated to allow efficient processing.
  • Page 546 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-22. Flow when Setting WUP0 = 0 upon Address Match (Including Extension Code Reception) In STOP mode INTIICA0 = 1? WUP0 = 0 Wait Wait for 5 clock cycles of f Read IICS0...
  • Page 547 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-23. When Operating as Master after Release from STOP Mode by Interrupt Other than INTIICA0 S TA R T START SPIE0 = 1 WUP0 = 1 Wait Wait for 3 clock cycles of f...

  • Page 548: 13.5.14 Communication Reservation

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.5.14 Communication reservation (1) When communication reservation is enabled (bit 0 (IICRSV0) of IICA flag register 0 (IICF0) = 0) To proceed with master communications next while not currently participating in the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released.
  • Page 549 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-24 shows the communication reservation timing. Figure 13-24. Communication Reservation Timing Write to Program processing STT0 = 1 IICA0 Set SPD0 Communi- Hardware processing cation STD0 reservation INTIICA0 SCLA0 SDAA0 Generated by the master...
  • Page 550 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-26 shows the procedure for communication reservation. Figure 13-26. Communication Reservation Procedure Set the STT0 flag (communication reservation) SET1 STT0 Define that communication reservation is Define communication in effect (define and set the user flag in...
  • Page 551 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (2) When communication reservation is disabled (bit 0 (IICRSV0) of IICA flag register 0 (IICF0) = 1) When bit 1 (STT0) of IICA control register 00 (IICCTL00) is set to 1 while the bus is not participating in this communication during communication, this request is rejected and a start condition is not generated.

  • Page 552: 13.5.15 Cautions

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.5.15 Cautions When STCEN0 = 0 Immediately after I C operation is enabled (IICE0 = 1), the bus communication state (IICBSY0 = 1) is recognized regardless of the actual bus state. When performing master communication from the state where a stop condition is not detected, first generate a stop condition to release the bus, then perform master communication.
  • Page 553 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA When transmission is reserved, set the SPIE0 bit (bit 4 of the IICCTL00 register) to 1 so that an interrupt request is generated when a stop condition is detected. Transfer is started when communication data is written to IICA shift register 0 (IICA0) after the interrupt request has been generated.

  • Page 554: 13.5.16 Communication Operations

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.5.16 Communication operations The following describes three operation procedures as flows. 1) Master operation in single master system The flow when the device is used as a master in the single master system is described.
  • Page 555 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (1) Master operation in single master system Figure 13-27. Master Operation in Single Master System START Release serial interface IICA0 from the reset state and Set the PER0 register start clock supply. Note 1...
  • Page 556 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Note 1. Release the I C bus (SCLA0 and SDAA0 pins = high level) in conformance with the specifications of the product that is communicating. If EEPROM is outputting a low level to the SDAA0 pin, set the SCLA0 pin to the output port, and output a clock pulse from the output port until the SDAA0 pin is constantly at the high level.
  • Page 557 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (2) Master operation in multi-master system Figure 13-28. Master operation in Multi-master System (1/3) START Release serial interface IICA0 from the reset state Set the PER0 register and start clock supply. Setting of the port multiplexed with the pin to be used...
  • Page 558 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-28. Master Operation in Multi-master System (2/3) Enable communication reservation Prepare for starting communication STT0 = 1 (generate a start condition) Note 1 Secure the wait time by software Wait MSTS0 = 1?
  • Page 559 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-28. Master Operation in Multi-master System (3/3) Start communication Write to IICA0 (specify the address and transfer direction) INTIICA0 interrupt occurred? Wait for detection of ACK MSTS0 = 1? ACKE0 = 1 WTIM0 = 0...
  • Page 560 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (3) Slave operation The processing procedure of slave operation is as follows. Basically, slave operation is event-driven. This requires processing by the INTIICA0 interrupt (processing that requires substantially changing the operation state such as detection of a stop condition during communication).
  • Page 561 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Next, the main processing of slave operation is explained. Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed in response to an interrupt.
  • Page 562 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-29. Slave Operation Procedure (1) START Release serial interface IICA0 from the reset state and start Set the PER0 register clock supply. Setting of the port multiplexed with the pin to be used...
  • Page 563 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA An example of the processing procedure of the slave with the INTIICA0 interrupt is explained below (processing is performed assuming that no extension code is used). The INTIICA0 interrupt checks the status, and the following operations are performed.

  • Page 564: C Interrupt Request (Intiica0) Generation Timing

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.5.17 I C interrupt request (INTIICA0) generation timing The timing of data transmission/reception and generation of interrupt request signal INTIICA0 and the value of IICA status register 0 (IICS0) with the INTIICA0 signal timing are shown below.
  • Page 565 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (1) Master operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6-AD0 D7-D0 D7-D0 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B 3: IICS0 = 1000×000B (Sets the WTIM0 bit to 1)
  • Page 566 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIM0 = 0 STT0 = 1 SPT0 = 1 ↓ ↓ AD6-AD0 D7-D0 AD6-AD0 D7-D0 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1...
  • Page 567 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6-AD0 D7-D0 D7-D0 1: IICS0 = 1010x110B 2: IICS0 = 1010x000B 3: IICS0 = 1010x000B (Sets the WTIM0 bit to 1 Note 1 4: IICS0 = 1010xx00B (Sets the SPT0 bit to 1)
  • Page 568 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (2) Slave operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 AD6-AD0 D7-D0 D7-D0 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B 3: IICS0 = 0001×000B 4: IICS0 = 00000001B...
  • Page 569 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (a match with SVA0 after restart) AD6-AD0 D7-D0 AD6-AD0 D7-D0 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B 3: IICS0 = 0001×110B...
  • Page 570 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (an address mismatch after restart (extension code)) AD6-AD0 D7-D0 AD6-AD0 D7-D0 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B...
  • Page 571 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (an address mismatch after restart (other than extension code)) AD6-AD0 D7-D0 AD6-AD0 D7-D0 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B...
  • Page 572 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (3) Slave operation (when receiving extension code) The device always participates in communications when it receives an extension code. (a) Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIM0 = 0...
  • Page 573 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (a match with SVA0 after restart) AD6-AD0 D7-D0 AD6-AD0 D7-D0 1: IICS0 = 0010×010B 2: IICS0 = 0010×000B 3: IICS0 = 0001×110B...
  • Page 574 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (extension code reception after restart) AD6-AD0 D7-D0 AD6-AD0 D7-D0 1: IICS0 = 0010×010B 2: IICS0 = 0010×000B 3: IICS0 = 0010×010B...
  • Page 575 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (an address mismatch after restart (other than extension code)) AD6-AD0 D7-D0 AD6-AD0 D7-D0 1: IICS0 = 0010×010B 2: IICS0 = 0010×000B...
  • Page 576 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (5) Arbitration loss operation (operation as slave after arbitration loss) To use the device as a master in the multi-master system, read the MSTS0 bit to check the arbitration result each time interrupt request signal INTIICA0 is generated.
  • Page 577 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (b) When lost in arbitration during transmission of extension code (i) When WTIM0 = 0 AD6-AD0 D7-D0 D7-D0 1: IICS0 = 0110×010B 2: IICS0 = 0010×000B 3: IICS0 = 0010×000B 4: IICS0 = 00000001B : Always generated...
  • Page 578 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (6) Arbitration loss operation (not participating in communications after arbitration loss) When the device is used as a master in the multi-master system, read the MSTS0 bit to check the arbitration result each time interrupt request signal INTIICA0 is generated.
  • Page 579 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (c) When lost in arbitration during data transfer (i) When WTIM0 = 0 AD6-AD0 D7-D0 D7-D0 1: IICS0 = 10001110B 2: IICS0 = 01000000B 3: IICS0 = 00000001B : Always generated Remark : Generated only when SPIE0 = 1...
  • Page 580 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (d) When lost in the restart condition during data transfer (i) Other than extension code (e.g., a mismatch with SVA0) AD6-AD0 D7-Dn AD6-AD0 D7-D0 1: IICS0 = 1000×110B 2: IICS0 = 01000110B 3: IICS0 = 00000001B : Always generated...
  • Page 581 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (e) When lost in the stop condition during data transfer AD6-AD0 D7-Dn 1: IICS0 = 10000110B 2: IICS0 = 01000001B : Always generated Remark : Generated only when SPIE0 = 1 n = 6 to 0 R01UH0959EJ0110 Rev.1.10...
  • Page 582 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA When lost in arbitration due to the data being at the low level when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ AD6-AD0 D7-D0 D7-D0 D7-D0 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1)
  • Page 583 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (g) When lost in arbitration at the stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ AD6-AD0 D7-D0 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1) 3: IICS0 = 1000××00B (Sets the STT0 bit to 1)
  • Page 584 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA (h) When lost in arbitration due to the data being at the low level when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6-AD0 D7-D0 D7-D0 D7-D0 1: IICS0 = 1000×110B...

  • Page 585: Timing Charts

    RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA 13.6 Timing Charts In the I C bus mode, the master outputs an address on the serial bus to select a target slave device from among several slave devices. The master transmits the TRC0 bit (bit 3 of IICA status register 0 (IICS0)) that indicates the data transfer direction following the slave address and starts serial communication with the slave.
  • Page 586 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-31. Example of Master to Slave Communications (9th Cycle Clock Stretching is Selected for Both Master and Slave) (1/4) (1) Start condition ~ address ~ data Master side Note 1 IICA0 <5> <2>...
  • Page 587 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Note 2. Make sure that the time between the fall of the SDAA0 pin signal and the fall of the SCLA0 pin signal is at least 4.0 μs when standard mode is set and at least 0.6 μs when fast mode is set.
  • Page 588 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-31. Example of Master to Slave Communications (9th Cycle Clock Stretching is Selected for Both Master and Slave) (2/4) (2) Address ~ data ~ data Master side Note 1 Note 1 IICA0 <5>...
  • Page 589 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Note 2. To release clock stretching in reception by the slave, write FFH to IICA0 or set the WREL0 bit. Explanation of <3> to <10> in Figure 13-31 (2) Address ~ data ~ data is given below.
  • Page 590 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-31. Example of Master to Slave Communications (9th Cycle Clock Stretching is Selected for Both Master and Slave) (3/4) (3) Data ~ data ~ stop condition Master side Note 1 IICA0 <9> ACKD0...
  • Page 591 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Note 2. Make sure that the time between the rise of the SCLA0 pin signal and the generation of the stop condition after a stop condition has been issued is at least 4.0 μs when standard mode is set and at least 0.6 μs when fast mode is set.
  • Page 592 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-31. Example of Master to Slave Communications (9th Cycle Clock Stretching is Selected for Both Master and Slave) (4/4) (4) Data ~ restart condition ~ address Master side IICA0 <iii> ACKD0 (ACK detection) WTIM0 ...
  • Page 593 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Note 2. To release clock stretching in reception by the slave, write FFH to IICA0 or set the WREL0 bit. The following describes the operations in Figure 13-31 (4) Data ~ restart condition ~ address. After the operations of steps <7>...
  • Page 594 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32. Example of Slave to Master Communications (8th Cycle Clock Stretching is Selected for Master, 9th Cycle Clock Stretching is Selected for Slave) (1/3) (1) Start condition ~ address ~ data Master side IICA0 <2>...
  • Page 595 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Note 3. To release clock stretching in transmission by the slave, write data to the IICA0 register instead of setting the WREL0 bit. Explanation of <1> to <7> in Figure 13-32 (1) Start condition ~ address ~ data is given below.
  • Page 596 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32. Example of Slave to Master Communications (8th Cycle Clock Stretching is Selected for Master, 9th Cycle Clock Stretching is Selected for Slave) (2/3) (2) Address ~ data ~ data Master side IICA0...
  • Page 597 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Note 2. To release clock stretching in transmission by the slave, write data to the IICA0 register instead of setting the WREL0 bit. Explanation of <3> to <12> in Figure 13-32 (2) Address ~ data ~ data is given below.
  • Page 598 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32. Example of Slave to Master Communications (8th Cycle Clock Stretching is Changed to 9th Cycle Clock Stretching for Master, 9th Cycle Clock Stretching is Selected for Slave) (3/3) (3) Data ~ data ~ stop condition...
  • Page 599 RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA Note 2. Make sure that the time between the rise of the SCLA0 pin signal and the generation of the stop condition after a stop condition has been issued is at least 4.0 μs when standard mode is set and at least 0.6 μs when fast mode is set.

  • Page 600: Chapter 14 Interrupt Functions

    RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS CHAPTER 14 INTERRUPT FUNCTIONS The interrupt function switches the program execution to other processing. When the branch processing is finished, the program returns to the interrupted processing. The number of interrupt sources differs depending on the product.
  • Page 601 RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS Table 14-1. Interrupt Source List (1/2) Interrupt Source Name Trigger INTWDTI Watchdog timer interval Internal 00004H     (75% of the overflow time + 3/(4 × f INTP0 Pin input edge detection External 00006H ...
  • Page 602 RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS Table 14-1. Interrupt Source List (2/2) Interrupt Source Name Trigger — Execution of BRK instruction — 0007EH     ¯¯¯¯¯¯ pin input — RESET RESET — 00000H —     SPOR Selectable power-on-reset ...
  • Page 603 RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus ISP1 ISP0 Vector table address Priority controller generator Interrupt request Standby release signal (B) External maskable interrupt (INTPn) Internal bus External interrupt edge enable...
  • Page 604 RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Basic Configuration of Interrupt Function (2/2) (C) Software interrupt Internal bus Vector table address Interrupt request generator Interrupt request flag Interrupt enable flag ISP0: In-service priority flag 0 ISP1: In-service priority flag 1...

  • Page 605: Registers Controlling Interrupt Functions

    RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS 14.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H)  Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) ...
  • Page 606 RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS Table 14-2. Flags Corresponding to Interrupt Request Sources (2/2) Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Register Register Register INTTM03H TMIF03H IF1L TMMK03H MK1L TMPR003H, TMPR103H PR01L,    ...

  • Page 607: Interrupt Request Flag Registers (If0L, If0H, If1L, If1H)

    RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS 14.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation.
  • Page 608 RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS Caution 2. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (CLR1). When describing in C language, use a bit manipulation instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L.0”);” because the compiled assembler must be a 1-bit memory manipulation instruction (CLR1).

  • Page 609: Interrupt Mask Flag Registers (Mk0L, Mk0H, Mk1L, Mk1H)

    RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS 14.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt. The MK0L, MK0H, MK1L, and MK1H registers can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 610: Priority Specification Flag Registers (Pr00L, Pr00H, Pr01L, Pr01H, Pr10L, Pr10H, Pr11L, Pr11H)

    RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS 14.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR10L, PR10H, PR11L, PR11H) The priority specification flag registers are used to set the corresponding maskable interrupt priority level. A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H).
  • Page 611 RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS Address: FFFEEH After reset: FFH □ □ □ □ □ □ □ □ Symbol PR11L TMPR106 TMPR105 TMPR104 ITPR1 TMPR103 TMPR102 IICAPR10 TMPR103H Address: FFFEBH After reset: FFH □ □ □ Symbol PR01H CMPPR01 CMPPR00...

  • Page 612: External Interrupt Rising Edge Enable Register (Egp0), External Interrupt Falling Edge Enable Register (Egn0)

    RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS 14.3.4 External interrupt rising edge enable register (EGP0), external interrupt falling edge enable register (EGN0) These registers specify the valid edge for INTP0 to INTP7. The EGP0 and EGN0 registers can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 613: Program Status Word (Psw)

    RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS 14.3.5 Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that control multiple interrupt servicing are mapped to the PSW.

  • Page 614: Interrupt Servicing Operations

    RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS 14.4 Interrupt Servicing Operations 14.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
  • Page 615 RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-7. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending (xxPR1, xxPR0) No (low priority) ≤ (ISP1, ISP0) Interrupt request Yes (high priority)
  • Page 616 RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks Instruc- PSW and PC saved, Interrupt servicing Instruction Instruction processing tion jump to interrupt servicing program xxIF 9 clocks Remark 1 clock: 1/f : CPU clock) Figure 14-9.

  • Page 617: Software Interrupt Request Acknowledgment

    RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS 14.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH, 0007FH) are loaded into the PC and branched.
  • Page 618 RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS Table 14-5. Relationship between Interrupt Requests Enabled for Multiple Interrupt Servicing during Interrupt Servicing Multiple Interrupt Request Maskable Interrupt Request Software Interrupt Priority Level 0 Priority Level 1 Priority Level 2 Priority Level 3 Request...
  • Page 619 RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx processing INTyy processing INTzz processing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz...
  • Page 620 RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS Example 2. Multiple interrupt servicing does not occur due to priority control Main processing INTxx processing INTyy processing IE = 0 INTxx INTyy (PR = 10) (PR = 11) RETI IE = 1 1 instruction...
  • Page 621 RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx processing INTyy processing IE = 0 INTyy (PR = 00) INTxx...

  • Page 622: Interrupt Request Pending

    RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS 14.4.4 Interrupt request pending There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (instructions that hold interrupt requests pending) are listed below.
  • Page 623 RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-11 shows the timing at which interrupt requests are held pending. Figure 14-11. Interrupt Request Pending PSW and PC saved, Interrupt servicing Instruction N Instruction M processing jump to interrupt servicing program xxIF Remark...

  • Page 624: Chapter 15 Standby Function

    RL78/G15 CHAPTER 15 STANDBY FUNCTION CHAPTER 15 STANDBY FUNCTION 15.1 Overview The standby function reduces the operating current of the system, and the following two modes are available. 1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high- speed system clock oscillator or high-speed on-chip oscillator is operating before the HALT mode is set, oscillation of each clock continues.

  • Page 625: Registers Controlling Standby Function

    RL78/G15 CHAPTER 15 STANDBY FUNCTION 15.2 Registers controlling standby function The standby function is controlled by the following registers. For details of each register, see CHAPTER 5 CLOCK GENERATOR. Register which enables or stops the operation of the low-speed on-chip oscillator in the HALT or STOP mode.
  • Page 626 RL78/G15 CHAPTER 15 STANDBY FUNCTION Table 15-1. Operating Status in HALT Mode HALT Mode Setting When HALT Instruction is Executed While CPU is Operating on Main System Clock When CPU is Operating on When CPU is Operating on When CPU is Operating on...
  • Page 627 RL78/G15 CHAPTER 15 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
  • Page 628 RL78/G15 CHAPTER 15 STANDBY FUNCTION b) HALT mode release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.

  • Page 629: Stop Mode

    RL78/G15 CHAPTER 15 STANDBY FUNCTION 15.3.2 STOP mode (1) STOP mode setting and operating status The STOP mode is set by executing the STOP instruction. Caution Because the interrupt request signal is used to clear the STOP mode, if the interrupt mask flag is 0...
  • Page 630 RL78/G15 CHAPTER 15 STANDBY FUNCTION Table 15-2. Operating Status in STOP Mode (2/2) STOP Mode Setting When STOP Instruction is Executed While CPU is Operating When CPU is Operating on When CPU is Operating on When CPU is Operating on...
  • Page 631 RL78/G15 CHAPTER 15 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released by the following two sources. a) STOP mode release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
  • Page 632 RL78/G15 CHAPTER 15 STANDBY FUNCTION Figure 15-3. STOP Mode Release by Interrupt Request Generation (2/3) (2) When high-speed system clock (X1 oscillation) is used as CPU clock (16-pin and 20-pin products only) Interrupt request STOP instruction Standby release Note 1...
  • Page 633 RL78/G15 CHAPTER 15 STANDBY FUNCTION Figure 15-3. STOP Mode Release by Interrupt Request Generation (3/3) (3) When high-speed system clock (external clock input) is used as CPU clock (16-pin and 20-pin products only) Interrupt request STOP instruction Standby release Note 1...
  • Page 634 RL78/G15 CHAPTER 15 STANDBY FUNCTION b) STOP mode release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.

  • Page 635: Chapter 16 Reset Function

    RL78/G15 CHAPTER 16 RESET FUNCTION CHAPTER 16 RESET FUNCTION The following six operations are available to generate a reset signal. ¯¯¯¯¯¯ pin External reset input via RESET Internal reset by watchdog timer program loop detection Internal reset by comparison of supply voltage and detection voltage of selectable power-on-reset (SPOR) circuit...
  • Page 636 RL78/G15 CHAPTER 16 RESET FUNCTION R01UH0959EJ0110 Rev.1.10 Page 636 of 765 Mar 7, 2023...

  • Page 637: Timing Of Reset Operation

    RL78/G15 CHAPTER 16 RESET FUNCTION 16.1 Timing of Reset Operation ¯¯¯¯¯¯ pin and released from the reset state by input of the high level This LSI is reset by input of the low level on the RESET ¯¯¯¯¯¯ pin. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the on the RESET operating clock starts.
  • Page 638 RL78/G15 CHAPTER 16 RESET FUNCTION Release from the reset state is automatic in the case of a reset due to a watchdog timer overflow, execution of an illegal instruction, or detection of illegal memory access. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the operating clock starts.

  • Page 639: States Of Operation During Reset Periods

    RL78/G15 CHAPTER 16 RESET FUNCTION 16.2 States of Operation During Reset Periods Table 16-1 shows the states of operation during reset periods. Table 16-2 shows the state of the hardware after acceptance of a reset. Table 16-1. States of Operation During Reset Period...
  • Page 640 RL78/G15 CHAPTER 16 RESET FUNCTION Table 16-2. State of Hardware After Receiving a Reset Signal Hardware After Reset Acknowledgment Note 1 Program counter (PC) The contents of the reset vector table (00000H, 00001H) are set. Stack pointer (SP) Undefined Program status word (PSW)

  • Page 641: Register For Confirming Reset Source

    RL78/G15 CHAPTER 16 RESET FUNCTION 16.3 Register for Confirming Reset Source 16.3.1 Reset Control Flag Register (RESF) Many internal reset generation sources exist in the RL78 microcontroller. The reset control flag register (RESF) is used to store which source has generated the reset request.
  • Page 642 RL78/G15 CHAPTER 16 RESET FUNCTION The status of the RESF register when a reset request is generated is shown in Table 16-3. Table 16-3. RESF Register Status When Reset Request Is Generated ¯¯¯¯¯¯ Input Reset Source RESET Reset by Reset by WDT...
  • Page 643 RL78/G15 CHAPTER 16 RESET FUNCTION The RESF register is automatically cleared when it is read by an 8-bit memory manipulation instruction. Figure 16-5 shows the procedure for checking a reset source. Figure 16-5. Example of Procedure for Checking Reset Source After reset acceptance ...

  • Page 644: Chapter 17 Selectable Power-On-Reset Circuit

    RL78/G15 CHAPTER 17 SELECTABLE POWER-ON-RESET CIRCUIT CHAPTER 17 SELECTABLE POWER-ON-RESET CIRCUIT 17.1 Functions of Selectable Power-on-reset Circuit The selectable power-on-reset (SPOR) circuit has the following functions. ● Generates internal reset signal at power on. The reset signal is released when the supply voltage (V...

  • Page 645: Configuration Of Selectable Power-On-Reset Circuit

    RL78/G15 CHAPTER 17 SELECTABLE POWER-ON-RESET CIRCUIT 17.2 Configuration of Selectable Power-on-reset Circuit The block diagram of the selectable power-on-reset circuit is shown in Figure 17-1. Figure 17-1. Block Diagram of Selectable Power-on-reset Circuit Voltage – Internal reset signal detection level...

  • Page 646: Operation Of Selectable Power-On-Reset Circuit

    RL78/G15 CHAPTER 17 SELECTABLE POWER-ON-RESET CIRCUIT 17.3 Operation of Selectable Power-on-reset Circuit Specify the voltage detection level by using the option byte 000C1H. The internal reset signal is generated at power on. The internal reset status is retained until the supply voltage (V ) exceeds the voltage detection level (V ).

  • Page 647: Cautions For Selectable Power-On-Reset Circuit

    RL78/G15 CHAPTER 17 SELECTABLE POWER-ON-RESET CIRCUIT 17.4 Cautions for Selectable Power-on-reset Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the SPOR detection voltage ), the system may be repeatedly reset and released from the reset status. In this case, the time from...

  • Page 648: Chapter 18 Option Byte

    RL78/G15 CHAPTER 18 OPTION BYTE CHAPTER 18 OPTION BYTE 18.1 Functions of Option Bytes Addresses 000C0H to 000C3H of the flash memory form an option byte area. Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H).

  • Page 649: Format Of User Option Byte

    RL78/G15 CHAPTER 18 OPTION BYTE 18.2 Format of User Option Byte Figure 18-1. Format of User Option Byte (000C0H) Address: 000C0H WDTON WDCS2 WDCS1 WDCS0 WDSTBYON WDTON Operation control of watchdog timer counter Counter operation disabled (counting stopped after reset)
  • Page 650 RL78/G15 CHAPTER 18 OPTION BYTE Figure 18-2. Format of User Option Byte (000C1H) Address: 000C1H PORTSELB SPORS1 SPORS0 ● Setting of SPOR detection voltage Detection voltage (V Option byte setting value SPOR Rising edge Falling edge SPORS1 SPORS0 4.28 V 4.20 V...
  • Page 651 RL78/G15 CHAPTER 18 OPTION BYTE Figure 18-3. Format of User Option Byte (000C2H) Address: 000C2H FRQSEL2 FRQSEL1 FRQSEL0 FRQSEL2 FRQSEL1 FRQSEL0 Frequency of the high-speed on-chip oscillator Operating frequency (f Operating voltage range (V MAIN 16 MHz 2.4 V to 5.5 V...

  • Page 652: Format Of On-Chip Debug Option Byte

    RL78/G15 CHAPTER 18 OPTION BYTE 18.3 Format of On-chip Debug Option Byte The format of on-chip debug option byte is shown below. Figure 18-4. Format of On-chip Debug Option Byte (000C3H) Address: 000C3H OCDENSET OCDENSET Control of on-chip debug operation Disables on-chip debug operation.

  • Page 653: Setting Of Option Byte

    RL78/G15 CHAPTER 18 OPTION BYTE 18.4 Setting of Option Byte The user option byte and on-chip debug option byte can be set using the link option in addition to describing to the source. When doing so, the contents set by using the link option take precedence, even if descriptions exist in the source, as mentioned below.

  • Page 654: Chapter 19 Flash Memory

    RL78/G15 CHAPTER 19 FLASH MEMORY CHAPTER 19 FLASH MEMORY The RL78 microcontroller incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory includes the “code flash memory”, in which programs can be executed, and the “data flash memory”, an area for storing data.
  • Page 655 RL78/G15 CHAPTER 19 FLASH MEMORY The following methods for programming the flash memory are available. ● The code flash memory and data flash memory can be rewritten to through serial programming using a flash memory programmer or an external device (UART communication), or through self-programming.

  • Page 656: Serial Programming Using Flash Memory Programmer

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.1 Serial Programming Using Flash Memory Programmer The following dedicated flash memory programmer can be used to write data to the internal flash memory of the RL78 microcontroller.  PR5PG-FP6  E2 or E2 Lite on-chip debugging emulator Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer.
  • Page 657 RL78/G15 CHAPTER 19 FLASH MEMORY Table 19-2. Wiring between RL78/G15 and Dedicated Flash Memory Programmer Pin Configuration of Dedicated Flash Memory Programmer Pin Name Pin No. 8-pin 10-pin 16-pin 20-pin Signal Name Pin Function WDFN SSOP SSOP HWQFN SSOP PG-FP6...

  • Page 658: Programming Environment

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.1.1 Programming environment The environment required for writing a program to the flash memory of the RL78 microcontroller is illustrated below. Figure 19-1. Environment for Writing Program to Flash Memory E2, E2 Lite PG-FP6 RS-232C...
  • Page 659 RL78/G15 CHAPTER 19 FLASH MEMORY The dedicated flash memory programmer generates the following signals for the RL78 microcontroller. See the manual for the PG-FP6 or, E2 or E2 Lite on-chip debugging emulator for details. Table 19-3. Pin Connection Dedicated Flash Memory Programmer...

  • Page 660: Writing To Flash Memory By Using External Device (That Incorporates Uart)

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.2 Writing to Flash Memory by Using External Device (that Incorporates UART) On-board data writing to the internal flash memory is possible by using the RL78 microcontroller and an external device (a microcontroller or ASIC) connected to a UART.

  • Page 661: Communication Mode

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.2.2 Communication mode Communication between the external device and the RL78 microcontroller is established by serial communication using the TOOL0 pin via the dedicated UART of the RL78 microcontroller. Transfer rate: Fixed to 115200 bps Figure 19-4.

  • Page 662: Connection Of Pins On Board

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.3 Connection of Pins on Board To write the flash memory on-board by using the flash memory programmer, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.

  • Page 663: Reset ¯¯¯¯¯¯ Pin

    RL78/G15 CHAPTER 19 FLASH MEMORY ¯¯¯¯¯¯ pin 19.3.2 RESET Signal conflict will occur if the reset signal of the dedicated flash memory programmer and external device are connected ¯¯¯¯¯¯ pin that is connected to the reset signal generator on the board. To prevent this conflict, isolate the to the RESET connection with the reset signal generator.

  • Page 664: Power Supply

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.3.5 Power supply Note 1 To use the supply voltage output of the flash memory programmer, connect the V pin to V of the flash memory programmer, and the V pin to GND of the flash memory programmer.

  • Page 665: Serial Programming Method

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.4 Serial Programming Method 19.4.1 Serial programming procedure The following figure illustrates a flow for rewriting the code flash memory through serial programming. Figure 19-6. Code Flash Memory Manipulation Procedure Start Controlling TOOL0 pin and...

  • Page 666: Flash Memory Programming Mode

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.4.2 Flash memory programming mode To rewrite the contents of the code flash memory by serial programming, the flash memory programming mode must be entered. <Serial programming using the dedicated flash memory programmer> Connect the RL78 microcontroller to a dedicated flash memory programmer. Communication from the dedicated flash memory programmer is performed to automatically switch to the flash memory programming mode.

  • Page 667: Selecting Communication Mode

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.4.3 Selecting communication mode Communication modes of the RL78 microcontroller are as follows. Table 19-6. Communication Modes Note 1 Communication Mode Standard Setting Pins Used Note 2 Port Speed Frequency Multiply Rate 1-line UART UART 115200 bps —...

  • Page 668: Processing Time For Each Command When Pg-Fp5 Is In Use (Reference Values)

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.5 Processing Time for Each Command When PG-FP5 Is in Use (Reference Values) The following tables show the processing time for each command (reference value) when PG-FP5 is used as a dedicated flash memory programmer.

  • Page 669: Self-Programming

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.6 Self-Programming The RL78 microcontroller supports a self-programming function that can be used to rewrite the code flash memory via a user program. Because this function allows a user application to rewrite the code flash memory by using the flash self- programming library, it can be used to upgrade the program in the field.

  • Page 670: Flash Address Pointer Registers H And L (Flaph, Flapl)

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.6.1.1 Flash address pointer registers H and L (FLAPH, FLAPL) The FLAPH and FLAPL registers specify the address where programming of the flash memory is to start. The FLAPH and FLAPL registers can be set by an 8-bit memory manipulation instruction.

  • Page 671: Flash End Address Specification Registers H And L (Flsedh, Flsedl)

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.6.1.2 Flash end address specification registers H and L (FLSEDH, FLSEDL) The FLSEDH and FLSEDL registers specify the address where programming of the flash memory is to end. The FLSEDH and FLSEDL registers can be set by an 8-bit memory manipulation instruction.
  • Page 672 RL78/G15 CHAPTER 19 FLASH MEMORY Block configuration of code flash memory Bits 12 to 10 of block start address 01FFFH 01C00H (007) 01BFFH 01800H (006) 017FFH 01400H (005) 013FFH 01000H (004) 00FFFH 00C00H (003) 00BFFH 00800H (002) 007FFH 00400H (001)

  • Page 673: Flash Write Buffer Registers Hh, Hl, Lh, And Ll (Flwhh, Flwhl, Flwlh, Flwll)

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.6.1.3 Flash write buffer registers HH, HL, LH, and LL (FLWHH, FLWHL, FLWLH, FLWLL) The FLWHH, FLWHL, FLWLH, and FLWLL registers hold data to be written during programming of the flash memory. The FLWHH, FLWHL, FLWLH, and FLWLL registers can be set by an 8-bit memory manipulation instruction.

  • Page 674: Flash Programming Mode Control Register (Flpmc)

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.6.1.4 Flash programming mode control register (FLPMC) The FLPMC register sets the flash memory to the self-programming mode. The FLPMC register can be set by an 8-bit memory manipulation instruction. This register is set to 08H following a reset.

  • Page 675: Flash Memory Sequencer Initial Setting Register (Fsset)

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.6.1.5 Flash memory sequencer initial setting register (FSSET) The FSSET register sets the operating frequency of the flash memory sequencer. The FSSET register can be set by an 8-bit memory manipulation instruction. This register is set to 00H following a reset.

  • Page 676: Flash Memory Sequencer Control Register (Fssq)

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.6.1.6 Flash memory sequencer control register (FSSQ) The FSSQ register defines the commands to be used when the flash memory sequencer is activated. The FSSQ register can be set by an 8-bit memory manipulation instruction.

  • Page 677: Flash Memory Sequencer Status Registers H And L (Fsasth, Fsastl)

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.6.1.7 Flash memory sequencer status registers H and L (FSASTH, FSASTL) The FSASTH and FSASTL registers indicate the results of the operations of the flash memory sequencer. The FSASTH and FSASTL registers can be read by an 8-bit memory manipulation instruction.

  • Page 678: Procedure For Executing Self-Programming Of Code/Data Flash Memory

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.6.2 Procedure for executing self-programming of code/data flash memory The following figure illustrates a flow for rewriting the code/data flash memory by using the flash self-programming code. For details of the registers to be used for execution of self-programming, see 19.6.1 Registers controlling self- programming.
  • Page 679 RL78/G15 CHAPTER 19 FLASH MEMORY Figure 19-15. Flash Memory Self-Programming Execution Procedure Start FSSET register Set the frequency of the CPU/peripheral hardware clock (f ) in Initial setting for the operating frequency the FSET4-0 bits of the FSSET register. FLPMC register...
  • Page 680 RL78/G15 CHAPTER 19 FLASH MEMORY Figure 19-16. Flash Memory Sequencer Starting and Ending Processing FSSQ SQST FSSQ SQMDx FSASTH.SQEND FSASTL.**ER <1> <2> <3> <4> <5> <6> <1> Set up operation. <2> Set the SQST bit (the sequencer starts operating and the CPU enters the wait state).

  • Page 681: Notes On Self-Programming

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.6.3 Notes on self-programming Allocate the self-programming code for rewriting the code/data flash area to the code flash area. Self-programming by fetching from the RAM is prohibited. Additionally, rewriting the boot area and the block for storing the self- programming code is prohibited.

  • Page 682: Data Flash

    RL78/G15 CHAPTER 19 FLASH MEMORY 19.7 Data Flash 19.7.1 Data flash overview An overview of the data flash memory is provided below. ● The user program can rewrite the data flash memory by using the self-programming code. ● The data flash memory can also be rewritten to through serial programming using the dedicated flash memory programmer or an external device.

  • Page 683: Chapter 20 On-Chip Debug Function

    Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.
  • Page 684 RL78/G15 CHAPTER 20 ON-CHIP DEBUG FUNCTION ¯¯¯¯¯¯ pin, its connection to an external circuit should be For the target system which uses the multi-use feature of RESET isolated. Figure 20-2. Connection Example of E2, E2 Lite On-chip Debugging Emulator and RL78 microcontroller ¯¯¯¯¯¯...

  • Page 685: Connecting External Device (That Incorporates Uart)

    RL78/G15 CHAPTER 20 ON-CHIP DEBUG FUNCTION 20.2 Connecting External Device (that Incorporates UART) ¯¯¯¯¯¯ , TOOL0, V The V , RESET , TOOLTxD, and TOOLRxD pins are used to communicate with the host machine on board via the RL78 microcontroller and an external device (a microcontroller or ASIC) connected to a UART.

  • Page 686: On-Chip Debug Security Id

    RL78/G15 CHAPTER 20 ON-CHIP DEBUG FUNCTION 20.3 On-Chip Debug Security ID The RL78 microcontroller has an on-chip debug operation control bit in the flash memory at 000C3H (see CHAPTER 18 OPTION BYTE) and an on-chip debug security ID setting area at 000C4H to 000CDH, to prevent third parties from reading memory content.

  • Page 687: Securing Of User Resources

    To perform communication between the RL78 microcontroller and E2, E2 Lite on-chip debugging emulator, as well as each debug function, the securing of memory space must be done beforehand. If Renesas Electronics assembler or compiler is used, the items can be set by using link options.
  • Page 688 RL78/G15 CHAPTER 20 ON-CHIP DEBUG FUNCTION Note 4. Since this area is allocated immediately before the stack area, the address of this area varies depending on the stack increase and decrease. That is, 10 extra bytes are consumed for the stack area used.

  • Page 689: Chapter 21 Bcd Correction Circuit

    RL78/G15 CHAPTER 21 BCD CORRECTION CIRCUIT CHAPTER 21 BCD CORRECTION CIRCUIT 21.1 BCD Correction Circuit Function The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD code with this circuit. The decimal correction operation result is obtained by performing addition/subtraction having the A register as the operand and then adding/subtracting the BCD correction result register (BCDADJ).

  • Page 690: Bcd Correction Circuit Operation

    RL78/G15 CHAPTER 21 BCD CORRECTION CIRCUIT 21.3 BCD Correction Circuit Operation The basic operation of the BCD correction circuit is as follows. 1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a BCD code value <1>...
  • Page 691 RL78/G15 CHAPTER 21 BCD CORRECTION CIRCUIT 2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by using a BCD code value <1> The BCD code value from which subtraction is performed is stored in the A register.

  • Page 692: Chapter 22 Instruction Set

    RL78/G15 CHAPTER 22 INSTRUCTION SET CHAPTER 22 INSTRUCTION SET This chapter lists the instructions in the RL78 microcontroller instruction set. For details of each operation and operation code, refer to the separate document RL78 Family User’s Manual: Software (R01US0015E). 22.1 Conventions Used in Operation List 22.1.1...
  • Page 693 RL78/G15 CHAPTER 22 INSTRUCTION SET Table 22-1. Operand Identifiers and Specification Methods Identifier Description Method X(R0), A(R1), C(R2), B(R3), E(R4), D(R5), L(R6), H(R7) AX(RP0), BC(RP1), DE(RP2), HL(RP3) Special-function register symbols (SFR symbols) FFF00H to FFFFFH sfrp Special-function register symbols (16-bit manipulatable SFR symbols. Even addresses only...

  • Page 694: Description Of Operation Column

    RL78/G15 CHAPTER 22 INSTRUCTION SET 22.1.2 Description of operation column The operation when the instruction is executed is shown in the “Operation” column using the following symbols. Table 22-2. Symbols in “Operation” Column Symbol Function A register: 8-bit accumulator X register...

  • Page 695: Description Of Flag Operation Column

    RL78/G15 CHAPTER 22 INSTRUCTION SET 22.1.3 Description of flag operation column The change of the flag value when the instruction is executed is shown in the “Flag” column using the following symbols. Table 22-3. Symbols in “Flag” Column Symbol Change of Flag Value...

  • Page 696: Operation List

    RL78/G15 CHAPTER 22 INSTRUCTION SET 22.2 Operation List Table 22-5. Operation List (1/13) Instruction Mnemonic Operand Bytes Clock Operation Flag Group Note 1 Note 2 8-bit data r, #byte — r ← byte transfer PSW, #byte — PSW ← byte ×...
  • Page 697 RL78/G15 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (2/13) Instruction Mnemonic Operand Bytes Clock Operation Flag Group Note 1 Note 2 8-bit data [HL], A — (HL) ← A transfer A, ES:[HL] A ← (ES, HL) ES:[HL], A —...
  • Page 698 RL78/G15 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (3/13) Instruction Mnemonic Operand Bytes Clock Operation Flag Group Note 1 Note 2 8-bit data C, !addr16 C ← (addr16) transfer C, ES:!addr16 C ← (ES, addr16) C, saddr — C ← (saddr) ES, saddr —...
  • Page 699 RL78/G15 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (4/13) Instruction Mnemonic Operand Bytes Clock Operation Flag Group Note 1 Note 2 16-bit data MOVW rp, #word — rp ← word transfer saddrp, #word — (saddrp) ← word sfrp, #word —...
  • Page 700 RL78/G15 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (5/13) Instruction Mnemonic Operand Bytes Clock Operation Flag Group Note 1 Note 2 16-bit data MOVW BC, ES:!addr16 BC ← (ES, addr16) transfer DE, !addr16 DE ← (addr16) DE, ES:!addr16 DE ← (ES, addr16) HL, !addr16 HL ←...
  • Page 701 RL78/G15 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (6/13) Instruction Mnemonic Operand Bytes Clock Operation Flag Group Note 1 Note 2 8-bit A, #byte — A, CY ← A − byte × × × operation saddr, #byte — (saddr), CY ← (saddr) − byte ×...
  • Page 702 RL78/G15 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (7/13) Instruction Mnemonic Operand Bytes Clock Operation Flag Group Note 1 Note 2 8-bit A, [HL+C] A ← A ∧ (HL + C) × operation A, ES:[HL+C] A ← A ∧ ((ES:HL) + C) ×...
  • Page 703 RL78/G15 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (8/13) Instruction Mnemonic Operand Bytes Clock Operation Flag Group Note 1 Note 2 8-bit A, #byte — A − byte × × × operation !addr16, #byte (addr16) − byte × ×...
  • Page 704 RL78/G15 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (9/13) Instruction Mnemonic Operand Bytes Clock Operation Flag Group Note 1 Note 2 16-bit SUBW AX, #word — AX, CY ← AX − word × × × operation AX, BC —...
  • Page 705 RL78/G15 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (10/13) Instruction Mnemonic Operand Bytes Clock Operation Flag Group Note 1 Note 2 Shift A, cnt — (CY ← A ← A ← 0) × cnt × － SHRW AX, cnt —...
  • Page 706 RL78/G15 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (11/13) Instruction Mnemonic Operand Bytes Clock Operation Flag Group Note 1 Note 2 XOR1 CY, A.bit — CY ← CY ∀ A.bit × manipulate CY, PSW.bit — CY ← CY ∀ PSW.bit ×...
  • Page 707 RL78/G15 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (12/13) Instruction Mnemonic Operand Bytes Clock Operation Flag Group Note 1 Note 2 Call/return RETI — — ← (SP), PC ← (SP + 1), ← (SP + 2), PSW ← (SP + 3), SP ←...
  • Page 708 RL78/G15 CHAPTER 22 INSTRUCTION SET Table 22-5. Operation List (13/13) Instruction Mnemonic Operand Bytes Clock Operation Flag Group Note 1 Note 2 Conditional BTCLR saddr.bit, $addr20 Note 5 — PC ← PC + 4 + jdisp8 if (saddr).bit = 1 branch then reset (saddr).bit...

  • Page 709: Chapter 23 Electrical Specifications

    Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.

  • Page 710: Absolute Maximum Ratings

    = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T 23.1 Absolute Maximum Ratings = 25°C] Item Symbol Condition Rating Unit −0.5 to +6.5 Supply voltage −0.3 to V Note 1 Input voltage + 0.3 −0.3 to V Output voltage + 0.3...

  • Page 711: Oscillator Characteristics

    = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T 23.2 Oscillator Characteristics 23.2.1 X1 oscillator characteristics = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V] Item Resonator Condition MIN. TYP. MAX. Unit 2.4 V ≤ V ≤...

  • Page 712: Dc Characteristics

    = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T 23.3 DC Characteristics 23.3.1 Pin characteristics = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V] (1/2) Item Symbol Condition MIN. TYP. MAX. Unit −10.0...
  • Page 713 = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. = −40 to +85°C, 2.4 V ≤ V ≤...

  • Page 714: Supply Current Characteristics

    = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T 23.3.2 Supply current characteristics = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Note 4 Supply Operating...
  • Page 715 = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T Peripheral Functions = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Note 1 Low-speed on-chip oscillator operating 0.30...

  • Page 716: Ac Characteristics

    = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T 23.4 AC Characteristics = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit 2.4 V ≤ V ≤ 5.5 V...
  • Page 717 = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T Minimum Instruction Execution Time during Main System Clock Operation vs V  When the high-speed on-chip oscillator clock is selected  During self-programming  When the high-speed system clock is selected 0.05...
  • Page 718 = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T TI/TO Timing TI00 to TI07 TO00 to TO07 ¯¯¯¯¯¯ Input Timing RESET ______ RESET R01UH0959EJ0110 Rev.1.10 Page 718 of 765 Mar 7, 2023...

  • Page 719: Serial Interface Characteristics

    = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T 23.5 Serial Interface Characteristics AC Timing Test Points Test points 23.5.1 Serial array unit (1) UART mode = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V]...
  • Page 720 = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T (2) Simplified SPI (CSI) mode (master mode, SCKp... internal clock output) = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V] Item Symbol Condition MIN.
  • Page 721 = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T Remark 1. p: CSI number (p = 00, 01), n: Channel number (n = 0, 1) Remark 2. : Serial array unit operation clock frequency (Operation clock to be set by serial clock select register 0 (SPS0) and the CKS0n bit of serial mode register 0n (SMR0n).
  • Page 722 = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T (4) Simplified I C mode = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V] Item Symbol Condition MIN. MAX. Unit Note 1 SCLr clock frequency = 100 pF, R = 3 kΩ...
  • Page 723 = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T Simplified I C mode serial transfer timing HIGH SCLr SDAr HD:DAT SU:DAT Remark 1. [Ω]: Communication line (SDAr) pull-up resistance, C [F]: Communication line (SCLr, SDAr) load capacitance Remark 2.

  • Page 724: Serial Interface Iica

    = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T 23.5.2 Serial interface IICA = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V] Item Symbol Condition Standard Mode Fast Mode Unit MIN. MAX. MIN.

  • Page 725: Analog Characteristics

    = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T 23.6 Analog Characteristics 23.6.1 A/D converter characteristics Targets: ANI0 to ANI10, internal reference voltage = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V] Item...

  • Page 726: Comparator Characteristics

    = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T 23.6.2 Comparator characteristics = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit − 1.4 Input voltage range...

  • Page 727: Spor Circuit Characteristics

    = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T 23.6.4 SPOR circuit characteristics = −40 to +85°C, V = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Detection voltage Power supply Power supply rising 4.08 4.28 4.45 SPOR0...

  • Page 728: Ram Data Retention Characteristics

    = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T 23.7 RAM Data Retention Characteristics = −40 to +85°C, V = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Data retention power supply voltage DDDR Caution Data in RAM is retained until the power supply voltage falls below the MIN. value of the data retention power supply voltage (V ).

  • Page 729: Flash Memory Programming Characteristics

    1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics. Code flash/data flash self-programming time ...

  • Page 730: 23.10 Timing Of Entry To Flash Memory Programming Mode

    = −40 to +85°C) RL78/G15 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T 23.10 Timing of Entry to Flash Memory Programming Mode  = −40 to +85°C, 2.4 V ≤ V ≤ 5.5 V, V = 0 V] Item Symbol Condition MIN. TYP.

  • Page 731: Chapter 24 Electrical Specifications (T +125°C)

    Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.

  • Page 732: Absolute Maximum Ratings

    = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T 24.1 Absolute Maximum Ratings = 25°C] Item Symbol Condition Rating Unit −0.5 to +6.5 Supply voltage −0.3 to V Note 1 Input voltage + 0.3 −0.3 to V...

  • Page 733: Oscillator Characteristics

    = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T 24.2 Oscillator Characteristics 24.2.1 X1 oscillator characteristics = −40 to +105°C: G products, T = −40 to +125°C: M products, 2.4 V ≤ V ≤ 5.5 V, V...

  • Page 734: Dc Characteristics

    = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T 24.3 DC Characteristics 24.3.1 Pin characteristics = −40 to +105°C: G products, T = −40 to +125°C: M products, 2.4 V ≤ V ≤ 5.5 V, V...
  • Page 735 = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. = −40 to +105°C: G products, T = −40 to +125°C: M products, 2.4 V ≤...

  • Page 736: Supply Current Characteristics

    = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T 24.3.2 Supply current characteristics = −40 to +105°C: G products, T = −40 to +125°C: M products, 2.4 V ≤ V ≤ 5.5 V, V...
  • Page 737 = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T Peripheral Functions = −40 to +105°C: G products, T = −40 to +125°C: M products, 2.4 V ≤ V ≤ 5.5 V, V = 0 V]...

  • Page 738: Ac Characteristics

    = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T 24.4 AC Characteristics = −40 to +105°C: G products, T = −40 to +125°C: M products, 2.4 V ≤ V ≤ 5.5 V, V = 0 V]...
  • Page 739 = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T Minimum Instruction Execution Time during Main System Clock Operation vs V  When the high-speed on-chip oscillator clock is selected  During self-programming  When the high-speed system clock is selected 0.05...
  • Page 740 = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T TI/TO Timing TI00 to TI07 TO00 to TO07 ¯¯¯¯¯¯ Input Timing RESET ______ RESET R01UH0959EJ0110 Rev.1.10 Page 740 of 765 Mar 7, 2023...

  • Page 741: Serial Interface Characteristics

    = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T 24.5 Serial Interface Characteristics AC Timing Test Points Test points 24.5.1 Serial array unit (1) UART mode = −40 to +105°C: G products, T = −40 to +125°C: M products, 2.4 V ≤ V ≤...
  • Page 742 = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T (2) Simplified SPI (CSI) mode (master mode, SCKp... internal clock output) = −40 to +105°C: G products, T = −40 to +125°C: M products, 2.4 V ≤ V ≤...
  • Page 743 = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T Remark 1. p: CSI number (p = 00, 01), n: Channel number (n = 0, 1) Remark 2. : Serial array unit operation clock frequency (Operation clock to be set by serial clock select register 0 (SPS0) and the CKS0n bit of serial mode register 0n (SMR0n).
  • Page 744 = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T (4) Simplified I C mode = −40 to +105°C: G products, T = −40 to +125°C: M products, 2.4 V ≤ V ≤ 5.5 V, V...
  • Page 745 = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T Simplified I C mode serial transfer timing HIGH SCLr SDAr HD:DAT SU:DAT Remark 1. [Ω]: Communication line (SDAr) pull-up resistance, C [F]: Communication line (SCLr, SDAr) load capacitance Remark 2.

  • Page 746: Serial Interface Iica

    = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T 24.5.2 Serial interface IICA = −40 to +105°C: G products, T = −40 to +125°C: M products, 2.4 V ≤ V ≤ 5.5 V, V...

  • Page 747: Analog Characteristics

    = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T 24.6 Analog Characteristics 24.6.1 A/D converter characteristics Targets: ANI0 to ANI10, internal reference voltage = −40 to +105°C: G products, T = −40 to +125°C: M products, 2.4 V ≤ V ≤...

  • Page 748: Comparator Characteristics

    = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T 24.6.2 Comparator characteristics = −40 to +105°C: G products, T = −40 to +125°C: M products, 2.4 V ≤ V ≤ 5.5 V, V = 0 V]...

  • Page 749: Spor Circuit Characteristics

    = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T 24.6.4 SPOR circuit characteristics = −40 to +105°C: G products, T = −40 to +125°C: M products, V = 0 V] Item Symbol Condition MIN.

  • Page 750: Ram Data Retention Characteristics

    = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T 24.7 RAM Data Retention Characteristics = −40 to +105°C: G products, T = −40 to +125°C: M products, V = 0 V] Item Symbol Condition MIN.

  • Page 751: Flash Memory Programming Characteristics

    1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics. ...

  • Page 752: 24.10 Timing Of Entry To Flash Memory Programming Mode

    = −40 to +105°C, TA = −40 to +125°C) RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T 24.10 Timing of Entry to Flash Memory Programming Mode  = −40 to +105°C: G products, T = −40 to +125°C: M products, 2.4 V ≤ V ≤...

  • Page 753: Chapter 25 Package Drawings

    RL78/G15 CHAPTER 25 PACKAGE DRAWINGS CHAPTER 25 PACKAGE DRAWINGS  25.1 8-pin products R5F12008MNS, R5F12008GNS, R5F12008ANS R5F12007MNS, R5F12007GNS, R5F12007ANS R01UH0959EJ0110 Rev.1.10 Page 753 of 765 Mar 7, 2023...

  • Page 754: 10-Pin Products

    RL78/G15 CHAPTER 25 PACKAGE DRAWINGS 25.2 10-pin products R5F12018MSP, R5F12018GSP, R5F12018ASP R5F12017MSP, R5F12017GSP, R5F12017ASP R01UH0959EJ0110 Rev.1.10 Page 754 of 765 Mar 7, 2023...

  • Page 755: 16-Pin Products

    RL78/G15 CHAPTER 25 PACKAGE DRAWINGS 25.3 16-pin products R5F12048MSP, R5F12048GSP, R5F12048ASP R5F12047MSP, R5F12047GSP, R5F12047ASP R01UH0959EJ0110 Rev.1.10 Page 755 of 765 Mar 7, 2023...
  • Page 756 RL78/G15 CHAPTER 25 PACKAGE DRAWINGS R5F12048MNA, R5F12048GNA, R5F12048ANA R5F12047MNA, R5F12047GNA, R5F12047ANA R01UH0959EJ0110 Rev.1.10 Page 756 of 765 Mar 7, 2023...

  • Page 757: 20-Pin Products

    RL78/G15 CHAPTER 25 PACKAGE DRAWINGS 25.4 20-pin products R5F12068MSP, R5F12068GSP, R5F12068ASP R5F12067MSP, R5F12067GSP, R5F12067ASP R01UH0959EJ0110 Rev.1.10 Page 757 of 765 Mar 7, 2023...

  • Page 758: Appendix A Revision History

    RL78/G15 APPENDIX A REVISION HISTORY APPENDIX A REVISION HISTORY Major Revisions in This Edition Page Description Classification CHAPTER 1 OUTLINE p.38 to p.41 2.1.1 8-pin products to 2.1.4 20-pin products: The order of pin names in Alternate Function, modified CHAPTER 3 CPU ARCHITECTURE p.55...
  • Page 759 RL78/G15 APPENDIX A REVISION HISTORY Page Description Classification p.729 23.8 Flash Memory Programming Characteristics: The condition was added to the code flash/data flash self-programming time p.730 23.10 Timing of Entry to Flash Memory Programming Mode: The condition, added CHAPTER 24 ELECTRICAL SPECIFICATIONS (T = −40 to +105°C, T...

  • Page 760: Revision History Of Preceding Editions

    Edition Description Chapter Rev.1.00 Figure 1-1. Part Number, Memory Size, and Package of RL78/G15: Packaging CHAPTER 1 OUTLINE specifications, modified Table 1-1. List of Ordering Part Numbers: The ordering part number was changed to list the product name and the packaging specifications in respective columns. RENESAS Code, added.
  • Page 761 RL78/G15 APPENDIX A REVISION HISTORY (2/4) Edition Description Chapter Rev.1.00 4.5.1 Basic concept when using alternate function: The description, modified CHAPTER 4 PORT FUNCTIONS Table 4-7. Setting Examples of Registers and Output Latches When Using Pin Function (3/10): POMp setting for (TxD0) and TxD0, modified Table 4-7.
  • Page 762 RL78/G15 APPENDIX A REVISION HISTORY (3/4) Edition Description Chapter Rev.1.00 13.5.14 Communication reservation: The description in (1) for the wait time, modified CHAPTER 13 SERIAL INTERFACE IICA Figure 13-26. Communication Reservation Procedure: Note 1, modified Figure 13-28. Master Operation in Multi-master System (2/3): Note 1, modified Figure 13-29.
  • Page 763 RL78/G15 APPENDIX A REVISION HISTORY (4/4) Edition Description Chapter Rev.1.00 CHAPTER 23 ELECTRICAL SPECIFICATIONS (T = −40 to +85°C) (Target): Caution 3, CHAPTER 23 ELECTRICAL added SPECIFICATIONS (T = −40 to +85°C) (Target) 23.2.2 On-chip oscillator characteristics: Note 3, added 23.3.2 Supply current characteristics: f...
  • Page 764 Colophon RL78/G15 User’s Manual: Hardware Publication Date: Rev.0.50 Dec 27, 2021 Rev.1.10 Mar 7, 2023 Published by: Renesas Electronics Corporation...
  • Page 765 Back Cover RL78/G15 R01UH0959EJ0110...

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