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M16C/62P Group (M16C/62P, M16C/62PT)
1.6
Pin Description
Table 1.17
Pin Description (100-pin and 128-pin Version) (1)
Signal Name
Pin Name
Power supply
VCC1,VCC2
input
VSS
Analog power
AVCC
supply input
AVSS
Reset input
RESET
CNVSS
CNVSS
External data
BYTE
bus width
select input
Bus control
D0 to D7
(4)
pins
D8 to D15
A0 to A19
A0/D0 to
A7/D7
A1/D0 to
A8/D7
CS0 to CS3
WRL/WR
WRH/BHE
RD
ALE
HOLD
HLDA
RDY
I : Input
O : Output
Power Supply : Power supplies which relate to the external bus pins are separated as VCC2, thus they can be
interfaced using the different voltage as VCC1.
NOTES:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 and VCC2 pins. Also the apply condition is that VCC1 = VCC2.
3. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
4. Bus control pins in M16C/62PT cannot be used.
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
I/O
Power
(3)
Type
Supply
−
I
I
VCC1
I
VCC1
I
VCC1
I
VCC1
I/O
VCC2
I/O
VCC2
O
VCC2
I/O
VCC2
I/O
VCC2
O
VCC2
O
VCC2
O
VCC2
I
VCC2
O
VCC2
I
VCC2
I/O : Input and output
Page 25 of 390
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Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS
pin. The VCC apply condition is that VCC1 ≥ VCC2.
Applies the power supply for the A/D converter. Connect the AVCC
pin to VCC1. Connect the AVSS pin to VSS.
The microcomputer is in a reset state when applying "L" to the this pin.
Switches processor mode. Connect this pin to VSS to when after
a reset to start up in single-chip mode. Connect this pin to VCC1 to
start up in microprocessor mode.
Switches the data bus in external memory space. The data bus is
16 bits long when the this pin is held "L" and 8 bits long when the
this pin is held "H". Set it to either one. Connect this pin to VSS
when an single-chip mode.
Inputs and outputs data (D0 to D7) when these pins are set as the
separate bus.
Inputs and outputs data (D8 to D15) when external 16-bit data bus
is set as the separate bus.
Output address bits (A0 to A19).
Input and output data (D0 to D7) and output address bits (A0 to A7) by
timesharing when external 8-bit data bus are set as the multiplexed bus.
Input and output data (D0 to D7) and output address bits (A1 to A8)
by timesharing when external 16-bit data bus are set as the
multiplexed bus.
Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to
specify an external space.
Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or
BHE and WR can be switched by program.
• WRL, WRH and RD are selected
The WRL signal becomes "L" by writing data to an even address in
an external memory space.
The WRH signal becomes "L" by writing data to an odd address in
an external memory space.
The RD pin signal becomes "L" by reading data in an external
memory space.
• WR, BHE and RD are selected
The WR signal becomes "L" by writing data in an external memory space.
The RD signal becomes "L" by reading data in an external memory space.
The BHE signal becomes "L" by accessing an odd address.
Select WR, BHE and RD for an external 8-bit data bus.
ALE is a signal to latch the address.
While the HOLD pin is held "L", the microcomputer is placed in a
hold state.
In a hold state, HLDA outputs a "L" signal.
While applying a "L" signal to the RDY pin, the microcomputer is
placed in a wait state.
Description
(1, 2)
010-62245566 13810019655
1. Overview
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