Figure 7.36 Example Of Transfer In Single Address Mode Activated By Dreq Low Level - Renesas H8SX/1520 Series Hardware Manual

Section 7 DMA Controller (DMAC)
Activation Timing by DREQ Low Level
(4)
Figure 7.36 shows an example of normal transfer mode activated by the DREQ signal low level.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after completion of the single cycle
and then a low level of the DREQ signal is detected. This operation is repeated until the transfe is
completed.
Bφ
DREQ
Address bus
DACK
DMA
operation
Channel
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
[1]
request is held.
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed after completion of the single cycle.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
Figure 7.36 Example of Transfer in Single Address Mode Activated
Rev. 3.00 Mar. 14, 2006 Page 194 of 804
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Bus
released
Wait
Duration of transfer
request disabled
Request
Min. of 3 cycles
[1]
[2]
DMA single
cycle
Transfer source/
Transfer destination
Single Wait
Request
Min. of 3 cycles
[5]
[3] [4]
Transfer request
enable resumed
by DREQ Low Level
Bus DMA single
released cycle
Transfer source/
Transfer destination
Single
Wait
Duration of transfer
request disabled
[6]
Transfer request
enable resumed
Bus
released
[7]